tegra124-apalis-v1.2.dtsi 57 KB

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  1. // SPDX-License-Identifier: GPL-2.0 OR MIT
  2. /*
  3. * Copyright 2016-2018 Toradex AG
  4. */
  5. #include "tegra124.dtsi"
  6. #include "tegra124-apalis-emc.dtsi"
  7. /*
  8. * Toradex Apalis TK1 Module Device Tree
  9. * Compatible for Revisions 2GB: V1.2A
  10. */
  11. / {
  12. memory@80000000 {
  13. reg = <0x0 0x80000000 0x0 0x80000000>;
  14. };
  15. pcie@1003000 {
  16. status = "okay";
  17. avddio-pex-supply = <&reg_1v05_vdd>;
  18. avdd-pex-pll-supply = <&reg_1v05_vdd>;
  19. avdd-pll-erefe-supply = <&reg_1v05_avdd>;
  20. dvddio-pex-supply = <&reg_1v05_vdd>;
  21. hvdd-pex-pll-e-supply = <&reg_module_3v3>;
  22. hvdd-pex-supply = <&reg_module_3v3>;
  23. vddio-pex-ctl-supply = <&reg_module_3v3>;
  24. /* Apalis PCIe (additional lane Apalis type specific) */
  25. pci@1,0 {
  26. /* PCIE1_RX/TX and TS_DIFF1/2 */
  27. phys = <&{/padctl@7009f000/pads/pcie/lanes/pcie-4}>,
  28. <&{/padctl@7009f000/pads/pcie/lanes/pcie-3}>;
  29. phy-names = "pcie-0", "pcie-1";
  30. };
  31. /* I210 Gigabit Ethernet Controller (On-module) */
  32. pci@2,0 {
  33. phys = <&{/padctl@7009f000/pads/pcie/lanes/pcie-2}>;
  34. phy-names = "pcie-0";
  35. status = "okay";
  36. ethernet@0,0 {
  37. reg = <0 0 0 0 0>;
  38. local-mac-address = [00 00 00 00 00 00];
  39. };
  40. };
  41. };
  42. host1x@50000000 {
  43. hdmi@54280000 {
  44. nvidia,ddc-i2c-bus = <&hdmi_ddc>;
  45. nvidia,hpd-gpio =
  46. <&gpio TEGRA_GPIO(N, 7) GPIO_ACTIVE_HIGH>;
  47. pll-supply = <&reg_1v05_avdd_hdmi_pll>;
  48. vdd-supply = <&reg_3v3_avdd_hdmi>;
  49. };
  50. };
  51. gpu@57000000 {
  52. /*
  53. * Node left disabled on purpose - the bootloader will enable
  54. * it after having set the VPR up
  55. */
  56. vdd-supply = <&reg_vdd_gpu>;
  57. };
  58. pinmux@70000868 {
  59. pinctrl-names = "default";
  60. pinctrl-0 = <&state_default>;
  61. state_default: pinmux {
  62. /* Analogue Audio (On-module) */
  63. dap3-fs-pp0 {
  64. nvidia,pins = "dap3_fs_pp0";
  65. nvidia,function = "i2s2";
  66. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  67. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  68. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  69. };
  70. dap3-din-pp1 {
  71. nvidia,pins = "dap3_din_pp1";
  72. nvidia,function = "i2s2";
  73. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  74. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  75. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  76. };
  77. dap3-dout-pp2 {
  78. nvidia,pins = "dap3_dout_pp2";
  79. nvidia,function = "i2s2";
  80. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  81. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  82. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  83. };
  84. dap3-sclk-pp3 {
  85. nvidia,pins = "dap3_sclk_pp3";
  86. nvidia,function = "i2s2";
  87. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  88. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  89. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  90. };
  91. dap-mclk1-pw4 {
  92. nvidia,pins = "dap_mclk1_pw4";
  93. nvidia,function = "extperiph1";
  94. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  95. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  96. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  97. };
  98. /* Apalis BKL1_ON */
  99. pbb5 {
  100. nvidia,pins = "pbb5";
  101. nvidia,function = "vgp5";
  102. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  103. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  104. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  105. };
  106. /* Apalis BKL1_PWM */
  107. pu6 {
  108. nvidia,pins = "pu6";
  109. nvidia,function = "pwm3";
  110. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  111. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  112. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  113. };
  114. /* Apalis CAM1_MCLK */
  115. cam-mclk-pcc0 {
  116. nvidia,pins = "cam_mclk_pcc0";
  117. nvidia,function = "vi_alt3";
  118. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  119. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  120. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  121. };
  122. /* Apalis Digital Audio */
  123. dap2-fs-pa2 {
  124. nvidia,pins = "dap2_fs_pa2";
  125. nvidia,function = "hda";
  126. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  127. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  128. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  129. };
  130. dap2-sclk-pa3 {
  131. nvidia,pins = "dap2_sclk_pa3";
  132. nvidia,function = "hda";
  133. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  134. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  135. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  136. };
  137. dap2-din-pa4 {
  138. nvidia,pins = "dap2_din_pa4";
  139. nvidia,function = "hda";
  140. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  141. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  142. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  143. };
  144. dap2-dout-pa5 {
  145. nvidia,pins = "dap2_dout_pa5";
  146. nvidia,function = "hda";
  147. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  148. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  149. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  150. };
  151. pbb3 { /* DAP1_RESET */
  152. nvidia,pins = "pbb3";
  153. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  154. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  155. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  156. };
  157. clk3-out-pee0 {
  158. nvidia,pins = "clk3_out_pee0";
  159. nvidia,function = "extperiph3";
  160. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  161. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  162. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  163. };
  164. /* Apalis GPIO */
  165. usb-vbus-en0-pn4 {
  166. nvidia,pins = "usb_vbus_en0_pn4";
  167. nvidia,function = "rsvd2";
  168. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  169. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  170. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  171. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  172. };
  173. usb-vbus-en1-pn5 {
  174. nvidia,pins = "usb_vbus_en1_pn5";
  175. nvidia,function = "rsvd2";
  176. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  177. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  178. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  179. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  180. };
  181. pex-l0-rst-n-pdd1 {
  182. nvidia,pins = "pex_l0_rst_n_pdd1";
  183. nvidia,function = "rsvd2";
  184. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  185. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  186. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  187. };
  188. pex-l0-clkreq-n-pdd2 {
  189. nvidia,pins = "pex_l0_clkreq_n_pdd2";
  190. nvidia,function = "rsvd2";
  191. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  192. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  193. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  194. };
  195. pex-l1-rst-n-pdd5 {
  196. nvidia,pins = "pex_l1_rst_n_pdd5";
  197. nvidia,function = "rsvd2";
  198. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  199. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  200. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  201. };
  202. pex-l1-clkreq-n-pdd6 {
  203. nvidia,pins = "pex_l1_clkreq_n_pdd6";
  204. nvidia,function = "rsvd2";
  205. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  206. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  207. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  208. };
  209. dp-hpd-pff0 {
  210. nvidia,pins = "dp_hpd_pff0";
  211. nvidia,function = "dp";
  212. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  213. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  214. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  215. };
  216. pff2 {
  217. nvidia,pins = "pff2";
  218. nvidia,function = "rsvd2";
  219. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  220. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  221. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  222. };
  223. owr { /* PEX_L1_CLKREQ_N multiplexed GPIO6 */
  224. nvidia,pins = "owr";
  225. nvidia,function = "rsvd2";
  226. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  227. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  228. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  229. nvidia,rcv-sel = <TEGRA_PIN_DISABLE>;
  230. };
  231. /* Apalis HDMI1_CEC */
  232. hdmi-cec-pee3 {
  233. nvidia,pins = "hdmi_cec_pee3";
  234. nvidia,function = "cec";
  235. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  236. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  237. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  238. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  239. };
  240. /* Apalis HDMI1_HPD */
  241. hdmi-int-pn7 {
  242. nvidia,pins = "hdmi_int_pn7";
  243. nvidia,function = "rsvd1";
  244. nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
  245. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  246. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  247. nvidia,rcv-sel = <TEGRA_PIN_DISABLE>;
  248. };
  249. /* Apalis I2C1 */
  250. gen1-i2c-scl-pc4 {
  251. nvidia,pins = "gen1_i2c_scl_pc4";
  252. nvidia,function = "i2c1";
  253. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  254. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  255. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  256. nvidia,open-drain = <TEGRA_PIN_ENABLE>;
  257. };
  258. gen1-i2c-sda-pc5 {
  259. nvidia,pins = "gen1_i2c_sda_pc5";
  260. nvidia,function = "i2c1";
  261. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  262. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  263. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  264. nvidia,open-drain = <TEGRA_PIN_ENABLE>;
  265. };
  266. /* Apalis I2C3 (CAM) */
  267. cam-i2c-scl-pbb1 {
  268. nvidia,pins = "cam_i2c_scl_pbb1";
  269. nvidia,function = "i2c3";
  270. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  271. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  272. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  273. nvidia,open-drain = <TEGRA_PIN_ENABLE>;
  274. };
  275. cam-i2c-sda-pbb2 {
  276. nvidia,pins = "cam_i2c_sda_pbb2";
  277. nvidia,function = "i2c3";
  278. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  279. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  280. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  281. nvidia,open-drain = <TEGRA_PIN_ENABLE>;
  282. };
  283. /* Apalis I2C4 (DDC) */
  284. ddc-scl-pv4 {
  285. nvidia,pins = "ddc_scl_pv4";
  286. nvidia,function = "i2c4";
  287. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  288. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  289. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  290. nvidia,rcv-sel = <TEGRA_PIN_ENABLE>;
  291. };
  292. ddc-sda-pv5 {
  293. nvidia,pins = "ddc_sda_pv5";
  294. nvidia,function = "i2c4";
  295. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  296. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  297. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  298. nvidia,rcv-sel = <TEGRA_PIN_ENABLE>;
  299. };
  300. /* Apalis MMC1 */
  301. sdmmc1-cd-n-pv3 { /* CD# GPIO */
  302. nvidia,pins = "sdmmc1_wp_n_pv3";
  303. nvidia,function = "sdmmc1";
  304. nvidia,pull = <TEGRA_PIN_PULL_UP>;
  305. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  306. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  307. };
  308. clk2-out-pw5 { /* D5 GPIO */
  309. nvidia,pins = "clk2_out_pw5";
  310. nvidia,function = "rsvd2";
  311. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  312. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  313. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  314. };
  315. sdmmc1-dat3-py4 {
  316. nvidia,pins = "sdmmc1_dat3_py4";
  317. nvidia,function = "sdmmc1";
  318. nvidia,pull = <TEGRA_PIN_PULL_UP>;
  319. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  320. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  321. };
  322. sdmmc1-dat2-py5 {
  323. nvidia,pins = "sdmmc1_dat2_py5";
  324. nvidia,function = "sdmmc1";
  325. nvidia,pull = <TEGRA_PIN_PULL_UP>;
  326. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  327. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  328. };
  329. sdmmc1-dat1-py6 {
  330. nvidia,pins = "sdmmc1_dat1_py6";
  331. nvidia,function = "sdmmc1";
  332. nvidia,pull = <TEGRA_PIN_PULL_UP>;
  333. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  334. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  335. };
  336. sdmmc1-dat0-py7 {
  337. nvidia,pins = "sdmmc1_dat0_py7";
  338. nvidia,function = "sdmmc1";
  339. nvidia,pull = <TEGRA_PIN_PULL_UP>;
  340. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  341. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  342. };
  343. sdmmc1-clk-pz0 {
  344. nvidia,pins = "sdmmc1_clk_pz0";
  345. nvidia,function = "sdmmc1";
  346. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  347. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  348. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  349. };
  350. sdmmc1-cmd-pz1 {
  351. nvidia,pins = "sdmmc1_cmd_pz1";
  352. nvidia,function = "sdmmc1";
  353. nvidia,pull = <TEGRA_PIN_PULL_UP>;
  354. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  355. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  356. };
  357. clk2-req-pcc5 { /* D4 GPIO */
  358. nvidia,pins = "clk2_req_pcc5";
  359. nvidia,function = "rsvd2";
  360. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  361. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  362. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  363. };
  364. sdmmc3-clk-lb-in-pee5 { /* D6 GPIO */
  365. nvidia,pins = "sdmmc3_clk_lb_in_pee5";
  366. nvidia,function = "rsvd2";
  367. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  368. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  369. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  370. };
  371. usb-vbus-en2-pff1 { /* D7 GPIO */
  372. nvidia,pins = "usb_vbus_en2_pff1";
  373. nvidia,function = "rsvd2";
  374. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  375. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  376. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  377. };
  378. /* Apalis PWM */
  379. ph0 {
  380. nvidia,pins = "ph0";
  381. nvidia,function = "pwm0";
  382. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  383. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  384. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  385. };
  386. ph1 {
  387. nvidia,pins = "ph1";
  388. nvidia,function = "pwm1";
  389. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  390. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  391. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  392. };
  393. ph2 {
  394. nvidia,pins = "ph2";
  395. nvidia,function = "pwm2";
  396. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  397. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  398. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  399. };
  400. /* PWM3 active on pu6 being Apalis BKL1_PWM as well */
  401. ph3 {
  402. nvidia,pins = "ph3";
  403. nvidia,function = "pwm3";
  404. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  405. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  406. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  407. };
  408. /* Apalis SATA1_ACT# */
  409. dap1-dout-pn2 {
  410. nvidia,pins = "dap1_dout_pn2";
  411. nvidia,function = "gmi";
  412. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  413. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  414. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  415. };
  416. /* Apalis SD1 */
  417. sdmmc3-clk-pa6 {
  418. nvidia,pins = "sdmmc3_clk_pa6";
  419. nvidia,function = "sdmmc3";
  420. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  421. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  422. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  423. };
  424. sdmmc3-cmd-pa7 {
  425. nvidia,pins = "sdmmc3_cmd_pa7";
  426. nvidia,function = "sdmmc3";
  427. nvidia,pull = <TEGRA_PIN_PULL_UP>;
  428. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  429. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  430. };
  431. sdmmc3-dat3-pb4 {
  432. nvidia,pins = "sdmmc3_dat3_pb4";
  433. nvidia,function = "sdmmc3";
  434. nvidia,pull = <TEGRA_PIN_PULL_UP>;
  435. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  436. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  437. };
  438. sdmmc3-dat2-pb5 {
  439. nvidia,pins = "sdmmc3_dat2_pb5";
  440. nvidia,function = "sdmmc3";
  441. nvidia,pull = <TEGRA_PIN_PULL_UP>;
  442. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  443. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  444. };
  445. sdmmc3-dat1-pb6 {
  446. nvidia,pins = "sdmmc3_dat1_pb6";
  447. nvidia,function = "sdmmc3";
  448. nvidia,pull = <TEGRA_PIN_PULL_UP>;
  449. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  450. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  451. };
  452. sdmmc3-dat0-pb7 {
  453. nvidia,pins = "sdmmc3_dat0_pb7";
  454. nvidia,function = "sdmmc3";
  455. nvidia,pull = <TEGRA_PIN_PULL_UP>;
  456. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  457. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  458. };
  459. sdmmc3-cd-n-pv2 { /* CD# GPIO */
  460. nvidia,pins = "sdmmc3_cd_n_pv2";
  461. nvidia,function = "rsvd3";
  462. nvidia,pull = <TEGRA_PIN_PULL_UP>;
  463. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  464. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  465. };
  466. /* Apalis SPDIF */
  467. spdif-out-pk5 {
  468. nvidia,pins = "spdif_out_pk5";
  469. nvidia,function = "spdif";
  470. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  471. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  472. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  473. };
  474. spdif-in-pk6 {
  475. nvidia,pins = "spdif_in_pk6";
  476. nvidia,function = "spdif";
  477. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  478. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  479. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  480. };
  481. /* Apalis SPI1 */
  482. ulpi-clk-py0 {
  483. nvidia,pins = "ulpi_clk_py0";
  484. nvidia,function = "spi1";
  485. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  486. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  487. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  488. };
  489. ulpi-dir-py1 {
  490. nvidia,pins = "ulpi_dir_py1";
  491. nvidia,function = "spi1";
  492. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  493. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  494. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  495. };
  496. ulpi-nxt-py2 {
  497. nvidia,pins = "ulpi_nxt_py2";
  498. nvidia,function = "spi1";
  499. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  500. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  501. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  502. };
  503. ulpi-stp-py3 {
  504. nvidia,pins = "ulpi_stp_py3";
  505. nvidia,function = "spi1";
  506. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  507. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  508. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  509. };
  510. /* Apalis SPI2 */
  511. pg5 {
  512. nvidia,pins = "pg5";
  513. nvidia,function = "spi4";
  514. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  515. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  516. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  517. };
  518. pg6 {
  519. nvidia,pins = "pg6";
  520. nvidia,function = "spi4";
  521. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  522. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  523. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  524. };
  525. pg7 {
  526. nvidia,pins = "pg7";
  527. nvidia,function = "spi4";
  528. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  529. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  530. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  531. };
  532. pi3 {
  533. nvidia,pins = "pi3";
  534. nvidia,function = "spi4";
  535. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  536. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  537. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  538. };
  539. /* Apalis UART1 */
  540. pb1 { /* DCD GPIO */
  541. nvidia,pins = "pb1";
  542. nvidia,function = "rsvd2";
  543. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  544. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  545. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  546. };
  547. pk7 { /* RI GPIO */
  548. nvidia,pins = "pk7";
  549. nvidia,function = "rsvd2";
  550. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  551. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  552. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  553. };
  554. uart1-txd-pu0 {
  555. nvidia,pins = "pu0";
  556. nvidia,function = "uarta";
  557. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  558. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  559. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  560. };
  561. uart1-rxd-pu1 {
  562. nvidia,pins = "pu1";
  563. nvidia,function = "uarta";
  564. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  565. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  566. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  567. };
  568. uart1-cts-n-pu2 {
  569. nvidia,pins = "pu2";
  570. nvidia,function = "uarta";
  571. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  572. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  573. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  574. };
  575. uart1-rts-n-pu3 {
  576. nvidia,pins = "pu3";
  577. nvidia,function = "uarta";
  578. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  579. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  580. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  581. };
  582. uart3-cts-n-pa1 { /* DSR GPIO */
  583. nvidia,pins = "uart3_cts_n_pa1";
  584. nvidia,function = "gmi";
  585. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  586. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  587. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  588. };
  589. uart3-rts-n-pc0 { /* DTR GPIO */
  590. nvidia,pins = "uart3_rts_n_pc0";
  591. nvidia,function = "gmi";
  592. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  593. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  594. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  595. };
  596. /* Apalis UART2 */
  597. uart2-txd-pc2 {
  598. nvidia,pins = "uart2_txd_pc2";
  599. nvidia,function = "irda";
  600. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  601. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  602. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  603. };
  604. uart2-rxd-pc3 {
  605. nvidia,pins = "uart2_rxd_pc3";
  606. nvidia,function = "irda";
  607. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  608. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  609. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  610. };
  611. uart2-cts-n-pj5 {
  612. nvidia,pins = "uart2_cts_n_pj5";
  613. nvidia,function = "uartb";
  614. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  615. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  616. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  617. };
  618. uart2-rts-n-pj6 {
  619. nvidia,pins = "uart2_rts_n_pj6";
  620. nvidia,function = "uartb";
  621. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  622. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  623. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  624. };
  625. /* Apalis UART3 */
  626. uart3-txd-pw6 {
  627. nvidia,pins = "uart3_txd_pw6";
  628. nvidia,function = "uartc";
  629. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  630. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  631. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  632. };
  633. uart3-rxd-pw7 {
  634. nvidia,pins = "uart3_rxd_pw7";
  635. nvidia,function = "uartc";
  636. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  637. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  638. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  639. };
  640. /* Apalis UART4 */
  641. uart4-rxd-pb0 {
  642. nvidia,pins = "pb0";
  643. nvidia,function = "uartd";
  644. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  645. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  646. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  647. };
  648. uart4-txd-pj7 {
  649. nvidia,pins = "pj7";
  650. nvidia,function = "uartd";
  651. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  652. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  653. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  654. };
  655. /* Apalis USBH_EN */
  656. gen2-i2c-sda-pt6 {
  657. nvidia,pins = "gen2_i2c_sda_pt6";
  658. nvidia,function = "rsvd2";
  659. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  660. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  661. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  662. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  663. };
  664. /* Apalis USBH_OC# */
  665. pbb0 {
  666. nvidia,pins = "pbb0";
  667. nvidia,function = "vgp6";
  668. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  669. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  670. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  671. };
  672. /* Apalis USBO1_EN */
  673. gen2-i2c-scl-pt5 {
  674. nvidia,pins = "gen2_i2c_scl_pt5";
  675. nvidia,function = "rsvd2";
  676. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  677. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  678. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  679. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  680. };
  681. /* Apalis USBO1_OC# */
  682. pbb4 {
  683. nvidia,pins = "pbb4";
  684. nvidia,function = "vgp4";
  685. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  686. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  687. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  688. };
  689. /* Apalis WAKE1_MICO */
  690. pex-wake-n-pdd3 {
  691. nvidia,pins = "pex_wake_n_pdd3";
  692. nvidia,function = "rsvd2";
  693. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  694. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  695. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  696. };
  697. /* CORE_PWR_REQ */
  698. core-pwr-req {
  699. nvidia,pins = "core_pwr_req";
  700. nvidia,function = "pwron";
  701. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  702. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  703. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  704. };
  705. /* CPU_PWR_REQ */
  706. cpu-pwr-req {
  707. nvidia,pins = "cpu_pwr_req";
  708. nvidia,function = "cpu";
  709. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  710. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  711. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  712. };
  713. /* DVFS */
  714. dvfs-pwm-px0 {
  715. nvidia,pins = "dvfs_pwm_px0";
  716. nvidia,function = "cldvfs";
  717. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  718. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  719. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  720. };
  721. dvfs-clk-px2 {
  722. nvidia,pins = "dvfs_clk_px2";
  723. nvidia,function = "cldvfs";
  724. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  725. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  726. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  727. };
  728. /* eMMC */
  729. sdmmc4-dat0-paa0 {
  730. nvidia,pins = "sdmmc4_dat0_paa0";
  731. nvidia,function = "sdmmc4";
  732. nvidia,pull = <TEGRA_PIN_PULL_UP>;
  733. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  734. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  735. };
  736. sdmmc4-dat1-paa1 {
  737. nvidia,pins = "sdmmc4_dat1_paa1";
  738. nvidia,function = "sdmmc4";
  739. nvidia,pull = <TEGRA_PIN_PULL_UP>;
  740. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  741. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  742. };
  743. sdmmc4-dat2-paa2 {
  744. nvidia,pins = "sdmmc4_dat2_paa2";
  745. nvidia,function = "sdmmc4";
  746. nvidia,pull = <TEGRA_PIN_PULL_UP>;
  747. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  748. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  749. };
  750. sdmmc4-dat3-paa3 {
  751. nvidia,pins = "sdmmc4_dat3_paa3";
  752. nvidia,function = "sdmmc4";
  753. nvidia,pull = <TEGRA_PIN_PULL_UP>;
  754. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  755. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  756. };
  757. sdmmc4-dat4-paa4 {
  758. nvidia,pins = "sdmmc4_dat4_paa4";
  759. nvidia,function = "sdmmc4";
  760. nvidia,pull = <TEGRA_PIN_PULL_UP>;
  761. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  762. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  763. };
  764. sdmmc4-dat5-paa5 {
  765. nvidia,pins = "sdmmc4_dat5_paa5";
  766. nvidia,function = "sdmmc4";
  767. nvidia,pull = <TEGRA_PIN_PULL_UP>;
  768. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  769. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  770. };
  771. sdmmc4-dat6-paa6 {
  772. nvidia,pins = "sdmmc4_dat6_paa6";
  773. nvidia,function = "sdmmc4";
  774. nvidia,pull = <TEGRA_PIN_PULL_UP>;
  775. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  776. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  777. };
  778. sdmmc4-dat7-paa7 {
  779. nvidia,pins = "sdmmc4_dat7_paa7";
  780. nvidia,function = "sdmmc4";
  781. nvidia,pull = <TEGRA_PIN_PULL_UP>;
  782. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  783. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  784. };
  785. sdmmc4-clk-pcc4 {
  786. nvidia,pins = "sdmmc4_clk_pcc4";
  787. nvidia,function = "sdmmc4";
  788. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  789. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  790. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  791. };
  792. sdmmc4-cmd-pt7 {
  793. nvidia,pins = "sdmmc4_cmd_pt7";
  794. nvidia,function = "sdmmc4";
  795. nvidia,pull = <TEGRA_PIN_PULL_UP>;
  796. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  797. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  798. };
  799. /* JTAG_RTCK */
  800. jtag-rtck {
  801. nvidia,pins = "jtag_rtck";
  802. nvidia,function = "rtck";
  803. nvidia,pull = <TEGRA_PIN_PULL_UP>;
  804. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  805. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  806. };
  807. /* LAN_DEV_OFF# */
  808. ulpi-data5-po6 {
  809. nvidia,pins = "ulpi_data5_po6";
  810. nvidia,function = "ulpi";
  811. nvidia,pull = <TEGRA_PIN_PULL_UP>;
  812. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  813. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  814. };
  815. /* LAN_RESET# */
  816. kb-row10-ps2 {
  817. nvidia,pins = "kb_row10_ps2";
  818. nvidia,function = "rsvd2";
  819. nvidia,pull = <TEGRA_PIN_PULL_UP>;
  820. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  821. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  822. };
  823. /* LAN_WAKE# */
  824. ulpi-data4-po5 {
  825. nvidia,pins = "ulpi_data4_po5";
  826. nvidia,function = "ulpi";
  827. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  828. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  829. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  830. };
  831. /* MCU_INT1# */
  832. pk2 {
  833. nvidia,pins = "pk2";
  834. nvidia,function = "rsvd1";
  835. nvidia,pull = <TEGRA_PIN_PULL_UP>;
  836. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  837. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  838. };
  839. /* MCU_INT2# */
  840. pj2 {
  841. nvidia,pins = "pj2";
  842. nvidia,function = "rsvd1";
  843. nvidia,pull = <TEGRA_PIN_PULL_UP>;
  844. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  845. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  846. };
  847. /* MCU_INT3# */
  848. pi5 {
  849. nvidia,pins = "pi5";
  850. nvidia,function = "rsvd2";
  851. nvidia,pull = <TEGRA_PIN_PULL_UP>;
  852. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  853. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  854. };
  855. /* MCU_INT4# */
  856. pj0 {
  857. nvidia,pins = "pj0";
  858. nvidia,function = "rsvd1";
  859. nvidia,pull = <TEGRA_PIN_PULL_UP>;
  860. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  861. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  862. };
  863. /* MCU_RESET */
  864. pbb6 {
  865. nvidia,pins = "pbb6";
  866. nvidia,function = "rsvd2";
  867. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  868. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  869. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  870. };
  871. /* MCU SPI */
  872. gpio-x4-aud-px4 {
  873. nvidia,pins = "gpio_x4_aud_px4";
  874. nvidia,function = "spi2";
  875. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  876. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  877. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  878. };
  879. gpio-x5-aud-px5 {
  880. nvidia,pins = "gpio_x5_aud_px5";
  881. nvidia,function = "spi2";
  882. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  883. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  884. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  885. };
  886. gpio-x6-aud-px6 { /* MCU_CS */
  887. nvidia,pins = "gpio_x6_aud_px6";
  888. nvidia,function = "spi2";
  889. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  890. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  891. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  892. };
  893. gpio-x7-aud-px7 {
  894. nvidia,pins = "gpio_x7_aud_px7";
  895. nvidia,function = "spi2";
  896. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  897. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  898. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  899. };
  900. gpio-w2-aud-pw2 { /* MCU_CSEZP */
  901. nvidia,pins = "gpio_w2_aud_pw2";
  902. nvidia,function = "spi2";
  903. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  904. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  905. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  906. };
  907. /* PMIC_CLK_32K */
  908. clk-32k-in {
  909. nvidia,pins = "clk_32k_in";
  910. nvidia,function = "clk";
  911. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  912. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  913. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  914. };
  915. /* PMIC_CPU_OC_INT */
  916. clk-32k-out-pa0 {
  917. nvidia,pins = "clk_32k_out_pa0";
  918. nvidia,function = "soc";
  919. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  920. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  921. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  922. };
  923. /* PWR_I2C */
  924. pwr-i2c-scl-pz6 {
  925. nvidia,pins = "pwr_i2c_scl_pz6";
  926. nvidia,function = "i2cpwr";
  927. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  928. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  929. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  930. nvidia,open-drain = <TEGRA_PIN_ENABLE>;
  931. };
  932. pwr-i2c-sda-pz7 {
  933. nvidia,pins = "pwr_i2c_sda_pz7";
  934. nvidia,function = "i2cpwr";
  935. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  936. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  937. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  938. nvidia,open-drain = <TEGRA_PIN_ENABLE>;
  939. };
  940. /* PWR_INT_N */
  941. pwr-int-n {
  942. nvidia,pins = "pwr_int_n";
  943. nvidia,function = "pmi";
  944. nvidia,pull = <TEGRA_PIN_PULL_UP>;
  945. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  946. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  947. };
  948. /* RESET_MOCI_CTRL */
  949. pu4 {
  950. nvidia,pins = "pu4";
  951. nvidia,function = "gmi";
  952. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  953. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  954. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  955. };
  956. /* RESET_OUT_N */
  957. reset-out-n {
  958. nvidia,pins = "reset_out_n";
  959. nvidia,function = "reset_out_n";
  960. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  961. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  962. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  963. };
  964. /* SHIFT_CTRL_DIR_IN */
  965. kb-row0-pr0 {
  966. nvidia,pins = "kb_row0_pr0";
  967. nvidia,function = "rsvd2";
  968. nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
  969. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  970. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  971. };
  972. kb-row1-pr1 {
  973. nvidia,pins = "kb_row1_pr1";
  974. nvidia,function = "rsvd2";
  975. nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
  976. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  977. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  978. };
  979. /* Configure level-shifter as output for HDA */
  980. kb-row11-ps3 {
  981. nvidia,pins = "kb_row11_ps3";
  982. nvidia,function = "rsvd2";
  983. nvidia,pull = <TEGRA_PIN_PULL_UP>;
  984. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  985. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  986. };
  987. /* SHIFT_CTRL_DIR_OUT */
  988. kb-col5-pq5 {
  989. nvidia,pins = "kb_col5_pq5";
  990. nvidia,function = "rsvd2";
  991. nvidia,pull = <TEGRA_PIN_PULL_UP>;
  992. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  993. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  994. };
  995. kb-col6-pq6 {
  996. nvidia,pins = "kb_col6_pq6";
  997. nvidia,function = "rsvd2";
  998. nvidia,pull = <TEGRA_PIN_PULL_UP>;
  999. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  1000. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  1001. };
  1002. kb-col7-pq7 {
  1003. nvidia,pins = "kb_col7_pq7";
  1004. nvidia,function = "rsvd2";
  1005. nvidia,pull = <TEGRA_PIN_PULL_UP>;
  1006. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  1007. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  1008. };
  1009. /* SHIFT_CTRL_OE */
  1010. kb-col0-pq0 {
  1011. nvidia,pins = "kb_col0_pq0";
  1012. nvidia,function = "rsvd2";
  1013. nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
  1014. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  1015. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  1016. };
  1017. kb-col1-pq1 {
  1018. nvidia,pins = "kb_col1_pq1";
  1019. nvidia,function = "rsvd2";
  1020. nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
  1021. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  1022. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  1023. };
  1024. kb-col2-pq2 {
  1025. nvidia,pins = "kb_col2_pq2";
  1026. nvidia,function = "rsvd2";
  1027. nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
  1028. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  1029. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  1030. };
  1031. kb-col4-pq4 {
  1032. nvidia,pins = "kb_col4_pq4";
  1033. nvidia,function = "kbc";
  1034. nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
  1035. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  1036. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  1037. };
  1038. kb-row2-pr2 {
  1039. nvidia,pins = "kb_row2_pr2";
  1040. nvidia,function = "rsvd2";
  1041. nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
  1042. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  1043. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  1044. };
  1045. /* GPIO_PI6 aka TMP451 ALERT#/THERM2# */
  1046. pi6 {
  1047. nvidia,pins = "pi6";
  1048. nvidia,function = "rsvd1";
  1049. nvidia,pull = <TEGRA_PIN_PULL_UP>;
  1050. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  1051. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  1052. };
  1053. /* TOUCH_INT */
  1054. gpio-w3-aud-pw3 {
  1055. nvidia,pins = "gpio_w3_aud_pw3";
  1056. nvidia,function = "spi6";
  1057. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  1058. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  1059. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  1060. };
  1061. pc7 { /* NC */
  1062. nvidia,pins = "pc7";
  1063. nvidia,function = "rsvd1";
  1064. nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
  1065. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  1066. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  1067. };
  1068. pg0 { /* NC */
  1069. nvidia,pins = "pg0";
  1070. nvidia,function = "rsvd1";
  1071. nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
  1072. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  1073. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  1074. };
  1075. pg1 { /* NC */
  1076. nvidia,pins = "pg1";
  1077. nvidia,function = "rsvd1";
  1078. nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
  1079. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  1080. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  1081. };
  1082. pg2 { /* NC */
  1083. nvidia,pins = "pg2";
  1084. nvidia,function = "rsvd1";
  1085. nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
  1086. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  1087. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  1088. };
  1089. pg3 { /* NC */
  1090. nvidia,pins = "pg3";
  1091. nvidia,function = "rsvd1";
  1092. nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
  1093. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  1094. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  1095. };
  1096. pg4 { /* NC */
  1097. nvidia,pins = "pg4";
  1098. nvidia,function = "rsvd1";
  1099. nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
  1100. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  1101. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  1102. };
  1103. ph4 { /* NC */
  1104. nvidia,pins = "ph4";
  1105. nvidia,function = "rsvd2";
  1106. nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
  1107. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  1108. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  1109. };
  1110. ph5 { /* NC */
  1111. nvidia,pins = "ph5";
  1112. nvidia,function = "rsvd2";
  1113. nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
  1114. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  1115. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  1116. };
  1117. ph6 { /* NC */
  1118. nvidia,pins = "ph6";
  1119. nvidia,function = "gmi";
  1120. nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
  1121. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  1122. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  1123. };
  1124. ph7 { /* NC */
  1125. nvidia,pins = "ph7";
  1126. nvidia,function = "gmi";
  1127. nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
  1128. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  1129. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  1130. };
  1131. pi0 { /* NC */
  1132. nvidia,pins = "pi0";
  1133. nvidia,function = "rsvd1";
  1134. nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
  1135. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  1136. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  1137. };
  1138. pi1 { /* NC */
  1139. nvidia,pins = "pi1";
  1140. nvidia,function = "rsvd1";
  1141. nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
  1142. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  1143. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  1144. };
  1145. pi2 { /* NC */
  1146. nvidia,pins = "pi2";
  1147. nvidia,function = "rsvd4";
  1148. nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
  1149. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  1150. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  1151. };
  1152. pi4 { /* NC */
  1153. nvidia,pins = "pi4";
  1154. nvidia,function = "gmi";
  1155. nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
  1156. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  1157. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  1158. };
  1159. pi7 { /* NC */
  1160. nvidia,pins = "pi7";
  1161. nvidia,function = "rsvd1";
  1162. nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
  1163. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  1164. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  1165. };
  1166. pk0 { /* NC */
  1167. nvidia,pins = "pk0";
  1168. nvidia,function = "rsvd1";
  1169. nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
  1170. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  1171. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  1172. };
  1173. pk1 { /* NC */
  1174. nvidia,pins = "pk1";
  1175. nvidia,function = "rsvd4";
  1176. nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
  1177. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  1178. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  1179. };
  1180. pk3 { /* NC */
  1181. nvidia,pins = "pk3";
  1182. nvidia,function = "gmi";
  1183. nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
  1184. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  1185. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  1186. };
  1187. pk4 { /* NC */
  1188. nvidia,pins = "pk4";
  1189. nvidia,function = "rsvd2";
  1190. nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
  1191. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  1192. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  1193. };
  1194. dap1-fs-pn0 { /* NC */
  1195. nvidia,pins = "dap1_fs_pn0";
  1196. nvidia,function = "rsvd4";
  1197. nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
  1198. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  1199. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  1200. };
  1201. dap1-din-pn1 { /* NC */
  1202. nvidia,pins = "dap1_din_pn1";
  1203. nvidia,function = "rsvd4";
  1204. nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
  1205. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  1206. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  1207. };
  1208. dap1-sclk-pn3 { /* NC */
  1209. nvidia,pins = "dap1_sclk_pn3";
  1210. nvidia,function = "rsvd4";
  1211. nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
  1212. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  1213. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  1214. };
  1215. ulpi-data7-po0 { /* NC */
  1216. nvidia,pins = "ulpi_data7_po0";
  1217. nvidia,function = "ulpi";
  1218. nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
  1219. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  1220. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  1221. };
  1222. ulpi-data0-po1 { /* NC */
  1223. nvidia,pins = "ulpi_data0_po1";
  1224. nvidia,function = "ulpi";
  1225. nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
  1226. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  1227. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  1228. };
  1229. ulpi-data1-po2 { /* NC */
  1230. nvidia,pins = "ulpi_data1_po2";
  1231. nvidia,function = "ulpi";
  1232. nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
  1233. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  1234. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  1235. };
  1236. ulpi-data2-po3 { /* NC */
  1237. nvidia,pins = "ulpi_data2_po3";
  1238. nvidia,function = "ulpi";
  1239. nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
  1240. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  1241. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  1242. };
  1243. ulpi-data3-po4 { /* NC */
  1244. nvidia,pins = "ulpi_data3_po4";
  1245. nvidia,function = "ulpi";
  1246. nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
  1247. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  1248. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  1249. };
  1250. ulpi-data6-po7 { /* NC */
  1251. nvidia,pins = "ulpi_data6_po7";
  1252. nvidia,function = "ulpi";
  1253. nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
  1254. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  1255. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  1256. };
  1257. dap4-fs-pp4 { /* NC */
  1258. nvidia,pins = "dap4_fs_pp4";
  1259. nvidia,function = "rsvd4";
  1260. nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
  1261. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  1262. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  1263. };
  1264. dap4-din-pp5 { /* NC */
  1265. nvidia,pins = "dap4_din_pp5";
  1266. nvidia,function = "rsvd3";
  1267. nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
  1268. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  1269. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  1270. };
  1271. dap4-dout-pp6 { /* NC */
  1272. nvidia,pins = "dap4_dout_pp6";
  1273. nvidia,function = "rsvd4";
  1274. nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
  1275. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  1276. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  1277. };
  1278. dap4-sclk-pp7 { /* NC */
  1279. nvidia,pins = "dap4_sclk_pp7";
  1280. nvidia,function = "rsvd3";
  1281. nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
  1282. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  1283. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  1284. };
  1285. kb-col3-pq3 { /* NC */
  1286. nvidia,pins = "kb_col3_pq3";
  1287. nvidia,function = "kbc";
  1288. nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
  1289. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  1290. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  1291. };
  1292. kb-row3-pr3 { /* NC */
  1293. nvidia,pins = "kb_row3_pr3";
  1294. nvidia,function = "kbc";
  1295. nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
  1296. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  1297. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  1298. };
  1299. kb-row4-pr4 { /* NC */
  1300. nvidia,pins = "kb_row4_pr4";
  1301. nvidia,function = "rsvd3";
  1302. nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
  1303. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  1304. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  1305. };
  1306. kb-row5-pr5 { /* NC */
  1307. nvidia,pins = "kb_row5_pr5";
  1308. nvidia,function = "rsvd3";
  1309. nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
  1310. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  1311. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  1312. };
  1313. kb-row6-pr6 { /* NC */
  1314. nvidia,pins = "kb_row6_pr6";
  1315. nvidia,function = "kbc";
  1316. nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
  1317. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  1318. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  1319. };
  1320. kb-row7-pr7 { /* NC */
  1321. nvidia,pins = "kb_row7_pr7";
  1322. nvidia,function = "rsvd2";
  1323. nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
  1324. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  1325. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  1326. };
  1327. kb-row8-ps0 { /* NC */
  1328. nvidia,pins = "kb_row8_ps0";
  1329. nvidia,function = "rsvd2";
  1330. nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
  1331. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  1332. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  1333. };
  1334. kb-row9-ps1 { /* NC */
  1335. nvidia,pins = "kb_row9_ps1";
  1336. nvidia,function = "rsvd2";
  1337. nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
  1338. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  1339. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  1340. };
  1341. kb-row12-ps4 { /* NC */
  1342. nvidia,pins = "kb_row12_ps4";
  1343. nvidia,function = "rsvd2";
  1344. nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
  1345. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  1346. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  1347. };
  1348. kb-row13-ps5 { /* NC */
  1349. nvidia,pins = "kb_row13_ps5";
  1350. nvidia,function = "rsvd2";
  1351. nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
  1352. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  1353. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  1354. };
  1355. kb-row14-ps6 { /* NC */
  1356. nvidia,pins = "kb_row14_ps6";
  1357. nvidia,function = "rsvd2";
  1358. nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
  1359. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  1360. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  1361. };
  1362. kb-row15-ps7 { /* NC */
  1363. nvidia,pins = "kb_row15_ps7";
  1364. nvidia,function = "rsvd3";
  1365. nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
  1366. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  1367. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  1368. };
  1369. kb-row16-pt0 { /* NC */
  1370. nvidia,pins = "kb_row16_pt0";
  1371. nvidia,function = "rsvd2";
  1372. nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
  1373. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  1374. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  1375. };
  1376. kb-row17-pt1 { /* NC */
  1377. nvidia,pins = "kb_row17_pt1";
  1378. nvidia,function = "rsvd2";
  1379. nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
  1380. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  1381. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  1382. };
  1383. pu5 { /* NC */
  1384. nvidia,pins = "pu5";
  1385. nvidia,function = "gmi";
  1386. nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
  1387. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  1388. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  1389. };
  1390. /*
  1391. * PCB Version Indication: V1.2 and later have GPIO_PV0
  1392. * wired to GND, was NC before
  1393. */
  1394. pv0 {
  1395. nvidia,pins = "pv0";
  1396. nvidia,function = "rsvd1";
  1397. nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
  1398. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  1399. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  1400. };
  1401. pv1 { /* NC */
  1402. nvidia,pins = "pv1";
  1403. nvidia,function = "rsvd1";
  1404. nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
  1405. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  1406. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  1407. };
  1408. gpio-x1-aud-px1 { /* NC */
  1409. nvidia,pins = "gpio_x1_aud_px1";
  1410. nvidia,function = "rsvd2";
  1411. nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
  1412. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  1413. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  1414. };
  1415. gpio-x3-aud-px3 { /* NC */
  1416. nvidia,pins = "gpio_x3_aud_px3";
  1417. nvidia,function = "rsvd4";
  1418. nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
  1419. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  1420. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  1421. };
  1422. pbb7 { /* NC */
  1423. nvidia,pins = "pbb7";
  1424. nvidia,function = "rsvd2";
  1425. nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
  1426. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  1427. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  1428. };
  1429. pcc1 { /* NC */
  1430. nvidia,pins = "pcc1";
  1431. nvidia,function = "rsvd2";
  1432. nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
  1433. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  1434. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  1435. };
  1436. pcc2 { /* NC */
  1437. nvidia,pins = "pcc2";
  1438. nvidia,function = "rsvd2";
  1439. nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
  1440. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  1441. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  1442. };
  1443. clk3-req-pee1 { /* NC */
  1444. nvidia,pins = "clk3_req_pee1";
  1445. nvidia,function = "rsvd2";
  1446. nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
  1447. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  1448. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  1449. };
  1450. dap-mclk1-req-pee2 { /* NC */
  1451. nvidia,pins = "dap_mclk1_req_pee2";
  1452. nvidia,function = "rsvd4";
  1453. nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
  1454. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  1455. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  1456. };
  1457. /*
  1458. * Leave SDMMC3_CLK_LB_OUT muxed as SDMMC3 with output
  1459. * driver enabled aka not tristated and input driver
  1460. * enabled as well as it features some magic properties
  1461. * even though the external loopback is disabled and the
  1462. * internal loopback used as per
  1463. * SDMMC_VENDOR_MISC_CNTRL_0 register's SDMMC_SPARE1
  1464. * bits being set to 0xfffd according to the TRM!
  1465. */
  1466. sdmmc3-clk-lb-out-pee4 { /* NC */
  1467. nvidia,pins = "sdmmc3_clk_lb_out_pee4";
  1468. nvidia,function = "sdmmc3";
  1469. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  1470. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  1471. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  1472. };
  1473. };
  1474. };
  1475. serial@70006040 {
  1476. compatible = "nvidia,tegra124-hsuart", "nvidia,tegra30-hsuart";
  1477. /delete-property/ reg-shift;
  1478. };
  1479. serial@70006200 {
  1480. compatible = "nvidia,tegra124-hsuart", "nvidia,tegra30-hsuart";
  1481. /delete-property/ reg-shift;
  1482. };
  1483. serial@70006300 {
  1484. compatible = "nvidia,tegra124-hsuart", "nvidia,tegra30-hsuart";
  1485. /delete-property/ reg-shift;
  1486. };
  1487. hdmi_ddc: i2c@7000c700 {
  1488. clock-frequency = <10000>;
  1489. };
  1490. /* PWR_I2C: power I2C to audio codec, PMIC and temperature sensor */
  1491. i2c@7000d000 {
  1492. status = "okay";
  1493. clock-frequency = <400000>;
  1494. /* SGTL5000 audio codec */
  1495. sgtl5000: codec@a {
  1496. compatible = "fsl,sgtl5000";
  1497. reg = <0x0a>;
  1498. #sound-dai-cells = <0>;
  1499. VDDA-supply = <&reg_module_3v3_audio>;
  1500. VDDD-supply = <&reg_1v8_vddio>;
  1501. VDDIO-supply = <&reg_1v8_vddio>;
  1502. clocks = <&tegra_car TEGRA124_CLK_EXTERN1>;
  1503. };
  1504. pmic: pmic@40 {
  1505. compatible = "ams,as3722";
  1506. reg = <0x40>;
  1507. interrupts = <0 86 IRQ_TYPE_LEVEL_HIGH>;
  1508. ams,system-power-controller;
  1509. #interrupt-cells = <2>;
  1510. interrupt-controller;
  1511. gpio-controller;
  1512. #gpio-cells = <2>;
  1513. pinctrl-names = "default";
  1514. pinctrl-0 = <&as3722_default>;
  1515. as3722_default: pinmux {
  1516. gpio2-7 {
  1517. pins = "gpio2", /* PWR_EN_+V3.3 */
  1518. "gpio7"; /* +V1.6_LPO */
  1519. function = "gpio";
  1520. bias-pull-up;
  1521. };
  1522. gpio0-1-3-4-5-6 {
  1523. pins = "gpio0", "gpio1", "gpio3",
  1524. "gpio4", "gpio5", "gpio6";
  1525. bias-high-impedance;
  1526. };
  1527. };
  1528. regulators {
  1529. vsup-sd2-supply = <&reg_module_3v3>;
  1530. vsup-sd3-supply = <&reg_module_3v3>;
  1531. vsup-sd4-supply = <&reg_module_3v3>;
  1532. vsup-sd5-supply = <&reg_module_3v3>;
  1533. vin-ldo0-supply = <&reg_1v35_vddio_ddr>;
  1534. vin-ldo1-6-supply = <&reg_module_3v3>;
  1535. vin-ldo2-5-7-supply = <&reg_1v8_vddio>;
  1536. vin-ldo3-4-supply = <&reg_module_3v3>;
  1537. vin-ldo9-10-supply = <&reg_module_3v3>;
  1538. vin-ldo11-supply = <&reg_module_3v3>;
  1539. reg_vdd_cpu: sd0 {
  1540. regulator-name = "+VDD_CPU_AP";
  1541. regulator-min-microvolt = <700000>;
  1542. regulator-max-microvolt = <1400000>;
  1543. regulator-min-microamp = <3500000>;
  1544. regulator-max-microamp = <3500000>;
  1545. regulator-always-on;
  1546. regulator-boot-on;
  1547. ams,ext-control = <2>;
  1548. };
  1549. sd1 {
  1550. regulator-name = "+VDD_CORE";
  1551. regulator-min-microvolt = <700000>;
  1552. regulator-max-microvolt = <1350000>;
  1553. regulator-min-microamp = <2500000>;
  1554. regulator-max-microamp = <4000000>;
  1555. regulator-always-on;
  1556. regulator-boot-on;
  1557. ams,ext-control = <1>;
  1558. };
  1559. reg_1v35_vddio_ddr: sd2 {
  1560. regulator-name =
  1561. "+V1.35_VDDIO_DDR(sd2)";
  1562. regulator-min-microvolt = <1350000>;
  1563. regulator-max-microvolt = <1350000>;
  1564. regulator-always-on;
  1565. regulator-boot-on;
  1566. };
  1567. sd3 {
  1568. regulator-name =
  1569. "+V1.35_VDDIO_DDR(sd3)";
  1570. regulator-min-microvolt = <1350000>;
  1571. regulator-max-microvolt = <1350000>;
  1572. regulator-always-on;
  1573. regulator-boot-on;
  1574. };
  1575. reg_1v05_vdd: sd4 {
  1576. regulator-name = "+V1.05";
  1577. regulator-min-microvolt = <1050000>;
  1578. regulator-max-microvolt = <1050000>;
  1579. };
  1580. reg_1v8_vddio: sd5 {
  1581. regulator-name = "+V1.8";
  1582. regulator-min-microvolt = <1800000>;
  1583. regulator-max-microvolt = <1800000>;
  1584. regulator-boot-on;
  1585. regulator-always-on;
  1586. };
  1587. reg_vdd_gpu: sd6 {
  1588. regulator-name = "+VDD_GPU_AP";
  1589. regulator-min-microvolt = <650000>;
  1590. regulator-max-microvolt = <1200000>;
  1591. regulator-min-microamp = <3500000>;
  1592. regulator-max-microamp = <3500000>;
  1593. regulator-boot-on;
  1594. regulator-always-on;
  1595. };
  1596. reg_1v05_avdd: ldo0 {
  1597. regulator-name = "+V1.05_AVDD";
  1598. regulator-min-microvolt = <1050000>;
  1599. regulator-max-microvolt = <1050000>;
  1600. regulator-boot-on;
  1601. regulator-always-on;
  1602. ams,ext-control = <1>;
  1603. };
  1604. vddio_sdmmc1: ldo1 {
  1605. regulator-name = "VDDIO_SDMMC1";
  1606. regulator-min-microvolt = <1800000>;
  1607. regulator-max-microvolt = <3300000>;
  1608. };
  1609. ldo2 {
  1610. regulator-name = "+V1.2";
  1611. regulator-min-microvolt = <1200000>;
  1612. regulator-max-microvolt = <1200000>;
  1613. regulator-boot-on;
  1614. regulator-always-on;
  1615. };
  1616. ldo3 {
  1617. regulator-name = "+V1.05_RTC";
  1618. regulator-min-microvolt = <1000000>;
  1619. regulator-max-microvolt = <1000000>;
  1620. regulator-boot-on;
  1621. regulator-always-on;
  1622. ams,enable-tracking;
  1623. };
  1624. /* 1.8V for LVDS, 3.3V for eDP */
  1625. ldo4 {
  1626. regulator-name = "AVDD_LVDS0_PLL";
  1627. regulator-min-microvolt = <1800000>;
  1628. regulator-max-microvolt = <1800000>;
  1629. };
  1630. /* LDO5 not used */
  1631. vddio_sdmmc3: ldo6 {
  1632. regulator-name = "VDDIO_SDMMC3";
  1633. regulator-min-microvolt = <1800000>;
  1634. regulator-max-microvolt = <3300000>;
  1635. };
  1636. /* LDO7 not used */
  1637. ldo9 {
  1638. regulator-name = "+V3.3_ETH(ldo9)";
  1639. regulator-min-microvolt = <3300000>;
  1640. regulator-max-microvolt = <3300000>;
  1641. regulator-always-on;
  1642. };
  1643. ldo10 {
  1644. regulator-name = "+V3.3_ETH(ldo10)";
  1645. regulator-min-microvolt = <3300000>;
  1646. regulator-max-microvolt = <3300000>;
  1647. regulator-always-on;
  1648. };
  1649. ldo11 {
  1650. regulator-name = "+V1.8_VPP_FUSE";
  1651. regulator-min-microvolt = <1800000>;
  1652. regulator-max-microvolt = <1800000>;
  1653. };
  1654. };
  1655. };
  1656. /*
  1657. * TMP451 temperature sensor
  1658. * Note: THERM_N directly connected to AS3722 PMIC THERM
  1659. */
  1660. temp-sensor@4c {
  1661. compatible = "ti,tmp451";
  1662. reg = <0x4c>;
  1663. interrupt-parent = <&gpio>;
  1664. interrupts = <TEGRA_GPIO(I, 6) IRQ_TYPE_EDGE_FALLING>;
  1665. #thermal-sensor-cells = <1>;
  1666. vcc-supply = <&reg_module_3v3>;
  1667. };
  1668. };
  1669. /* SPI2: MCU SPI */
  1670. spi@7000d600 {
  1671. status = "okay";
  1672. spi-max-frequency = <25000000>;
  1673. };
  1674. pmc@7000e400 {
  1675. nvidia,invert-interrupt;
  1676. nvidia,suspend-mode = <1>;
  1677. nvidia,cpu-pwr-good-time = <500>;
  1678. nvidia,cpu-pwr-off-time = <300>;
  1679. nvidia,core-pwr-good-time = <641 3845>;
  1680. nvidia,core-pwr-off-time = <61036>;
  1681. nvidia,core-power-req-active-high;
  1682. nvidia,sys-clock-req-active-high;
  1683. /* Set power_off bit in ResetControl register of AS3722 PMIC */
  1684. i2c-thermtrip {
  1685. nvidia,i2c-controller-id = <4>;
  1686. nvidia,bus-addr = <0x40>;
  1687. nvidia,reg-addr = <0x36>;
  1688. nvidia,reg-data = <0x2>;
  1689. };
  1690. };
  1691. sata@70020000 {
  1692. phys = <&{/padctl@7009f000/pads/sata/lanes/sata-0}>;
  1693. phy-names = "sata-0";
  1694. avdd-supply = <&reg_1v05_vdd>;
  1695. hvdd-supply = <&reg_module_3v3>;
  1696. vddio-supply = <&reg_1v05_vdd>;
  1697. };
  1698. usb@70090000 {
  1699. /* USBO1, USBO1 (SS), USBH2, USBH4 and USBH4 (SS) */
  1700. phys = <&{/padctl@7009f000/pads/usb2/lanes/usb2-0}>,
  1701. <&{/padctl@7009f000/pads/pcie/lanes/pcie-1}>,
  1702. <&{/padctl@7009f000/pads/usb2/lanes/usb2-1}>,
  1703. <&{/padctl@7009f000/pads/usb2/lanes/usb2-2}>,
  1704. <&{/padctl@7009f000/pads/pcie/lanes/pcie-0}>;
  1705. phy-names = "usb2-0", "usb3-1", "usb2-1", "usb2-2", "usb3-0";
  1706. avddio-pex-supply = <&reg_1v05_vdd>;
  1707. avdd-pll-erefe-supply = <&reg_1v05_avdd>;
  1708. avdd-pll-utmip-supply = <&reg_1v8_vddio>;
  1709. avdd-usb-ss-pll-supply = <&reg_1v05_vdd>;
  1710. avdd-usb-supply = <&reg_module_3v3>;
  1711. dvddio-pex-supply = <&reg_1v05_vdd>;
  1712. hvdd-usb-ss-pll-e-supply = <&reg_module_3v3>;
  1713. hvdd-usb-ss-supply = <&reg_module_3v3>;
  1714. };
  1715. padctl@7009f000 {
  1716. avdd-pll-utmip-supply = <&reg_1v8_vddio>;
  1717. avdd-pll-erefe-supply = <&reg_1v05_avdd>;
  1718. avdd-pex-pll-supply = <&reg_1v05_vdd>;
  1719. hvdd-pex-pll-e-supply = <&reg_module_3v3>;
  1720. pads {
  1721. usb2 {
  1722. status = "okay";
  1723. lanes {
  1724. usb2-0 {
  1725. status = "okay";
  1726. nvidia,function = "xusb";
  1727. };
  1728. usb2-1 {
  1729. status = "okay";
  1730. nvidia,function = "xusb";
  1731. };
  1732. usb2-2 {
  1733. status = "okay";
  1734. nvidia,function = "xusb";
  1735. };
  1736. };
  1737. };
  1738. pcie {
  1739. status = "okay";
  1740. lanes {
  1741. pcie-0 {
  1742. status = "okay";
  1743. nvidia,function = "usb3-ss";
  1744. };
  1745. pcie-1 {
  1746. status = "okay";
  1747. nvidia,function = "usb3-ss";
  1748. };
  1749. pcie-2 {
  1750. status = "okay";
  1751. nvidia,function = "pcie";
  1752. };
  1753. pcie-3 {
  1754. status = "okay";
  1755. nvidia,function = "pcie";
  1756. };
  1757. pcie-4 {
  1758. status = "okay";
  1759. nvidia,function = "pcie";
  1760. };
  1761. };
  1762. };
  1763. sata {
  1764. status = "okay";
  1765. lanes {
  1766. sata-0 {
  1767. status = "okay";
  1768. nvidia,function = "sata";
  1769. };
  1770. };
  1771. };
  1772. };
  1773. ports {
  1774. /* USBO1 */
  1775. usb2-0 {
  1776. status = "okay";
  1777. mode = "otg";
  1778. usb-role-switch;
  1779. vbus-supply = <&reg_usbo1_vbus>;
  1780. };
  1781. /* USBH2 */
  1782. usb2-1 {
  1783. status = "okay";
  1784. mode = "host";
  1785. vbus-supply = <&reg_usbh_vbus>;
  1786. };
  1787. /* USBH4 */
  1788. usb2-2 {
  1789. status = "okay";
  1790. mode = "host";
  1791. vbus-supply = <&reg_usbh_vbus>;
  1792. };
  1793. usb3-0 {
  1794. status = "okay";
  1795. nvidia,usb2-companion = <2>;
  1796. vbus-supply = <&reg_usbh_vbus>;
  1797. };
  1798. usb3-1 {
  1799. status = "okay";
  1800. nvidia,usb2-companion = <0>;
  1801. vbus-supply = <&reg_usbo1_vbus>;
  1802. };
  1803. };
  1804. };
  1805. /* eMMC */
  1806. mmc@700b0600 {
  1807. status = "okay";
  1808. bus-width = <8>;
  1809. non-removable;
  1810. vmmc-supply = <&reg_module_3v3>; /* VCC */
  1811. vqmmc-supply = <&reg_1v8_vddio>; /* VCCQ */
  1812. mmc-ddr-1_8v;
  1813. };
  1814. /* CPU DFLL clock */
  1815. clock@70110000 {
  1816. status = "okay";
  1817. nvidia,i2c-fs-rate = <400000>;
  1818. vdd-cpu-supply = <&reg_vdd_cpu>;
  1819. };
  1820. ahub@70300000 {
  1821. i2s@70301200 {
  1822. status = "okay";
  1823. };
  1824. };
  1825. clk32k_in: osc3 {
  1826. compatible = "fixed-clock";
  1827. #clock-cells = <0>;
  1828. clock-frequency = <32768>;
  1829. };
  1830. cpus {
  1831. cpu@0 {
  1832. vdd-cpu-supply = <&reg_vdd_cpu>;
  1833. };
  1834. };
  1835. reg_1v05_avdd_hdmi_pll: regulator-1v05-avdd-hdmi-pll {
  1836. compatible = "regulator-fixed";
  1837. regulator-name = "+V1.05_AVDD_HDMI_PLL";
  1838. regulator-min-microvolt = <1050000>;
  1839. regulator-max-microvolt = <1050000>;
  1840. gpio = <&gpio TEGRA_GPIO(H, 7) GPIO_ACTIVE_LOW>;
  1841. vin-supply = <&reg_1v05_vdd>;
  1842. };
  1843. reg_3v3_mxm: regulator-3v3-mxm {
  1844. compatible = "regulator-fixed";
  1845. regulator-name = "+V3.3_MXM";
  1846. regulator-min-microvolt = <3300000>;
  1847. regulator-max-microvolt = <3300000>;
  1848. regulator-always-on;
  1849. regulator-boot-on;
  1850. };
  1851. reg_3v3_avdd_hdmi: regulator-3v3-avdd-hdmi {
  1852. compatible = "regulator-fixed";
  1853. regulator-name = "+V3.3_AVDD_HDMI";
  1854. regulator-min-microvolt = <3300000>;
  1855. regulator-max-microvolt = <3300000>;
  1856. vin-supply = <&reg_1v05_vdd>;
  1857. };
  1858. reg_module_3v3: regulator-module-3v3 {
  1859. compatible = "regulator-fixed";
  1860. regulator-name = "+V3.3";
  1861. regulator-min-microvolt = <3300000>;
  1862. regulator-max-microvolt = <3300000>;
  1863. regulator-always-on;
  1864. regulator-boot-on;
  1865. /* PWR_EN_+V3.3 */
  1866. gpio = <&pmic 2 GPIO_ACTIVE_HIGH>;
  1867. enable-active-high;
  1868. vin-supply = <&reg_3v3_mxm>;
  1869. };
  1870. reg_module_3v3_audio: regulator-module-3v3-audio {
  1871. compatible = "regulator-fixed";
  1872. regulator-name = "+V3.3_AUDIO_AVDD_S";
  1873. regulator-min-microvolt = <3300000>;
  1874. regulator-max-microvolt = <3300000>;
  1875. regulator-always-on;
  1876. };
  1877. sound {
  1878. compatible = "toradex,tegra-audio-sgtl5000-apalis_tk1",
  1879. "nvidia,tegra-audio-sgtl5000";
  1880. nvidia,model = "Toradex Apalis TK1";
  1881. nvidia,audio-routing =
  1882. "Headphone Jack", "HP_OUT",
  1883. "LINE_IN", "Line In Jack",
  1884. "MIC_IN", "Mic Jack";
  1885. nvidia,i2s-controller = <&tegra_i2s2>;
  1886. nvidia,audio-codec = <&sgtl5000>;
  1887. clocks = <&tegra_car TEGRA124_CLK_PLL_A>,
  1888. <&tegra_car TEGRA124_CLK_PLL_A_OUT0>,
  1889. <&tegra_pmc TEGRA_PMC_CLK_OUT_1>;
  1890. clock-names = "pll_a", "pll_a_out0", "mclk";
  1891. assigned-clocks = <&tegra_car TEGRA124_CLK_EXTERN1>,
  1892. <&tegra_pmc TEGRA_PMC_CLK_OUT_1>;
  1893. assigned-clock-parents = <&tegra_car TEGRA124_CLK_PLL_A_OUT0>,
  1894. <&tegra_car TEGRA124_CLK_EXTERN1>;
  1895. };
  1896. thermal-zones {
  1897. cpu-thermal {
  1898. trips {
  1899. cpu-shutdown-trip {
  1900. temperature = <101000>;
  1901. hysteresis = <0>;
  1902. type = "critical";
  1903. };
  1904. };
  1905. };
  1906. mem-thermal {
  1907. trips {
  1908. mem-shutdown-trip {
  1909. temperature = <101000>;
  1910. hysteresis = <0>;
  1911. type = "critical";
  1912. };
  1913. };
  1914. };
  1915. gpu-thermal {
  1916. trips {
  1917. gpu-shutdown-trip {
  1918. temperature = <101000>;
  1919. hysteresis = <0>;
  1920. type = "critical";
  1921. };
  1922. };
  1923. };
  1924. };
  1925. };
  1926. &gpio {
  1927. /* I210 Gigabit Ethernet Controller Reset */
  1928. lan-reset-n-hog {
  1929. gpio-hog;
  1930. gpios = <TEGRA_GPIO(S, 2) GPIO_ACTIVE_HIGH>;
  1931. output-high;
  1932. line-name = "LAN_RESET_N";
  1933. };
  1934. /* Control MXM3 pin 26 Reset Module Output Carrier Input */
  1935. reset-moci-ctrl-hog {
  1936. gpio-hog;
  1937. gpios = <TEGRA_GPIO(U, 4) GPIO_ACTIVE_HIGH>;
  1938. output-high;
  1939. line-name = "RESET_MOCI_CTRL";
  1940. };
  1941. };