tegra114-dalmore.dts 34 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. /*
  3. * This dts file supports Dalmore A04.
  4. * Other board revisions are not supported
  5. */
  6. /dts-v1/;
  7. #include <dt-bindings/input/input.h>
  8. #include "tegra114.dtsi"
  9. / {
  10. model = "NVIDIA Tegra114 Dalmore evaluation board";
  11. compatible = "nvidia,dalmore", "nvidia,tegra114";
  12. aliases {
  13. rtc0 = "/i2c@7000d000/tps65913@58";
  14. rtc1 = "/rtc@7000e000";
  15. serial0 = &uartd;
  16. };
  17. chosen {
  18. stdout-path = "serial0:115200n8";
  19. };
  20. memory@80000000 {
  21. reg = <0x80000000 0x40000000>;
  22. };
  23. host1x@50000000 {
  24. hdmi@54280000 {
  25. status = "okay";
  26. hdmi-supply = <&vdd_5v0_hdmi>;
  27. vdd-supply = <&vdd_hdmi_reg>;
  28. pll-supply = <&palmas_smps3_reg>;
  29. nvidia,ddc-i2c-bus = <&hdmi_ddc>;
  30. nvidia,hpd-gpio =
  31. <&gpio TEGRA_GPIO(N, 7) GPIO_ACTIVE_HIGH>;
  32. };
  33. dsi@54300000 {
  34. status = "okay";
  35. avdd-dsi-csi-supply = <&avdd_1v2_reg>;
  36. panel@0 {
  37. compatible = "panasonic,vvx10f004b00";
  38. reg = <0>;
  39. power-supply = <&avdd_lcd_reg>;
  40. backlight = <&backlight>;
  41. };
  42. };
  43. };
  44. pinmux@70000868 {
  45. pinctrl-names = "default";
  46. pinctrl-0 = <&state_default>;
  47. state_default: pinmux {
  48. clk1_out_pw4 {
  49. nvidia,pins = "clk1_out_pw4";
  50. nvidia,function = "extperiph1";
  51. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  52. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  53. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  54. };
  55. dap1_din_pn1 {
  56. nvidia,pins = "dap1_din_pn1";
  57. nvidia,function = "i2s0";
  58. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  59. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  60. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  61. };
  62. dap1_dout_pn2 {
  63. nvidia,pins = "dap1_dout_pn2",
  64. "dap1_fs_pn0",
  65. "dap1_sclk_pn3";
  66. nvidia,function = "i2s0";
  67. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  68. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  69. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  70. };
  71. dap2_din_pa4 {
  72. nvidia,pins = "dap2_din_pa4";
  73. nvidia,function = "i2s1";
  74. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  75. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  76. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  77. };
  78. dap2_dout_pa5 {
  79. nvidia,pins = "dap2_dout_pa5",
  80. "dap2_fs_pa2",
  81. "dap2_sclk_pa3";
  82. nvidia,function = "i2s1";
  83. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  84. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  85. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  86. };
  87. dap4_din_pp5 {
  88. nvidia,pins = "dap4_din_pp5",
  89. "dap4_dout_pp6",
  90. "dap4_fs_pp4",
  91. "dap4_sclk_pp7";
  92. nvidia,function = "i2s3";
  93. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  94. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  95. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  96. };
  97. dvfs_pwm_px0 {
  98. nvidia,pins = "dvfs_pwm_px0",
  99. "dvfs_clk_px2";
  100. nvidia,function = "cldvfs";
  101. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  102. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  103. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  104. };
  105. ulpi_clk_py0 {
  106. nvidia,pins = "ulpi_clk_py0",
  107. "ulpi_data0_po1",
  108. "ulpi_data1_po2",
  109. "ulpi_data2_po3",
  110. "ulpi_data3_po4",
  111. "ulpi_data4_po5",
  112. "ulpi_data5_po6",
  113. "ulpi_data6_po7",
  114. "ulpi_data7_po0";
  115. nvidia,function = "ulpi";
  116. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  117. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  118. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  119. };
  120. ulpi_dir_py1 {
  121. nvidia,pins = "ulpi_dir_py1",
  122. "ulpi_nxt_py2";
  123. nvidia,function = "ulpi";
  124. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  125. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  126. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  127. };
  128. ulpi_stp_py3 {
  129. nvidia,pins = "ulpi_stp_py3";
  130. nvidia,function = "ulpi";
  131. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  132. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  133. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  134. };
  135. cam_i2c_scl_pbb1 {
  136. nvidia,pins = "cam_i2c_scl_pbb1",
  137. "cam_i2c_sda_pbb2";
  138. nvidia,function = "i2c3";
  139. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  140. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  141. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  142. nvidia,lock = <TEGRA_PIN_DISABLE>;
  143. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  144. };
  145. cam_mclk_pcc0 {
  146. nvidia,pins = "cam_mclk_pcc0",
  147. "pbb0";
  148. nvidia,function = "vi_alt3";
  149. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  150. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  151. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  152. nvidia,lock = <TEGRA_PIN_DISABLE>;
  153. };
  154. gen2_i2c_scl_pt5 {
  155. nvidia,pins = "gen2_i2c_scl_pt5",
  156. "gen2_i2c_sda_pt6";
  157. nvidia,function = "i2c2";
  158. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  159. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  160. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  161. nvidia,lock = <TEGRA_PIN_DISABLE>;
  162. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  163. };
  164. gmi_a16_pj7 {
  165. nvidia,pins = "gmi_a16_pj7";
  166. nvidia,function = "uartd";
  167. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  168. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  169. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  170. };
  171. gmi_a17_pb0 {
  172. nvidia,pins = "gmi_a17_pb0",
  173. "gmi_a18_pb1";
  174. nvidia,function = "uartd";
  175. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  176. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  177. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  178. };
  179. gmi_a19_pk7 {
  180. nvidia,pins = "gmi_a19_pk7";
  181. nvidia,function = "uartd";
  182. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  183. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  184. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  185. };
  186. gmi_ad5_pg5 {
  187. nvidia,pins = "gmi_ad5_pg5",
  188. "gmi_cs6_n_pi3",
  189. "gmi_wr_n_pi0";
  190. nvidia,function = "spi4";
  191. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  192. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  193. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  194. };
  195. gmi_ad6_pg6 {
  196. nvidia,pins = "gmi_ad6_pg6",
  197. "gmi_ad7_pg7";
  198. nvidia,function = "spi4";
  199. nvidia,pull = <TEGRA_PIN_PULL_UP>;
  200. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  201. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  202. };
  203. gmi_ad12_ph4 {
  204. nvidia,pins = "gmi_ad12_ph4";
  205. nvidia,function = "rsvd4";
  206. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  207. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  208. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  209. };
  210. gmi_ad9_ph1 {
  211. nvidia,pins = "gmi_ad9_ph1";
  212. nvidia,function = "pwm1";
  213. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  214. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  215. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  216. };
  217. gmi_cs1_n_pj2 {
  218. nvidia,pins = "gmi_cs1_n_pj2",
  219. "gmi_oe_n_pi1";
  220. nvidia,function = "soc";
  221. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  222. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  223. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  224. };
  225. clk2_out_pw5 {
  226. nvidia,pins = "clk2_out_pw5";
  227. nvidia,function = "extperiph2";
  228. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  229. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  230. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  231. };
  232. sdmmc1_clk_pz0 {
  233. nvidia,pins = "sdmmc1_clk_pz0";
  234. nvidia,function = "sdmmc1";
  235. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  236. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  237. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  238. };
  239. sdmmc1_cmd_pz1 {
  240. nvidia,pins = "sdmmc1_cmd_pz1",
  241. "sdmmc1_dat0_py7",
  242. "sdmmc1_dat1_py6",
  243. "sdmmc1_dat2_py5",
  244. "sdmmc1_dat3_py4";
  245. nvidia,function = "sdmmc1";
  246. nvidia,pull = <TEGRA_PIN_PULL_UP>;
  247. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  248. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  249. };
  250. sdmmc1_wp_n_pv3 {
  251. nvidia,pins = "sdmmc1_wp_n_pv3";
  252. nvidia,function = "spi4";
  253. nvidia,pull = <TEGRA_PIN_PULL_UP>;
  254. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  255. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  256. };
  257. sdmmc3_clk_pa6 {
  258. nvidia,pins = "sdmmc3_clk_pa6";
  259. nvidia,function = "sdmmc3";
  260. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  261. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  262. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  263. };
  264. sdmmc3_cmd_pa7 {
  265. nvidia,pins = "sdmmc3_cmd_pa7",
  266. "sdmmc3_dat0_pb7",
  267. "sdmmc3_dat1_pb6",
  268. "sdmmc3_dat2_pb5",
  269. "sdmmc3_dat3_pb4",
  270. "kb_col4_pq4",
  271. "sdmmc3_clk_lb_out_pee4",
  272. "sdmmc3_clk_lb_in_pee5";
  273. nvidia,function = "sdmmc3";
  274. nvidia,pull = <TEGRA_PIN_PULL_UP>;
  275. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  276. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  277. };
  278. sdmmc4_clk_pcc4 {
  279. nvidia,pins = "sdmmc4_clk_pcc4";
  280. nvidia,function = "sdmmc4";
  281. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  282. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  283. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  284. };
  285. sdmmc4_cmd_pt7 {
  286. nvidia,pins = "sdmmc4_cmd_pt7",
  287. "sdmmc4_dat0_paa0",
  288. "sdmmc4_dat1_paa1",
  289. "sdmmc4_dat2_paa2",
  290. "sdmmc4_dat3_paa3",
  291. "sdmmc4_dat4_paa4",
  292. "sdmmc4_dat5_paa5",
  293. "sdmmc4_dat6_paa6",
  294. "sdmmc4_dat7_paa7";
  295. nvidia,function = "sdmmc4";
  296. nvidia,pull = <TEGRA_PIN_PULL_UP>;
  297. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  298. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  299. };
  300. clk_32k_out_pa0 {
  301. nvidia,pins = "clk_32k_out_pa0";
  302. nvidia,function = "blink";
  303. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  304. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  305. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  306. };
  307. kb_col0_pq0 {
  308. nvidia,pins = "kb_col0_pq0",
  309. "kb_col1_pq1",
  310. "kb_col2_pq2",
  311. "kb_row0_pr0",
  312. "kb_row1_pr1",
  313. "kb_row2_pr2";
  314. nvidia,function = "kbc";
  315. nvidia,pull = <TEGRA_PIN_PULL_UP>;
  316. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  317. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  318. };
  319. dap3_din_pp1 {
  320. nvidia,pins = "dap3_din_pp1",
  321. "dap3_sclk_pp3";
  322. nvidia,function = "displayb";
  323. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  324. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  325. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  326. };
  327. pv0 {
  328. nvidia,pins = "pv0";
  329. nvidia,function = "rsvd4";
  330. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  331. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  332. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  333. };
  334. kb_row7_pr7 {
  335. nvidia,pins = "kb_row7_pr7";
  336. nvidia,function = "rsvd2";
  337. nvidia,pull = <TEGRA_PIN_PULL_UP>;
  338. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  339. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  340. };
  341. kb_row10_ps2 {
  342. nvidia,pins = "kb_row10_ps2";
  343. nvidia,function = "uarta";
  344. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  345. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  346. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  347. };
  348. kb_row9_ps1 {
  349. nvidia,pins = "kb_row9_ps1";
  350. nvidia,function = "uarta";
  351. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  352. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  353. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  354. };
  355. pwr_i2c_scl_pz6 {
  356. nvidia,pins = "pwr_i2c_scl_pz6",
  357. "pwr_i2c_sda_pz7";
  358. nvidia,function = "i2cpwr";
  359. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  360. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  361. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  362. nvidia,lock = <TEGRA_PIN_DISABLE>;
  363. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  364. };
  365. sys_clk_req_pz5 {
  366. nvidia,pins = "sys_clk_req_pz5";
  367. nvidia,function = "sysclk";
  368. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  369. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  370. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  371. };
  372. core_pwr_req {
  373. nvidia,pins = "core_pwr_req";
  374. nvidia,function = "pwron";
  375. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  376. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  377. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  378. };
  379. cpu_pwr_req {
  380. nvidia,pins = "cpu_pwr_req";
  381. nvidia,function = "cpu";
  382. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  383. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  384. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  385. };
  386. pwr_int_n {
  387. nvidia,pins = "pwr_int_n";
  388. nvidia,function = "pmi";
  389. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  390. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  391. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  392. };
  393. reset_out_n {
  394. nvidia,pins = "reset_out_n";
  395. nvidia,function = "reset_out_n";
  396. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  397. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  398. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  399. };
  400. clk3_out_pee0 {
  401. nvidia,pins = "clk3_out_pee0";
  402. nvidia,function = "extperiph3";
  403. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  404. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  405. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  406. };
  407. gen1_i2c_scl_pc4 {
  408. nvidia,pins = "gen1_i2c_scl_pc4",
  409. "gen1_i2c_sda_pc5";
  410. nvidia,function = "i2c1";
  411. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  412. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  413. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  414. nvidia,lock = <TEGRA_PIN_DISABLE>;
  415. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  416. };
  417. uart2_cts_n_pj5 {
  418. nvidia,pins = "uart2_cts_n_pj5";
  419. nvidia,function = "uartb";
  420. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  421. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  422. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  423. };
  424. uart2_rts_n_pj6 {
  425. nvidia,pins = "uart2_rts_n_pj6";
  426. nvidia,function = "uartb";
  427. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  428. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  429. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  430. };
  431. uart2_rxd_pc3 {
  432. nvidia,pins = "uart2_rxd_pc3";
  433. nvidia,function = "irda";
  434. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  435. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  436. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  437. };
  438. uart2_txd_pc2 {
  439. nvidia,pins = "uart2_txd_pc2";
  440. nvidia,function = "irda";
  441. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  442. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  443. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  444. };
  445. uart3_cts_n_pa1 {
  446. nvidia,pins = "uart3_cts_n_pa1",
  447. "uart3_rxd_pw7";
  448. nvidia,function = "uartc";
  449. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  450. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  451. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  452. };
  453. uart3_rts_n_pc0 {
  454. nvidia,pins = "uart3_rts_n_pc0",
  455. "uart3_txd_pw6";
  456. nvidia,function = "uartc";
  457. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  458. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  459. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  460. };
  461. owr {
  462. nvidia,pins = "owr";
  463. nvidia,function = "owr";
  464. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  465. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  466. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  467. };
  468. hdmi_cec_pee3 {
  469. nvidia,pins = "hdmi_cec_pee3";
  470. nvidia,function = "cec";
  471. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  472. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  473. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  474. nvidia,lock = <TEGRA_PIN_DISABLE>;
  475. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  476. };
  477. ddc_scl_pv4 {
  478. nvidia,pins = "ddc_scl_pv4",
  479. "ddc_sda_pv5";
  480. nvidia,function = "i2c4";
  481. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  482. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  483. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  484. nvidia,lock = <TEGRA_PIN_DISABLE>;
  485. nvidia,rcv-sel = <TEGRA_PIN_ENABLE>;
  486. };
  487. spdif_in_pk6 {
  488. nvidia,pins = "spdif_in_pk6";
  489. nvidia,function = "usb";
  490. nvidia,pull = <TEGRA_PIN_PULL_UP>;
  491. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  492. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  493. nvidia,lock = <TEGRA_PIN_DISABLE>;
  494. };
  495. usb_vbus_en0_pn4 {
  496. nvidia,pins = "usb_vbus_en0_pn4";
  497. nvidia,function = "usb";
  498. nvidia,pull = <TEGRA_PIN_PULL_UP>;
  499. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  500. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  501. nvidia,lock = <TEGRA_PIN_DISABLE>;
  502. nvidia,open-drain = <TEGRA_PIN_ENABLE>;
  503. };
  504. gpio_x6_aud_px6 {
  505. nvidia,pins = "gpio_x6_aud_px6";
  506. nvidia,function = "spi6";
  507. nvidia,pull = <TEGRA_PIN_PULL_UP>;
  508. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  509. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  510. };
  511. gpio_x4_aud_px4 {
  512. nvidia,pins = "gpio_x4_aud_px4",
  513. "gpio_x7_aud_px7";
  514. nvidia,function = "rsvd1";
  515. nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
  516. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  517. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  518. };
  519. gpio_x5_aud_px5 {
  520. nvidia,pins = "gpio_x5_aud_px5";
  521. nvidia,function = "rsvd1";
  522. nvidia,pull = <TEGRA_PIN_PULL_UP>;
  523. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  524. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  525. };
  526. gpio_w2_aud_pw2 {
  527. nvidia,pins = "gpio_w2_aud_pw2";
  528. nvidia,function = "rsvd2";
  529. nvidia,pull = <TEGRA_PIN_PULL_UP>;
  530. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  531. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  532. };
  533. gpio_w3_aud_pw3 {
  534. nvidia,pins = "gpio_w3_aud_pw3";
  535. nvidia,function = "spi6";
  536. nvidia,pull = <TEGRA_PIN_PULL_UP>;
  537. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  538. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  539. };
  540. gpio_x1_aud_px1 {
  541. nvidia,pins = "gpio_x1_aud_px1";
  542. nvidia,function = "rsvd4";
  543. nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
  544. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  545. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  546. };
  547. gpio_x3_aud_px3 {
  548. nvidia,pins = "gpio_x3_aud_px3";
  549. nvidia,function = "rsvd4";
  550. nvidia,pull = <TEGRA_PIN_PULL_UP>;
  551. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  552. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  553. };
  554. dap3_fs_pp0 {
  555. nvidia,pins = "dap3_fs_pp0";
  556. nvidia,function = "i2s2";
  557. nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
  558. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  559. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  560. };
  561. dap3_dout_pp2 {
  562. nvidia,pins = "dap3_dout_pp2";
  563. nvidia,function = "i2s2";
  564. nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
  565. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  566. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  567. };
  568. pv1 {
  569. nvidia,pins = "pv1";
  570. nvidia,function = "rsvd1";
  571. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  572. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  573. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  574. };
  575. pbb3 {
  576. nvidia,pins = "pbb3",
  577. "pbb5",
  578. "pbb6",
  579. "pbb7";
  580. nvidia,function = "rsvd4";
  581. nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
  582. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  583. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  584. };
  585. pcc1 {
  586. nvidia,pins = "pcc1",
  587. "pcc2";
  588. nvidia,function = "rsvd4";
  589. nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
  590. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  591. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  592. };
  593. gmi_ad0_pg0 {
  594. nvidia,pins = "gmi_ad0_pg0",
  595. "gmi_ad1_pg1";
  596. nvidia,function = "gmi";
  597. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  598. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  599. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  600. };
  601. gmi_ad10_ph2 {
  602. nvidia,pins = "gmi_ad10_ph2",
  603. "gmi_ad11_ph3",
  604. "gmi_ad13_ph5",
  605. "gmi_ad8_ph0",
  606. "gmi_clk_pk1";
  607. nvidia,function = "gmi";
  608. nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
  609. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  610. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  611. };
  612. gmi_ad2_pg2 {
  613. nvidia,pins = "gmi_ad2_pg2",
  614. "gmi_ad3_pg3";
  615. nvidia,function = "gmi";
  616. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  617. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  618. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  619. };
  620. gmi_adv_n_pk0 {
  621. nvidia,pins = "gmi_adv_n_pk0",
  622. "gmi_cs0_n_pj0",
  623. "gmi_cs2_n_pk3",
  624. "gmi_cs4_n_pk2",
  625. "gmi_cs7_n_pi6",
  626. "gmi_dqs_p_pj3",
  627. "gmi_iordy_pi5",
  628. "gmi_wp_n_pc7";
  629. nvidia,function = "gmi";
  630. nvidia,pull = <TEGRA_PIN_PULL_UP>;
  631. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  632. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  633. };
  634. gmi_cs3_n_pk4 {
  635. nvidia,pins = "gmi_cs3_n_pk4";
  636. nvidia,function = "gmi";
  637. nvidia,pull = <TEGRA_PIN_PULL_UP>;
  638. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  639. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  640. };
  641. clk2_req_pcc5 {
  642. nvidia,pins = "clk2_req_pcc5";
  643. nvidia,function = "rsvd4";
  644. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  645. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  646. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  647. };
  648. kb_col3_pq3 {
  649. nvidia,pins = "kb_col3_pq3",
  650. "kb_col6_pq6",
  651. "kb_col7_pq7";
  652. nvidia,function = "kbc";
  653. nvidia,pull = <TEGRA_PIN_PULL_UP>;
  654. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  655. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  656. };
  657. kb_col5_pq5 {
  658. nvidia,pins = "kb_col5_pq5";
  659. nvidia,function = "kbc";
  660. nvidia,pull = <TEGRA_PIN_PULL_UP>;
  661. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  662. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  663. };
  664. kb_row3_pr3 {
  665. nvidia,pins = "kb_row3_pr3",
  666. "kb_row4_pr4",
  667. "kb_row6_pr6",
  668. "kb_row8_ps0";
  669. nvidia,function = "kbc";
  670. nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
  671. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  672. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  673. };
  674. clk3_req_pee1 {
  675. nvidia,pins = "clk3_req_pee1";
  676. nvidia,function = "rsvd4";
  677. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  678. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  679. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  680. };
  681. pu4 {
  682. nvidia,pins = "pu4";
  683. nvidia,function = "displayb";
  684. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  685. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  686. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  687. };
  688. pu5 {
  689. nvidia,pins = "pu5",
  690. "pu6";
  691. nvidia,function = "displayb";
  692. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  693. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  694. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  695. };
  696. hdmi_int_pn7 {
  697. nvidia,pins = "hdmi_int_pn7";
  698. nvidia,function = "rsvd1";
  699. nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
  700. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  701. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  702. };
  703. clk1_req_pee2 {
  704. nvidia,pins = "clk1_req_pee2",
  705. "usb_vbus_en1_pn5";
  706. nvidia,function = "rsvd4";
  707. nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
  708. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  709. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  710. };
  711. drive_sdio1 {
  712. nvidia,pins = "drive_sdio1";
  713. nvidia,high-speed-mode = <TEGRA_PIN_ENABLE>;
  714. nvidia,schmitt = <TEGRA_PIN_DISABLE>;
  715. nvidia,pull-down-strength = <36>;
  716. nvidia,pull-up-strength = <20>;
  717. nvidia,slew-rate-rising = <TEGRA_PIN_SLEW_RATE_SLOW>;
  718. nvidia,slew-rate-falling = <TEGRA_PIN_SLEW_RATE_SLOW>;
  719. };
  720. drive_sdio3 {
  721. nvidia,pins = "drive_sdio3";
  722. nvidia,high-speed-mode = <TEGRA_PIN_ENABLE>;
  723. nvidia,schmitt = <TEGRA_PIN_DISABLE>;
  724. nvidia,pull-down-strength = <22>;
  725. nvidia,pull-up-strength = <36>;
  726. nvidia,slew-rate-rising = <TEGRA_PIN_SLEW_RATE_FASTEST>;
  727. nvidia,slew-rate-falling = <TEGRA_PIN_SLEW_RATE_FASTEST>;
  728. };
  729. drive_gma {
  730. nvidia,pins = "drive_gma";
  731. nvidia,high-speed-mode = <TEGRA_PIN_ENABLE>;
  732. nvidia,schmitt = <TEGRA_PIN_DISABLE>;
  733. nvidia,pull-down-strength = <2>;
  734. nvidia,pull-up-strength = <1>;
  735. nvidia,slew-rate-rising = <TEGRA_PIN_SLEW_RATE_FASTEST>;
  736. nvidia,slew-rate-falling = <TEGRA_PIN_SLEW_RATE_FASTEST>;
  737. };
  738. };
  739. };
  740. serial@70006300 {
  741. status = "okay";
  742. };
  743. pwm@7000a000 {
  744. status = "okay";
  745. };
  746. i2c@7000c000 {
  747. status = "okay";
  748. clock-frequency = <100000>;
  749. battery: smart-battery@b {
  750. compatible = "ti,bq20z45", "sbs,sbs-battery";
  751. reg = <0xb>;
  752. sbs,i2c-retry-count = <2>;
  753. sbs,poll-retry-count = <100>;
  754. power-supplies = <&charger>;
  755. };
  756. rt5640: rt5640@1c {
  757. compatible = "realtek,rt5640";
  758. reg = <0x1c>;
  759. interrupt-parent = <&gpio>;
  760. interrupts = <TEGRA_GPIO(W, 3) IRQ_TYPE_EDGE_FALLING>;
  761. realtek,ldo1-en-gpios =
  762. <&gpio TEGRA_GPIO(V, 3) GPIO_ACTIVE_HIGH>;
  763. };
  764. temperature-sensor@4c {
  765. compatible = "onnn,nct1008";
  766. reg = <0x4c>;
  767. vcc-supply = <&palmas_ldo6_reg>;
  768. interrupt-parent = <&gpio>;
  769. interrupts = <TEGRA_GPIO(O, 4) IRQ_TYPE_EDGE_FALLING>;
  770. };
  771. };
  772. hdmi_ddc: i2c@7000c700 {
  773. status = "okay";
  774. };
  775. i2c@7000d000 {
  776. status = "okay";
  777. clock-frequency = <400000>;
  778. tps51632@43 {
  779. compatible = "ti,tps51632";
  780. reg = <0x43>;
  781. regulator-name = "vdd-cpu";
  782. regulator-min-microvolt = <500000>;
  783. regulator-max-microvolt = <1520000>;
  784. regulator-boot-on;
  785. regulator-always-on;
  786. };
  787. tps65090@48 {
  788. compatible = "ti,tps65090";
  789. reg = <0x48>;
  790. interrupt-parent = <&gpio>;
  791. interrupts = <TEGRA_GPIO(J, 0) IRQ_TYPE_LEVEL_HIGH>;
  792. vsys1-supply = <&vdd_ac_bat_reg>;
  793. vsys2-supply = <&vdd_ac_bat_reg>;
  794. vsys3-supply = <&vdd_ac_bat_reg>;
  795. infet1-supply = <&vdd_ac_bat_reg>;
  796. infet2-supply = <&vdd_ac_bat_reg>;
  797. infet3-supply = <&tps65090_dcdc2_reg>;
  798. infet4-supply = <&tps65090_dcdc2_reg>;
  799. infet5-supply = <&tps65090_dcdc2_reg>;
  800. infet6-supply = <&tps65090_dcdc2_reg>;
  801. infet7-supply = <&tps65090_dcdc2_reg>;
  802. vsys-l1-supply = <&vdd_ac_bat_reg>;
  803. vsys-l2-supply = <&vdd_ac_bat_reg>;
  804. charger: charger {
  805. compatible = "ti,tps65090-charger";
  806. ti,enable-low-current-chrg;
  807. };
  808. regulators {
  809. tps65090_dcdc1_reg: dcdc1 {
  810. regulator-name = "vdd-sys-5v0";
  811. regulator-always-on;
  812. regulator-boot-on;
  813. };
  814. tps65090_dcdc2_reg: dcdc2 {
  815. regulator-name = "vdd-sys-3v3";
  816. regulator-always-on;
  817. regulator-boot-on;
  818. };
  819. tps65090_dcdc3_reg: dcdc3 {
  820. regulator-name = "vdd-ao";
  821. regulator-always-on;
  822. regulator-boot-on;
  823. };
  824. vdd_bl_reg: fet1 {
  825. regulator-name = "vdd-lcd-bl";
  826. };
  827. fet3 {
  828. regulator-name = "vdd-modem-3v3";
  829. };
  830. avdd_lcd_reg: fet4 {
  831. regulator-name = "avdd-lcd";
  832. };
  833. fet5 {
  834. regulator-name = "vdd-lvds";
  835. };
  836. fet6 {
  837. regulator-name = "vdd-sd-slot";
  838. regulator-always-on;
  839. regulator-boot-on;
  840. };
  841. fet7 {
  842. regulator-name = "vdd-com-3v3";
  843. };
  844. ldo1 {
  845. regulator-name = "vdd-sby-5v0";
  846. regulator-always-on;
  847. regulator-boot-on;
  848. };
  849. ldo2 {
  850. regulator-name = "vdd-sby-3v3";
  851. regulator-always-on;
  852. regulator-boot-on;
  853. };
  854. };
  855. };
  856. palmas: tps65913@58 {
  857. compatible = "ti,tps65913", "ti,palmas";
  858. reg = <0x58>;
  859. interrupts = <0 86 IRQ_TYPE_LEVEL_HIGH>;
  860. #interrupt-cells = <2>;
  861. interrupt-controller;
  862. ti,system-power-controller;
  863. palmas_gpio: gpio {
  864. compatible = "ti,palmas-gpio";
  865. gpio-controller;
  866. #gpio-cells = <2>;
  867. };
  868. pmic {
  869. compatible = "ti,tps65913-pmic", "ti,palmas-pmic";
  870. smps1-in-supply = <&tps65090_dcdc3_reg>;
  871. smps3-in-supply = <&tps65090_dcdc3_reg>;
  872. smps4-in-supply = <&tps65090_dcdc2_reg>;
  873. smps7-in-supply = <&tps65090_dcdc2_reg>;
  874. smps8-in-supply = <&tps65090_dcdc2_reg>;
  875. smps9-in-supply = <&tps65090_dcdc2_reg>;
  876. ldo1-in-supply = <&tps65090_dcdc2_reg>;
  877. ldo2-in-supply = <&tps65090_dcdc2_reg>;
  878. ldo3-in-supply = <&palmas_smps3_reg>;
  879. ldo4-in-supply = <&tps65090_dcdc2_reg>;
  880. ldo5-in-supply = <&vdd_ac_bat_reg>;
  881. ldo6-in-supply = <&tps65090_dcdc2_reg>;
  882. ldo7-in-supply = <&tps65090_dcdc2_reg>;
  883. ldo8-in-supply = <&tps65090_dcdc3_reg>;
  884. ldo9-in-supply = <&palmas_smps9_reg>;
  885. ldoln-in-supply = <&tps65090_dcdc1_reg>;
  886. ldousb-in-supply = <&tps65090_dcdc1_reg>;
  887. regulators {
  888. smps12 {
  889. regulator-name = "vddio-ddr";
  890. regulator-min-microvolt = <1350000>;
  891. regulator-max-microvolt = <1350000>;
  892. regulator-always-on;
  893. regulator-boot-on;
  894. };
  895. palmas_smps3_reg: smps3 {
  896. regulator-name = "vddio-1v8";
  897. regulator-min-microvolt = <1800000>;
  898. regulator-max-microvolt = <1800000>;
  899. regulator-always-on;
  900. regulator-boot-on;
  901. };
  902. smps45 {
  903. regulator-name = "vdd-core";
  904. regulator-min-microvolt = <900000>;
  905. regulator-max-microvolt = <1400000>;
  906. regulator-always-on;
  907. regulator-boot-on;
  908. };
  909. smps457 {
  910. regulator-name = "vdd-core";
  911. regulator-min-microvolt = <900000>;
  912. regulator-max-microvolt = <1400000>;
  913. regulator-always-on;
  914. regulator-boot-on;
  915. };
  916. smps8 {
  917. regulator-name = "avdd-pll";
  918. regulator-min-microvolt = <1050000>;
  919. regulator-max-microvolt = <1050000>;
  920. regulator-always-on;
  921. regulator-boot-on;
  922. };
  923. palmas_smps9_reg: smps9 {
  924. regulator-name = "sdhci-vdd-sd-slot";
  925. regulator-min-microvolt = <2800000>;
  926. regulator-max-microvolt = <2800000>;
  927. regulator-always-on;
  928. };
  929. ldo1 {
  930. regulator-name = "avdd-cam1";
  931. regulator-min-microvolt = <2800000>;
  932. regulator-max-microvolt = <2800000>;
  933. };
  934. ldo2 {
  935. regulator-name = "avdd-cam2";
  936. regulator-min-microvolt = <2800000>;
  937. regulator-max-microvolt = <2800000>;
  938. };
  939. avdd_1v2_reg: ldo3 {
  940. regulator-name = "avdd-dsi-csi";
  941. regulator-min-microvolt = <1200000>;
  942. regulator-max-microvolt = <1200000>;
  943. };
  944. ldo4 {
  945. regulator-name = "vpp-fuse";
  946. regulator-min-microvolt = <1800000>;
  947. regulator-max-microvolt = <1800000>;
  948. };
  949. palmas_ldo6_reg: ldo6 {
  950. regulator-name = "vdd-sensor-2v85";
  951. regulator-min-microvolt = <2850000>;
  952. regulator-max-microvolt = <2850000>;
  953. };
  954. ldo7 {
  955. regulator-name = "vdd-af-cam1";
  956. regulator-min-microvolt = <2800000>;
  957. regulator-max-microvolt = <2800000>;
  958. };
  959. ldo8 {
  960. regulator-name = "vdd-rtc";
  961. regulator-min-microvolt = <900000>;
  962. regulator-max-microvolt = <900000>;
  963. regulator-always-on;
  964. regulator-boot-on;
  965. ti,enable-ldo8-tracking;
  966. };
  967. ldo9 {
  968. regulator-name = "vddio-sdmmc-2";
  969. regulator-min-microvolt = <1800000>;
  970. regulator-max-microvolt = <3300000>;
  971. regulator-always-on;
  972. regulator-boot-on;
  973. };
  974. ldoln {
  975. regulator-name = "hvdd-usb";
  976. regulator-min-microvolt = <3300000>;
  977. regulator-max-microvolt = <3300000>;
  978. };
  979. ldousb {
  980. regulator-name = "avdd-usb";
  981. regulator-min-microvolt = <3300000>;
  982. regulator-max-microvolt = <3300000>;
  983. regulator-always-on;
  984. regulator-boot-on;
  985. };
  986. regen1 {
  987. regulator-name = "rail-3v3";
  988. regulator-max-microvolt = <3300000>;
  989. regulator-always-on;
  990. regulator-boot-on;
  991. };
  992. regen2 {
  993. regulator-name = "rail-5v0";
  994. regulator-max-microvolt = <5000000>;
  995. regulator-always-on;
  996. regulator-boot-on;
  997. };
  998. };
  999. };
  1000. rtc {
  1001. compatible = "ti,palmas-rtc";
  1002. interrupt-parent = <&palmas>;
  1003. interrupts = <8 0>;
  1004. };
  1005. pinmux {
  1006. compatible = "ti,tps65913-pinctrl";
  1007. pinctrl-names = "default";
  1008. pinctrl-0 = <&palmas_default>;
  1009. palmas_default: pinmux {
  1010. pin_gpio6 {
  1011. pins = "gpio6";
  1012. function = "gpio";
  1013. };
  1014. };
  1015. };
  1016. };
  1017. };
  1018. spi@7000da00 {
  1019. status = "okay";
  1020. spi-max-frequency = <25000000>;
  1021. flash@0 {
  1022. compatible = "winbond,w25q32dw", "jedec,spi-nor";
  1023. reg = <0>;
  1024. spi-max-frequency = <20000000>;
  1025. };
  1026. };
  1027. pmc@7000e400 {
  1028. nvidia,invert-interrupt;
  1029. nvidia,suspend-mode = <1>;
  1030. nvidia,cpu-pwr-good-time = <500>;
  1031. nvidia,cpu-pwr-off-time = <300>;
  1032. nvidia,core-pwr-good-time = <641 3845>;
  1033. nvidia,core-pwr-off-time = <61036>;
  1034. nvidia,core-power-req-active-high;
  1035. nvidia,sys-clock-req-active-high;
  1036. };
  1037. ahub@70080000 {
  1038. i2s@70080400 {
  1039. status = "okay";
  1040. };
  1041. };
  1042. mmc@78000400 {
  1043. cd-gpios = <&gpio TEGRA_GPIO(V, 2) GPIO_ACTIVE_LOW>;
  1044. wp-gpios = <&gpio TEGRA_GPIO(Q, 4) GPIO_ACTIVE_HIGH>;
  1045. bus-width = <4>;
  1046. status = "okay";
  1047. };
  1048. mmc@78000600 {
  1049. bus-width = <8>;
  1050. status = "okay";
  1051. non-removable;
  1052. };
  1053. usb@7d000000 {
  1054. compatible = "nvidia,tegra114-udc";
  1055. status = "okay";
  1056. dr_mode = "peripheral";
  1057. };
  1058. usb-phy@7d000000 {
  1059. status = "okay";
  1060. };
  1061. usb@7d008000 {
  1062. status = "okay";
  1063. };
  1064. usb-phy@7d008000 {
  1065. status = "okay";
  1066. vbus-supply = <&usb3_vbus_reg>;
  1067. };
  1068. backlight: backlight {
  1069. compatible = "pwm-backlight";
  1070. enable-gpios = <&gpio TEGRA_GPIO(H, 2) GPIO_ACTIVE_HIGH>;
  1071. power-supply = <&vdd_bl_reg>;
  1072. pwms = <&pwm 1 1000000>;
  1073. brightness-levels = <0 4 8 16 32 64 128 255>;
  1074. default-brightness-level = <6>;
  1075. };
  1076. clk32k_in: clock-32k {
  1077. compatible = "fixed-clock";
  1078. clock-frequency = <32768>;
  1079. #clock-cells = <0>;
  1080. };
  1081. gpio-keys {
  1082. compatible = "gpio-keys";
  1083. key-home {
  1084. label = "Home";
  1085. gpios = <&gpio TEGRA_GPIO(I, 5) GPIO_ACTIVE_LOW>;
  1086. linux,code = <KEY_HOME>;
  1087. };
  1088. key-power {
  1089. label = "Power";
  1090. gpios = <&gpio TEGRA_GPIO(Q, 0) GPIO_ACTIVE_LOW>;
  1091. linux,code = <KEY_POWER>;
  1092. wakeup-source;
  1093. };
  1094. key-volume-down {
  1095. label = "Volume Down";
  1096. gpios = <&gpio TEGRA_GPIO(R, 1) GPIO_ACTIVE_LOW>;
  1097. linux,code = <KEY_VOLUMEDOWN>;
  1098. };
  1099. key-volume-up {
  1100. label = "Volume Up";
  1101. gpios = <&gpio TEGRA_GPIO(R, 2) GPIO_ACTIVE_LOW>;
  1102. linux,code = <KEY_VOLUMEUP>;
  1103. };
  1104. };
  1105. vdd_ac_bat_reg: regulator-acbat {
  1106. compatible = "regulator-fixed";
  1107. regulator-name = "vdd_ac_bat";
  1108. regulator-min-microvolt = <5000000>;
  1109. regulator-max-microvolt = <5000000>;
  1110. regulator-always-on;
  1111. };
  1112. dvdd_ts_reg: regulator-ts {
  1113. compatible = "regulator-fixed";
  1114. regulator-name = "dvdd_ts";
  1115. regulator-min-microvolt = <1800000>;
  1116. regulator-max-microvolt = <1800000>;
  1117. enable-active-high;
  1118. gpio = <&gpio TEGRA_GPIO(H, 5) GPIO_ACTIVE_HIGH>;
  1119. };
  1120. usb1_vbus_reg: regulator-usb1 {
  1121. compatible = "regulator-fixed";
  1122. regulator-name = "usb1_vbus";
  1123. regulator-min-microvolt = <5000000>;
  1124. regulator-max-microvolt = <5000000>;
  1125. enable-active-high;
  1126. gpio = <&gpio TEGRA_GPIO(N, 4) GPIO_ACTIVE_HIGH>;
  1127. gpio-open-drain;
  1128. vin-supply = <&tps65090_dcdc1_reg>;
  1129. };
  1130. usb3_vbus_reg: regulator-usb3 {
  1131. compatible = "regulator-fixed";
  1132. regulator-name = "usb2_vbus";
  1133. regulator-min-microvolt = <5000000>;
  1134. regulator-max-microvolt = <5000000>;
  1135. enable-active-high;
  1136. gpio = <&gpio TEGRA_GPIO(K, 6) GPIO_ACTIVE_HIGH>;
  1137. gpio-open-drain;
  1138. vin-supply = <&tps65090_dcdc1_reg>;
  1139. };
  1140. vdd_hdmi_reg: regulator-hdmi {
  1141. compatible = "regulator-fixed";
  1142. regulator-name = "vdd_hdmi_5v0";
  1143. regulator-min-microvolt = <5000000>;
  1144. regulator-max-microvolt = <5000000>;
  1145. vin-supply = <&tps65090_dcdc1_reg>;
  1146. };
  1147. vdd_cam_1v8_reg: regulator-cam {
  1148. compatible = "regulator-fixed";
  1149. regulator-name = "vdd_cam_1v8_reg";
  1150. regulator-min-microvolt = <1800000>;
  1151. regulator-max-microvolt = <1800000>;
  1152. enable-active-high;
  1153. gpio = <&palmas_gpio 6 0>;
  1154. };
  1155. vdd_5v0_hdmi: regulator-hdmicon {
  1156. compatible = "regulator-fixed";
  1157. regulator-name = "VDD_5V0_HDMI_CON";
  1158. regulator-min-microvolt = <5000000>;
  1159. regulator-max-microvolt = <5000000>;
  1160. gpio = <&gpio TEGRA_GPIO(K, 1) GPIO_ACTIVE_HIGH>;
  1161. enable-active-high;
  1162. vin-supply = <&tps65090_dcdc1_reg>;
  1163. };
  1164. sound {
  1165. compatible = "nvidia,tegra-audio-rt5640-dalmore",
  1166. "nvidia,tegra-audio-rt5640";
  1167. nvidia,model = "NVIDIA Tegra Dalmore";
  1168. nvidia,audio-routing =
  1169. "Headphones", "HPOR",
  1170. "Headphones", "HPOL",
  1171. "Speakers", "SPORP",
  1172. "Speakers", "SPORN",
  1173. "Speakers", "SPOLP",
  1174. "Speakers", "SPOLN",
  1175. "Mic Jack", "MICBIAS1",
  1176. "IN2P", "Mic Jack";
  1177. nvidia,i2s-controller = <&tegra_i2s1>;
  1178. nvidia,audio-codec = <&rt5640>;
  1179. nvidia,hp-det-gpios = <&gpio TEGRA_GPIO(R, 7) GPIO_ACTIVE_HIGH>;
  1180. clocks = <&tegra_car TEGRA114_CLK_PLL_A>,
  1181. <&tegra_car TEGRA114_CLK_PLL_A_OUT0>,
  1182. <&tegra_pmc TEGRA_PMC_CLK_OUT_1>;
  1183. clock-names = "pll_a", "pll_a_out0", "mclk";
  1184. assigned-clocks = <&tegra_car TEGRA114_CLK_EXTERN1>,
  1185. <&tegra_pmc TEGRA_PMC_CLK_OUT_1>;
  1186. assigned-clock-parents = <&tegra_car TEGRA114_CLK_PLL_A_OUT0>,
  1187. <&tegra_car TEGRA114_CLK_EXTERN1>;
  1188. };
  1189. };