ste-href-family-pinctrl.dtsi 4.9 KB

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  1. // SPDX-License-Identifier: GPL-2.0-or-later
  2. /*
  3. * Copyright 2013 Linaro Ltd.
  4. */
  5. #include "ste-dbx5x0-pinctrl.dtsi"
  6. / {
  7. soc {
  8. pinctrl {
  9. /* Settings for all SPI default and sleep states */
  10. spi2 {
  11. spi2_default_mode: spi_default {
  12. default_mux {
  13. function = "spi2";
  14. groups = "spi2_oc1_2";
  15. };
  16. default_cfg1 {
  17. pins = "GPIO216_AG12"; /* FRM */
  18. ste,config = <&gpio_out_hi>;
  19. };
  20. default_cfg2 {
  21. pins = "GPIO218_AH11"; /* RXD */
  22. ste,config = <&in_pd>;
  23. };
  24. default_cfg3 {
  25. pins =
  26. "GPIO215_AH13", /* TXD */
  27. "GPIO217_AH12"; /* CLK */
  28. ste,config = <&out_lo>;
  29. };
  30. };
  31. spi2_idle_mode: spi_idle {
  32. /*
  33. * The idle mode is basically sleep mode sans wakeups. Also
  34. * note that we have muxes the pins off the function here
  35. * as we do not state any muxing.
  36. */
  37. idle_cfg1 {
  38. pins = "GPIO218_AH11"; /* RXD */
  39. ste,config = <&slpm_in_pdis>;
  40. };
  41. idle_cfg2 {
  42. pins = "GPIO215_AH13"; /* TXD */
  43. ste,config = <&slpm_out_lo_pdis>;
  44. };
  45. idle_cfg3 {
  46. pins = "GPIO217_AH12"; /* CLK */
  47. ste,config = <&slpm_pdis>;
  48. };
  49. };
  50. spi2_sleep_mode: spi_sleep {
  51. sleep_cfg1 {
  52. pins =
  53. "GPIO216_AG12", /* FRM */
  54. "GPIO218_AH11"; /* RXD */
  55. ste,config = <&slpm_in_wkup_pdis>;
  56. };
  57. sleep_cfg2 {
  58. pins = "GPIO215_AH13"; /* TXD */
  59. ste,config = <&slpm_out_lo_wkup_pdis>;
  60. };
  61. sleep_cfg3 {
  62. pins = "GPIO217_AH12"; /* CLK */
  63. ste,config = <&slpm_wkup_pdis>;
  64. };
  65. };
  66. };
  67. mcde {
  68. lcd_default_mode: lcd_default {
  69. default_mux1 {
  70. /* Mux in VSI0 and all the data lines */
  71. function = "lcd";
  72. groups =
  73. "lcdvsi0_a_1", /* VSI0 for LCD */
  74. "lcd_d0_d7_a_1", /* Data lines */
  75. "lcdvsi1_a_1"; /* VSI1 for HDMI */
  76. };
  77. default_mux2 {
  78. function = "lcda";
  79. groups =
  80. "lcdaclk_b_1"; /* Clock line for TV-out */
  81. };
  82. default_cfg1 {
  83. pins =
  84. "GPIO68_E1", /* VSI0 */
  85. "GPIO69_E2"; /* VSI1 */
  86. ste,config = <&in_pu>;
  87. };
  88. };
  89. lcd_sleep_mode: lcd_sleep {
  90. sleep_cfg1 {
  91. pins = "GPIO69_E2"; /* VSI1 */
  92. ste,config = <&slpm_in_wkup_pdis>;
  93. };
  94. };
  95. };
  96. ske {
  97. /* SKE keys on position 2 in an 8x8 matrix */
  98. ske_kpa2_default_mode: ske_kpa2_default {
  99. default_mux {
  100. function = "kp";
  101. groups = "kp_a_2";
  102. };
  103. default_cfg1 {
  104. pins =
  105. "GPIO153_B17", /* I7 */
  106. "GPIO154_C16", /* I6 */
  107. "GPIO155_C19", /* I5 */
  108. "GPIO156_C17", /* I4 */
  109. "GPIO161_D21", /* I3 */
  110. "GPIO162_D20", /* I2 */
  111. "GPIO163_C20", /* I1 */
  112. "GPIO164_B21"; /* I0 */
  113. ste,config = <&in_pd>;
  114. };
  115. default_cfg2 {
  116. pins =
  117. "GPIO157_A18", /* O7 */
  118. "GPIO158_C18", /* O6 */
  119. "GPIO159_B19", /* O5 */
  120. "GPIO160_B20", /* O4 */
  121. "GPIO165_C21", /* O3 */
  122. "GPIO166_A22", /* O2 */
  123. "GPIO167_B24", /* O1 */
  124. "GPIO168_C22"; /* O0 */
  125. ste,config = <&out_lo>;
  126. };
  127. };
  128. ske_kpa2_sleep_mode: ske_kpa2_sleep {
  129. sleep_cfg1 {
  130. pins =
  131. "GPIO153_B17", /* I7 */
  132. "GPIO154_C16", /* I6 */
  133. "GPIO155_C19", /* I5 */
  134. "GPIO156_C17", /* I4 */
  135. "GPIO161_D21", /* I3 */
  136. "GPIO162_D20", /* I2 */
  137. "GPIO163_C20", /* I1 */
  138. "GPIO164_B21"; /* I0 */
  139. ste,config = <&slpm_in_pu_wkup_pdis_en>;
  140. };
  141. sleep_cfg2 {
  142. pins =
  143. "GPIO157_A18", /* O7 */
  144. "GPIO158_C18", /* O6 */
  145. "GPIO159_B19", /* O5 */
  146. "GPIO160_B20", /* O4 */
  147. "GPIO165_C21", /* O3 */
  148. "GPIO166_A22", /* O2 */
  149. "GPIO167_B24", /* O1 */
  150. "GPIO168_C22"; /* O0 */
  151. ste,config = <&slpm_out_lo_pdis>;
  152. };
  153. };
  154. /*
  155. * SKE keys on position 1 and "other C1" combi giving
  156. * six rows of six keys.
  157. */
  158. ske_kpaoc1_default_mode: ske_kpaoc1_default {
  159. default_mux {
  160. function = "kp";
  161. groups = "kp_a_1", "kp_oc1_1";
  162. };
  163. default_cfg1 {
  164. pins =
  165. "GPIO91_B6", /* KP_O0 */
  166. "GPIO90_A3", /* KP_O1 */
  167. "GPIO87_B3", /* KP_O2 */
  168. "GPIO86_C6", /* KP_O3 */
  169. "GPIO96_D8", /* KP_O6 */
  170. "GPIO94_D7"; /* KP_O7 */
  171. ste,config = <&out_lo>;
  172. };
  173. default_cfg2 {
  174. pins =
  175. "GPIO93_B7", /* KP_I0 */
  176. "GPIO92_D6", /* KP_I1 */
  177. "GPIO89_E6", /* KP_I2 */
  178. "GPIO88_C4", /* KP_I3 */
  179. "GPIO97_D9", /* KP_I6 */
  180. "GPIO95_E8"; /* KP_I7 */
  181. ste,config = <&in_pu>;
  182. };
  183. };
  184. };
  185. wlan {
  186. wlan_default_mode: wlan_default {
  187. /*
  188. * Activate this mode with the WLAN chip.
  189. * These are plain GPIO pins used by WLAN
  190. */
  191. default_cfg1 {
  192. pins =
  193. "GPIO226_AF8", /* WLAN_PMU_EN */
  194. "GPIO85_D5"; /* WLAN_ENA */
  195. ste,config = <&gpio_out_lo>;
  196. };
  197. default_cfg2 {
  198. pins = "GPIO4_AH6"; /* WLAN_IRQ on UART1 */
  199. ste,config = <&gpio_in_pu>;
  200. };
  201. };
  202. };
  203. };
  204. };
  205. };