rda8810pl.dtsi 2.9 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147
  1. // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
  2. /*
  3. * RDA8810PL SoC
  4. *
  5. * Copyright (c) 2017 Andreas Färber
  6. * Copyright (c) 2018 Manivannan Sadhasivam
  7. */
  8. #include <dt-bindings/interrupt-controller/irq.h>
  9. / {
  10. compatible = "rda,8810pl";
  11. interrupt-parent = <&intc>;
  12. #address-cells = <1>;
  13. #size-cells = <1>;
  14. cpus {
  15. #address-cells = <1>;
  16. #size-cells = <0>;
  17. cpu@0 {
  18. device_type = "cpu";
  19. compatible = "arm,cortex-a5";
  20. reg = <0x0>;
  21. };
  22. };
  23. sram@100000 {
  24. compatible = "mmio-sram";
  25. reg = <0x100000 0x10000>;
  26. #address-cells = <1>;
  27. #size-cells = <1>;
  28. ranges;
  29. };
  30. modem@10000000 {
  31. compatible = "simple-bus";
  32. #address-cells = <1>;
  33. #size-cells = <1>;
  34. ranges = <0x0 0x10000000 0xfffffff>;
  35. gpioc@1a08000 {
  36. compatible = "rda,8810pl-gpio";
  37. reg = <0x1a08000 0x1000>;
  38. gpio-controller;
  39. #gpio-cells = <2>;
  40. ngpios = <32>;
  41. };
  42. };
  43. apb@20800000 {
  44. compatible = "simple-bus";
  45. #address-cells = <1>;
  46. #size-cells = <1>;
  47. ranges = <0x0 0x20800000 0x100000>;
  48. intc: interrupt-controller@0 {
  49. compatible = "rda,8810pl-intc";
  50. reg = <0x0 0x1000>;
  51. interrupt-controller;
  52. #interrupt-cells = <2>;
  53. };
  54. };
  55. apb@20900000 {
  56. compatible = "simple-bus";
  57. #address-cells = <1>;
  58. #size-cells = <1>;
  59. ranges = <0x0 0x20900000 0x100000>;
  60. timer@10000 {
  61. compatible = "rda,8810pl-timer";
  62. reg = <0x10000 0x1000>;
  63. interrupts = <16 IRQ_TYPE_LEVEL_HIGH>,
  64. <17 IRQ_TYPE_LEVEL_HIGH>;
  65. interrupt-names = "hwtimer", "ostimer";
  66. };
  67. gpioa@30000 {
  68. compatible = "rda,8810pl-gpio";
  69. reg = <0x30000 0x1000>;
  70. gpio-controller;
  71. #gpio-cells = <2>;
  72. ngpios = <32>;
  73. interrupt-controller;
  74. #interrupt-cells = <2>;
  75. interrupts = <12 IRQ_TYPE_LEVEL_HIGH>;
  76. };
  77. gpiob@31000 {
  78. compatible = "rda,8810pl-gpio";
  79. reg = <0x31000 0x1000>;
  80. gpio-controller;
  81. #gpio-cells = <2>;
  82. ngpios = <32>;
  83. interrupt-controller;
  84. #interrupt-cells = <2>;
  85. interrupts = <13 IRQ_TYPE_LEVEL_HIGH>;
  86. };
  87. gpiod@32000 {
  88. compatible = "rda,8810pl-gpio";
  89. reg = <0x32000 0x1000>;
  90. gpio-controller;
  91. #gpio-cells = <2>;
  92. ngpios = <32>;
  93. interrupt-controller;
  94. #interrupt-cells = <2>;
  95. interrupts = <14 IRQ_TYPE_LEVEL_HIGH>;
  96. };
  97. };
  98. apb@20a00000 {
  99. compatible = "simple-bus";
  100. #address-cells = <1>;
  101. #size-cells = <1>;
  102. ranges = <0x0 0x20a00000 0x100000>;
  103. uart1: serial@0 {
  104. compatible = "rda,8810pl-uart";
  105. reg = <0x0 0x1000>;
  106. interrupts = <9 IRQ_TYPE_LEVEL_HIGH>;
  107. status = "disabled";
  108. };
  109. uart2: serial@10000 {
  110. compatible = "rda,8810pl-uart";
  111. reg = <0x10000 0x1000>;
  112. interrupts = <10 IRQ_TYPE_LEVEL_HIGH>;
  113. status = "disabled";
  114. };
  115. uart3: serial@90000 {
  116. compatible = "rda,8810pl-uart";
  117. reg = <0x90000 0x1000>;
  118. interrupts = <11 IRQ_TYPE_LEVEL_HIGH>;
  119. status = "disabled";
  120. };
  121. };
  122. l2: cache-controller@21100000 {
  123. compatible = "arm,pl310-cache";
  124. reg = <0x21100000 0x1000>;
  125. cache-unified;
  126. cache-level = <2>;
  127. };
  128. };