r8a7745-sk-rzg1e.dts 1.3 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. /*
  3. * Device Tree Source for the SK-RZG1E board
  4. *
  5. * Copyright (C) 2016-2017 Cogent Embedded, Inc.
  6. */
  7. /dts-v1/;
  8. #include "r8a7745.dtsi"
  9. #include <dt-bindings/gpio/gpio.h>
  10. / {
  11. model = "SK-RZG1E";
  12. compatible = "renesas,sk-rzg1e", "renesas,r8a7745";
  13. aliases {
  14. serial0 = &scif2;
  15. };
  16. chosen {
  17. bootargs = "ignore_loglevel rw root=/dev/nfs ip=on";
  18. stdout-path = "serial0:115200n8";
  19. };
  20. memory@40000000 {
  21. device_type = "memory";
  22. reg = <0 0x40000000 0 0x40000000>;
  23. };
  24. };
  25. &extal_clk {
  26. clock-frequency = <20000000>;
  27. };
  28. &pfc {
  29. scif2_pins: scif2 {
  30. groups = "scif2_data";
  31. function = "scif2";
  32. };
  33. ether_pins: ether {
  34. groups = "eth_link", "eth_mdio", "eth_rmii";
  35. function = "eth";
  36. };
  37. phy1_pins: phy1 {
  38. groups = "intc_irq8";
  39. function = "intc";
  40. };
  41. };
  42. &scif2 {
  43. pinctrl-0 = <&scif2_pins>;
  44. pinctrl-names = "default";
  45. status = "okay";
  46. };
  47. &ether {
  48. pinctrl-0 = <&ether_pins>, <&phy1_pins>;
  49. pinctrl-names = "default";
  50. phy-handle = <&phy1>;
  51. renesas,ether-link-active-low;
  52. status = "okay";
  53. phy1: ethernet-phy@1 {
  54. compatible = "ethernet-phy-id0022.1537",
  55. "ethernet-phy-ieee802.3-c22";
  56. reg = <1>;
  57. interrupt-parent = <&irqc>;
  58. interrupts = <8 IRQ_TYPE_LEVEL_LOW>;
  59. micrel,led-mode = <1>;
  60. reset-gpios = <&gpio1 24 GPIO_ACTIVE_LOW>;
  61. };
  62. };