r8a7743-sk-rzg1m.dts 1.4 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. /*
  3. * Device Tree Source for the SK-RZG1M board
  4. *
  5. * Copyright (C) 2016-2017 Cogent Embedded, Inc.
  6. */
  7. /dts-v1/;
  8. #include "r8a7743.dtsi"
  9. #include <dt-bindings/gpio/gpio.h>
  10. / {
  11. model = "SK-RZG1M";
  12. compatible = "renesas,sk-rzg1m", "renesas,r8a7743";
  13. aliases {
  14. serial0 = &scif0;
  15. };
  16. chosen {
  17. bootargs = "ignore_loglevel rw root=/dev/nfs ip=on";
  18. stdout-path = "serial0:115200n8";
  19. };
  20. memory@40000000 {
  21. device_type = "memory";
  22. reg = <0 0x40000000 0 0x40000000>;
  23. };
  24. memory@200000000 {
  25. device_type = "memory";
  26. reg = <2 0x00000000 0 0x40000000>;
  27. };
  28. };
  29. &extal_clk {
  30. clock-frequency = <20000000>;
  31. };
  32. &pfc {
  33. scif0_pins: scif0 {
  34. groups = "scif0_data_d";
  35. function = "scif0";
  36. };
  37. ether_pins: ether {
  38. groups = "eth_link", "eth_mdio", "eth_rmii";
  39. function = "eth";
  40. };
  41. phy1_pins: phy1 {
  42. groups = "intc_irq0";
  43. function = "intc";
  44. };
  45. };
  46. &scif0 {
  47. pinctrl-0 = <&scif0_pins>;
  48. pinctrl-names = "default";
  49. status = "okay";
  50. };
  51. &ether {
  52. pinctrl-0 = <&ether_pins>, <&phy1_pins>;
  53. pinctrl-names = "default";
  54. phy-handle = <&phy1>;
  55. renesas,ether-link-active-low;
  56. status = "okay";
  57. phy1: ethernet-phy@1 {
  58. compatible = "ethernet-phy-id0022.1537",
  59. "ethernet-phy-ieee802.3-c22";
  60. reg = <1>;
  61. interrupt-parent = <&irqc>;
  62. interrupts = <0 IRQ_TYPE_LEVEL_LOW>;
  63. micrel,led-mode = <1>;
  64. reset-gpios = <&gpio5 22 GPIO_ACTIVE_LOW>;
  65. };
  66. };