r7s72100-gr-peach.dts 2.8 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. /*
  3. * Device Tree Source for the GR-Peach board
  4. *
  5. * Copyright (C) 2017 Jacopo Mondi <[email protected]>
  6. * Copyright (C) 2016 Renesas Electronics
  7. */
  8. /dts-v1/;
  9. #include "r7s72100.dtsi"
  10. #include <dt-bindings/gpio/gpio.h>
  11. #include <dt-bindings/pinctrl/r7s72100-pinctrl.h>
  12. / {
  13. model = "GR-Peach";
  14. compatible = "renesas,gr-peach", "renesas,r7s72100";
  15. aliases {
  16. serial0 = &scif2;
  17. };
  18. chosen {
  19. bootargs = "ignore_loglevel rw root=/dev/mtdblock0";
  20. stdout-path = "serial0:115200n8";
  21. };
  22. memory@20000000 {
  23. device_type = "memory";
  24. reg = <0x20000000 0x00a00000>;
  25. };
  26. lbsc {
  27. #address-cells = <1>;
  28. #size-cells = <1>;
  29. };
  30. flash@18000000 {
  31. compatible = "mtd-rom";
  32. probe-type = "map_rom";
  33. reg = <0x18000000 0x00800000>;
  34. bank-width = <4>;
  35. device-width = <1>;
  36. clocks = <&mstp9_clks R7S72100_CLK_SPIBSC0>;
  37. power-domains = <&cpg_clocks>;
  38. #address-cells = <1>;
  39. #size-cells = <1>;
  40. rootfs@600000 {
  41. label = "rootfs";
  42. reg = <0x00600000 0x00200000>;
  43. };
  44. };
  45. leds {
  46. status = "okay";
  47. compatible = "gpio-leds";
  48. led1 {
  49. gpios = <&port6 12 GPIO_ACTIVE_HIGH>;
  50. };
  51. };
  52. };
  53. &pinctrl {
  54. scif2_pins: serial2 {
  55. /* P6_2 as RxD2; P6_3 as TxD2 */
  56. pinmux = <RZA1_PINMUX(6, 2, 7)>, <RZA1_PINMUX(6, 3, 7)>;
  57. };
  58. ether_pins: ether {
  59. /* Ethernet on Ports 1,3,5,10 */
  60. pinmux = <RZA1_PINMUX(1, 14, 4)>, /* P1_14 = ET_COL */
  61. <RZA1_PINMUX(3, 0, 2)>, /* P3_0 = ET_TXCLK */
  62. <RZA1_PINMUX(3, 3, 2)>, /* P3_3 = ET_MDIO */
  63. <RZA1_PINMUX(3, 4, 2)>, /* P3_4 = ET_RXCLK */
  64. <RZA1_PINMUX(3, 5, 2)>, /* P3_5 = ET_RXER */
  65. <RZA1_PINMUX(3, 6, 2)>, /* P3_6 = ET_RXDV */
  66. <RZA1_PINMUX(5, 9, 2)>, /* P5_9 = ET_MDC */
  67. <RZA1_PINMUX(10, 1, 4)>, /* P10_1 = ET_TXER */
  68. <RZA1_PINMUX(10, 2, 4)>, /* P10_2 = ET_TXEN */
  69. <RZA1_PINMUX(10, 3, 4)>, /* P10_3 = ET_CRS */
  70. <RZA1_PINMUX(10, 4, 4)>, /* P10_4 = ET_TXD0 */
  71. <RZA1_PINMUX(10, 5, 4)>, /* P10_5 = ET_TXD1 */
  72. <RZA1_PINMUX(10, 6, 4)>, /* P10_6 = ET_TXD2 */
  73. <RZA1_PINMUX(10, 7, 4)>, /* P10_7 = ET_TXD3 */
  74. <RZA1_PINMUX(10, 8, 4)>, /* P10_8 = ET_RXD0 */
  75. <RZA1_PINMUX(10, 9, 4)>, /* P10_9 = ET_RXD1 */
  76. <RZA1_PINMUX(10, 10, 4)>,/* P10_10 = ET_RXD2 */
  77. <RZA1_PINMUX(10, 11, 4)>;/* P10_11 = ET_RXD3 */
  78. };
  79. };
  80. &extal_clk {
  81. clock-frequency = <13333000>;
  82. };
  83. &usb_x1_clk {
  84. clock-frequency = <48000000>;
  85. };
  86. &mtu2 {
  87. status = "okay";
  88. };
  89. &ostm0 {
  90. status = "okay";
  91. };
  92. &ostm1 {
  93. status = "okay";
  94. };
  95. &scif2 {
  96. pinctrl-names = "default";
  97. pinctrl-0 = <&scif2_pins>;
  98. status = "okay";
  99. };
  100. &ether {
  101. pinctrl-names = "default";
  102. pinctrl-0 = <&ether_pins>;
  103. status = "okay";
  104. renesas,no-ether-link;
  105. phy-handle = <&phy0>;
  106. phy0: ethernet-phy@0 {
  107. compatible = "ethernet-phy-id0007.c0f0",
  108. "ethernet-phy-ieee802.3-c22";
  109. reg = <0>;
  110. reset-gpios = <&port4 2 GPIO_ACTIVE_LOW>;
  111. reset-delay-us = <5>;
  112. };
  113. };