omap3-igep0030-common.dtsi 3.0 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103
  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. * Common Device Tree Source for IGEP COM MODULE
  4. *
  5. * Copyright (C) 2014 Javier Martinez Canillas <[email protected]>
  6. * Copyright (C) 2014 Enric Balletbo i Serra <[email protected]>
  7. */
  8. #include "omap3-igep.dtsi"
  9. / {
  10. leds: gpio_leds {
  11. compatible = "gpio-leds";
  12. user0 {
  13. label = "omap3:red:user0";
  14. gpios = <&twl_gpio 18 GPIO_ACTIVE_LOW>; /* LEDA */
  15. default-state = "off";
  16. };
  17. user1 {
  18. label = "omap3:green:user1";
  19. gpios = <&twl_gpio 19 GPIO_ACTIVE_LOW>; /* LEDB */
  20. default-state = "off";
  21. };
  22. user2 {
  23. label = "omap3:red:user1";
  24. gpios = <&gpio1 16 GPIO_ACTIVE_LOW>; /* gpio_16 */
  25. default-state = "off";
  26. };
  27. };
  28. hsusb2_phy: hsusb2_phy {
  29. compatible = "usb-nop-xceiv";
  30. reset-gpios = <&gpio2 22 GPIO_ACTIVE_LOW>; /* gpio_54 */
  31. #phy-cells = <0>;
  32. };
  33. };
  34. &omap3_pmx_core {
  35. pinctrl-names = "default";
  36. pinctrl-0 = <&hsusb2_pins>;
  37. hsusb2_pins: pinmux_hsusb2_pins {
  38. pinctrl-single,pins = <
  39. OMAP3_CORE1_IOPAD(0x21d4, PIN_INPUT_PULLDOWN | MUX_MODE3) /* mcspi1_cs3.hsusb2_data2 */
  40. OMAP3_CORE1_IOPAD(0x21d6, PIN_INPUT_PULLDOWN | MUX_MODE3) /* mcspi2_clk.hsusb2_data7 */
  41. OMAP3_CORE1_IOPAD(0x21d8, PIN_INPUT_PULLDOWN | MUX_MODE3) /* mcspi2_simo.hsusb2_data4 */
  42. OMAP3_CORE1_IOPAD(0x21da, PIN_INPUT_PULLDOWN | MUX_MODE3) /* mcspi2_somi.hsusb2_data5 */
  43. OMAP3_CORE1_IOPAD(0x21dc, PIN_INPUT_PULLDOWN | MUX_MODE3) /* mcspi2_cs0.hsusb2_data6 */
  44. OMAP3_CORE1_IOPAD(0x21de, PIN_INPUT_PULLDOWN | MUX_MODE3) /* mcspi2_cs1.hsusb2_data3 */
  45. >;
  46. };
  47. uart2_pins: pinmux_uart2_pins {
  48. pinctrl-single,pins = <
  49. OMAP3_CORE1_IOPAD(0x216c, PIN_INPUT | MUX_MODE1) /* mcbsp3_dx.uart2_cts */
  50. OMAP3_CORE1_IOPAD(0x216e, PIN_OUTPUT | MUX_MODE1) /* mcbsp3_dr.uart2_rts */
  51. OMAP3_CORE1_IOPAD(0x2170, PIN_OUTPUT | MUX_MODE1) /* mcbsp3_clk.uart2_tx */
  52. OMAP3_CORE1_IOPAD(0x2172, PIN_INPUT | MUX_MODE1) /* mcbsp3_fsx.uart2_rx */
  53. >;
  54. };
  55. };
  56. &omap3_pmx_core2 {
  57. pinctrl-names = "default";
  58. pinctrl-0 = <&hsusb2_core2_pins>;
  59. hsusb2_core2_pins: pinmux_hsusb2_core2_pins {
  60. pinctrl-single,pins = <
  61. OMAP3630_CORE2_IOPAD(0x25f0, PIN_OUTPUT | MUX_MODE3) /* etk_d10.hsusb2_clk */
  62. OMAP3630_CORE2_IOPAD(0x25f2, PIN_OUTPUT | MUX_MODE3) /* etk_d11.hsusb2_stp */
  63. OMAP3630_CORE2_IOPAD(0x25f4, PIN_INPUT_PULLDOWN | MUX_MODE3) /* etk_d12.hsusb2_dir */
  64. OMAP3630_CORE2_IOPAD(0x25f6, PIN_INPUT_PULLDOWN | MUX_MODE3) /* etk_d13.hsusb2_nxt */
  65. OMAP3630_CORE2_IOPAD(0x25f8, PIN_INPUT_PULLDOWN | MUX_MODE3) /* etk_d14.hsusb2_data0 */
  66. OMAP3630_CORE2_IOPAD(0x25fa, PIN_INPUT_PULLDOWN | MUX_MODE3) /* etk_d15.hsusb2_data1 */
  67. >;
  68. };
  69. leds_core2_pins: pinmux_leds_core2_pins {
  70. pinctrl-single,pins = <
  71. OMAP3630_CORE2_IOPAD(0x25e0, PIN_OUTPUT | MUX_MODE4) /* etk_d2.gpio_16 */
  72. >;
  73. };
  74. };
  75. &usbhshost {
  76. port2-mode = "ehci-phy";
  77. };
  78. &usbhsehci {
  79. phys = <0 &hsusb2_phy>;
  80. };
  81. &uart2 {
  82. pinctrl-names = "default";
  83. pinctrl-0 = <&uart2_pins>;
  84. };
  85. &gpmc {
  86. ranges = <0 0 0x30000000 0x01000000>; /* CS0: 16MB for NAND */
  87. };