omap3-igep0020-common.dtsi 7.5 KB

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  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. * Common Device Tree Source for IGEPv2
  4. *
  5. * Copyright (C) 2014 Javier Martinez Canillas <[email protected]>
  6. * Copyright (C) 2014 Enric Balletbo i Serra <[email protected]>
  7. */
  8. #include "omap3-igep.dtsi"
  9. #include "omap-gpmc-smsc9221.dtsi"
  10. / {
  11. leds {
  12. pinctrl-names = "default";
  13. pinctrl-0 = <&leds_pins>;
  14. compatible = "gpio-leds";
  15. boot {
  16. label = "omap3:green:boot";
  17. gpios = <&gpio1 26 GPIO_ACTIVE_HIGH>;
  18. default-state = "on";
  19. };
  20. user0 {
  21. label = "omap3:red:user0";
  22. gpios = <&gpio1 27 GPIO_ACTIVE_HIGH>;
  23. default-state = "off";
  24. };
  25. user1 {
  26. label = "omap3:red:user1";
  27. gpios = <&gpio1 28 GPIO_ACTIVE_HIGH>;
  28. default-state = "off";
  29. };
  30. user2 {
  31. label = "omap3:green:user1";
  32. gpios = <&twl_gpio 19 GPIO_ACTIVE_LOW>;
  33. };
  34. };
  35. /* HS USB Port 1 Power */
  36. hsusb1_power: hsusb1_power_reg {
  37. compatible = "regulator-fixed";
  38. regulator-name = "hsusb1_vbus";
  39. regulator-min-microvolt = <3300000>;
  40. regulator-max-microvolt = <3300000>;
  41. gpio = <&twl_gpio 18 GPIO_ACTIVE_LOW>; /* GPIO LEDA */
  42. startup-delay-us = <70000>;
  43. };
  44. /* HS USB Host PHY on PORT 1 */
  45. hsusb1_phy: hsusb1_phy {
  46. compatible = "usb-nop-xceiv";
  47. reset-gpios = <&gpio1 24 GPIO_ACTIVE_LOW>; /* gpio_24 */
  48. vcc-supply = <&hsusb1_power>;
  49. #phy-cells = <0>;
  50. };
  51. tfp410: encoder {
  52. compatible = "ti,tfp410";
  53. powerdown-gpios = <&gpio6 10 GPIO_ACTIVE_LOW>; /* gpio_170 */
  54. ports {
  55. #address-cells = <1>;
  56. #size-cells = <0>;
  57. port@0 {
  58. reg = <0>;
  59. tfp410_in: endpoint {
  60. remote-endpoint = <&dpi_out>;
  61. };
  62. };
  63. port@1 {
  64. reg = <1>;
  65. tfp410_out: endpoint {
  66. remote-endpoint = <&dvi_connector_in>;
  67. };
  68. };
  69. };
  70. };
  71. dvi0: connector {
  72. compatible = "dvi-connector";
  73. label = "dvi";
  74. digital;
  75. ddc-i2c-bus = <&i2c3>;
  76. port {
  77. dvi_connector_in: endpoint {
  78. remote-endpoint = <&tfp410_out>;
  79. };
  80. };
  81. };
  82. };
  83. &omap3_pmx_core {
  84. pinctrl-names = "default";
  85. pinctrl-0 = <
  86. &tfp410_pins
  87. &dss_dpi_pins
  88. >;
  89. tfp410_pins: pinmux_tfp410_pins {
  90. pinctrl-single,pins = <
  91. OMAP3_CORE1_IOPAD(0x21c6, PIN_OUTPUT | MUX_MODE4) /* hdq_sio.gpio_170 */
  92. >;
  93. };
  94. dss_dpi_pins: pinmux_dss_dpi_pins {
  95. pinctrl-single,pins = <
  96. OMAP3_CORE1_IOPAD(0x20d4, PIN_OUTPUT | MUX_MODE0) /* dss_pclk.dss_pclk */
  97. OMAP3_CORE1_IOPAD(0x20d6, PIN_OUTPUT | MUX_MODE0) /* dss_hsync.dss_hsync */
  98. OMAP3_CORE1_IOPAD(0x20d8, PIN_OUTPUT | MUX_MODE0) /* dss_vsync.dss_vsync */
  99. OMAP3_CORE1_IOPAD(0x20da, PIN_OUTPUT | MUX_MODE0) /* dss_acbias.dss_acbias */
  100. OMAP3_CORE1_IOPAD(0x20dc, PIN_OUTPUT | MUX_MODE0) /* dss_data0.dss_data0 */
  101. OMAP3_CORE1_IOPAD(0x20de, PIN_OUTPUT | MUX_MODE0) /* dss_data1.dss_data1 */
  102. OMAP3_CORE1_IOPAD(0x20e0, PIN_OUTPUT | MUX_MODE0) /* dss_data2.dss_data2 */
  103. OMAP3_CORE1_IOPAD(0x20e2, PIN_OUTPUT | MUX_MODE0) /* dss_data3.dss_data3 */
  104. OMAP3_CORE1_IOPAD(0x20e4, PIN_OUTPUT | MUX_MODE0) /* dss_data4.dss_data4 */
  105. OMAP3_CORE1_IOPAD(0x20e6, PIN_OUTPUT | MUX_MODE0) /* dss_data5.dss_data5 */
  106. OMAP3_CORE1_IOPAD(0x20e8, PIN_OUTPUT | MUX_MODE0) /* dss_data6.dss_data6 */
  107. OMAP3_CORE1_IOPAD(0x20ea, PIN_OUTPUT | MUX_MODE0) /* dss_data7.dss_data7 */
  108. OMAP3_CORE1_IOPAD(0x20ec, PIN_OUTPUT | MUX_MODE0) /* dss_data8.dss_data8 */
  109. OMAP3_CORE1_IOPAD(0x20ee, PIN_OUTPUT | MUX_MODE0) /* dss_data9.dss_data9 */
  110. OMAP3_CORE1_IOPAD(0x20f0, PIN_OUTPUT | MUX_MODE0) /* dss_data10.dss_data10 */
  111. OMAP3_CORE1_IOPAD(0x20f2, PIN_OUTPUT | MUX_MODE0) /* dss_data11.dss_data11 */
  112. OMAP3_CORE1_IOPAD(0x20f4, PIN_OUTPUT | MUX_MODE0) /* dss_data12.dss_data12 */
  113. OMAP3_CORE1_IOPAD(0x20f6, PIN_OUTPUT | MUX_MODE0) /* dss_data13.dss_data13 */
  114. OMAP3_CORE1_IOPAD(0x20f8, PIN_OUTPUT | MUX_MODE0) /* dss_data14.dss_data14 */
  115. OMAP3_CORE1_IOPAD(0x20fa, PIN_OUTPUT | MUX_MODE0) /* dss_data15.dss_data15 */
  116. OMAP3_CORE1_IOPAD(0x20fc, PIN_OUTPUT | MUX_MODE0) /* dss_data16.dss_data16 */
  117. OMAP3_CORE1_IOPAD(0x20fe, PIN_OUTPUT | MUX_MODE0) /* dss_data17.dss_data17 */
  118. OMAP3_CORE1_IOPAD(0x2100, PIN_OUTPUT | MUX_MODE0) /* dss_data18.dss_data18 */
  119. OMAP3_CORE1_IOPAD(0x2102, PIN_OUTPUT | MUX_MODE0) /* dss_data19.dss_data19 */
  120. OMAP3_CORE1_IOPAD(0x2104, PIN_OUTPUT | MUX_MODE0) /* dss_data20.dss_data20 */
  121. OMAP3_CORE1_IOPAD(0x2106, PIN_OUTPUT | MUX_MODE0) /* dss_data21.dss_data21 */
  122. OMAP3_CORE1_IOPAD(0x2108, PIN_OUTPUT | MUX_MODE0) /* dss_data22.dss_data22 */
  123. OMAP3_CORE1_IOPAD(0x210a, PIN_OUTPUT | MUX_MODE0) /* dss_data23.dss_data23 */
  124. >;
  125. };
  126. uart2_pins: pinmux_uart2_pins {
  127. pinctrl-single,pins = <
  128. OMAP3_CORE1_IOPAD(0x2174, PIN_INPUT | MUX_MODE0) /* uart2_cts.uart2_cts */
  129. OMAP3_CORE1_IOPAD(0x2176, PIN_OUTPUT | MUX_MODE0) /* uart2_rts .uart2_rts*/
  130. OMAP3_CORE1_IOPAD(0x2178, PIN_OUTPUT | MUX_MODE0) /* uart2_tx.uart2_tx */
  131. OMAP3_CORE1_IOPAD(0x217a, PIN_INPUT | MUX_MODE0) /* uart2_rx.uart2_rx */
  132. >;
  133. };
  134. smsc9221_pins: pinmux_smsc9221_pins {
  135. pinctrl-single,pins = <
  136. OMAP3_CORE1_IOPAD(0x21d2, PIN_INPUT | MUX_MODE4) /* mcspi1_cs2.gpio_176 */
  137. >;
  138. };
  139. };
  140. &omap3_pmx_core2 {
  141. pinctrl-names = "default";
  142. pinctrl-0 = <
  143. &hsusbb1_pins
  144. >;
  145. hsusbb1_pins: pinmux_hsusbb1_pins {
  146. pinctrl-single,pins = <
  147. OMAP3630_CORE2_IOPAD(0x25da, PIN_OUTPUT | MUX_MODE3) /* etk_ctl.hsusb1_clk */
  148. OMAP3630_CORE2_IOPAD(0x25d8, PIN_OUTPUT | MUX_MODE3) /* etk_clk.hsusb1_stp */
  149. OMAP3630_CORE2_IOPAD(0x25ec, PIN_INPUT_PULLDOWN | MUX_MODE3) /* etk_d8.hsusb1_dir */
  150. OMAP3630_CORE2_IOPAD(0x25ee, PIN_INPUT_PULLDOWN | MUX_MODE3) /* etk_d9.hsusb1_nxt */
  151. OMAP3630_CORE2_IOPAD(0x25dc, PIN_INPUT_PULLDOWN | MUX_MODE3) /* etk_d0.hsusb1_data0 */
  152. OMAP3630_CORE2_IOPAD(0x25de, PIN_INPUT_PULLDOWN | MUX_MODE3) /* etk_d1.hsusb1_data1 */
  153. OMAP3630_CORE2_IOPAD(0x25e0, PIN_INPUT_PULLDOWN | MUX_MODE3) /* etk_d2.hsusb1_data2 */
  154. OMAP3630_CORE2_IOPAD(0x25e2, PIN_INPUT_PULLDOWN | MUX_MODE3) /* etk_d3.hsusb1_data7 */
  155. OMAP3630_CORE2_IOPAD(0x25e4, PIN_INPUT_PULLDOWN | MUX_MODE3) /* etk_d4.hsusb1_data4 */
  156. OMAP3630_CORE2_IOPAD(0x25e6, PIN_INPUT_PULLDOWN | MUX_MODE3) /* etk_d5.hsusb1_data5 */
  157. OMAP3630_CORE2_IOPAD(0x25e8, PIN_INPUT_PULLDOWN | MUX_MODE3) /* etk_d6.hsusb1_data6 */
  158. OMAP3630_CORE2_IOPAD(0x25ea, PIN_INPUT_PULLDOWN | MUX_MODE3) /* etk_d7.hsusb1_data3 */
  159. >;
  160. };
  161. leds_pins: pinmux_leds_pins {
  162. pinctrl-single,pins = <
  163. OMAP3630_CORE2_IOPAD(0x25f4, PIN_OUTPUT | MUX_MODE4) /* etk_d12.gpio_26 */
  164. OMAP3630_CORE2_IOPAD(0x25f6, PIN_OUTPUT | MUX_MODE4) /* etk_d13.gpio_27 */
  165. OMAP3630_CORE2_IOPAD(0x25f8, PIN_OUTPUT | MUX_MODE4) /* etk_d14.gpio_28 */
  166. >;
  167. };
  168. mmc1_wp_pins: pinmux_mmc1_cd_pins {
  169. pinctrl-single,pins = <
  170. OMAP3630_CORE2_IOPAD(0x25fa, PIN_INPUT | MUX_MODE4) /* etk_d15.gpio_29 */
  171. >;
  172. };
  173. };
  174. &i2c3 {
  175. clock-frequency = <100000>;
  176. /*
  177. * Display monitor features are burnt in the EEPROM
  178. * as EDID data.
  179. */
  180. eeprom@50 {
  181. compatible = "ti,eeprom";
  182. reg = <0x50>;
  183. };
  184. };
  185. &gpmc {
  186. ranges = <0 0 0x30000000 0x01000000>, /* CS0: 16MB for NAND */
  187. <5 0 0x2c000000 0x01000000>; /* CS5: 16MB for ethernet */
  188. ethernet@gpmc {
  189. pinctrl-names = "default";
  190. pinctrl-0 = <&smsc9221_pins>;
  191. reg = <5 0 0xff>;
  192. interrupt-parent = <&gpio6>;
  193. interrupts = <16 IRQ_TYPE_LEVEL_LOW>;
  194. };
  195. };
  196. &uart2 {
  197. pinctrl-names = "default";
  198. pinctrl-0 = <&uart2_pins>;
  199. };
  200. &usbhshost {
  201. port1-mode = "ehci-phy";
  202. };
  203. &usbhsehci {
  204. phys = <&hsusb1_phy>;
  205. };
  206. &vpll2 {
  207. /* Needed for DSS */
  208. regulator-name = "vdds_dsi";
  209. };
  210. &dss {
  211. status = "okay";
  212. port {
  213. dpi_out: endpoint {
  214. remote-endpoint = <&tfp410_in>;
  215. data-lines = <24>;
  216. };
  217. };
  218. };
  219. &mmc1 {
  220. pinctrl-0 = <&mmc1_pins &mmc1_wp_pins>;
  221. wp-gpios = <&gpio1 29 GPIO_ACTIVE_LOW>; /* gpio_29 */
  222. };