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samsung-sm8650
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android_kernel_samsung_sm8650_ksu
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android_kernel_...
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arch
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arm
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boot
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dts
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omap2.dtsi

omap2.dtsi 7.0 KB
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  1. // SPDX-License-Identifier: GPL-2.0-only
    2. 

  2. /*
    3. 

  3.  * Device Tree Source for OMAP2 SoC
    4. 

  4.  *
    5. 

  5.  * Copyright (C) 2011 Texas Instruments Incorporated - https://www.ti.com/
    6. 

  6.  */
    7. 

  7. 

  8. #include <dt-bindings/bus/ti-sysc.h>
    9. 

  9. #include <dt-bindings/gpio/gpio.h>
    10. 

  10. #include <dt-bindings/interrupt-controller/irq.h>
    11. 

  11. #include <dt-bindings/pinctrl/omap.h>
    12. 

  12. 

  13. / {
    14. 

  14. 	compatible = "ti,omap2430", "ti,omap2420", "ti,omap2";
    15. 

  15. 	interrupt-parent = <&intc>;
    16. 

  16. 	#address-cells = <1>;
    17. 

  17. 	#size-cells = <1>;
    18. 

  18. 	chosen { };
    19. 

  19. 

  20. 	aliases {
    21. 

  21. 		serial0 = &uart1;
    22. 

  22. 		serial1 = &uart2;
    23. 

  23. 		serial2 = &uart3;
    24. 

  24. 		i2c0 = &i2c1;
    25. 

  25. 		i2c1 = &i2c2;
    26. 

  26. 	};
    27. 

  27. 

  28. 	cpus {
    29. 

  29. 		#address-cells = <0>;
    30. 

  30. 		#size-cells = <0>;
    31. 

  31. 

  32. 		cpu {
    33. 

  33. 			compatible = "arm,arm1136jf-s";
    34. 

  34. 			device_type = "cpu";
    35. 

  35. 		};
    36. 

  36. 	};
    37. 

  37. 

  38. 	pmu {
    39. 

  39. 		compatible = "arm,arm1136-pmu";
    40. 

  40. 		interrupts = <3>;
    41. 

  41. 	};
    42. 

  42. 

  43. 	soc {
    44. 

  44. 		compatible = "ti,omap-infra";
    45. 

  45. 		mpu {
    46. 

  46. 			compatible = "ti,omap2-mpu";
    47. 

  47. 			ti,hwmods = "mpu";
    48. 

  48. 		};
    49. 

  49. 	};
    50. 

  50. 

  51. 	ocp {
    52. 

  52. 		compatible = "simple-bus";
    53. 

  53. 		#address-cells = <1>;
    54. 

  54. 		#size-cells = <1>;
    55. 

  55. 		ranges;
    56. 

  56. 		ti,hwmods = "l3_main";
    57. 

  57. 

  58. 		aes: aes@480a6000 {
    59. 

  59. 			compatible = "ti,omap2-aes";
    60. 

  60. 			ti,hwmods = "aes";
    61. 

  61. 			reg = <0x480a6000 0x50>;
    62. 

  62. 			dmas = <&sdma 9 &sdma 10>;
    63. 

  63. 			dma-names = "tx", "rx";
    64. 

  64. 		};
    65. 

  65. 

  66. 		hdq1w: 1w@480b2000 {
    67. 

  67. 			compatible = "ti,omap2420-1w";
    68. 

  68. 			ti,hwmods = "hdq1w";
    69. 

  69. 			reg = <0x480b2000 0x1000>;
    70. 

  70. 			interrupts = <58>;
    71. 

  71. 		};
    72. 

  72. 

  73. 		intc: interrupt-controller@1 {
    74. 

  74. 			compatible = "ti,omap2-intc";
    75. 

  75. 			interrupt-controller;
    76. 

  76. 			#interrupt-cells = <1>;
    77. 

  77. 			reg = <0x480FE000 0x1000>;
    78. 

  78. 		};
    79. 

  79. 

  80. 		target-module@48056000 {
    81. 

  81. 			compatible = "ti,sysc-omap2", "ti,sysc";
    82. 

  82. 			reg = <0x48056000 0x4>,
    83. 

  83. 			      <0x4805602c 0x4>,
    84. 

  84. 			      <0x48056028 0x4>;
    85. 

  85. 			reg-names = "rev", "sysc", "syss";
    86. 

  86. 			ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY |
    87. 

  87. 					 SYSC_OMAP2_EMUFREE |
    88. 

  88. 					 SYSC_OMAP2_SOFTRESET |
    89. 

  89. 					 SYSC_OMAP2_AUTOIDLE)>;
    90. 

  90. 			ti,sysc-midle = <SYSC_IDLE_FORCE>,
    91. 

  91. 					<SYSC_IDLE_NO>,
    92. 

  92. 					<SYSC_IDLE_SMART>;
    93. 

  93. 			ti,syss-mask = <1>;
    94. 

  94. 			clocks = <&core_l3_ck>;
    95. 

  95. 			clock-names = "fck";
    96. 

  96. 			#address-cells = <1>;
    97. 

  97. 			#size-cells = <1>;
    98. 

  98. 			ranges = <0 0x48056000 0x1000>;
    99. 

  99. 

  100. 			sdma: dma-controller@0 {
    101. 

  101. 				compatible = "ti,omap2420-sdma", "ti,omap-sdma";
    102. 

  102. 				reg = <0 0x1000>;
    103. 

  103. 				interrupts = <12>,
    104. 

  104. 					     <13>,
    105. 

  105. 					     <14>,
    106. 

  106. 					     <15>;
    107. 

  107. 				#dma-cells = <1>;
    108. 

  108. 				dma-channels = <32>;
    109. 

  109. 				dma-requests = <64>;
    110. 

  110. 			};
    111. 

  111. 		};
    112. 

  112. 

  113. 		i2c1: i2c@48070000 {
    114. 

  114. 			compatible = "ti,omap2-i2c";
    115. 

  115. 			ti,hwmods = "i2c1";
    116. 

  116. 			reg = <0x48070000 0x80>;
    117. 

  117. 			#address-cells = <1>;
    118. 

  118. 			#size-cells = <0>;
    119. 

  119. 			interrupts = <56>;
    120. 

  120. 		};
    121. 

  121. 

  122. 		i2c2: i2c@48072000 {
    123. 

  123. 			compatible = "ti,omap2-i2c";
    124. 

  124. 			ti,hwmods = "i2c2";
    125. 

  125. 			reg = <0x48072000 0x80>;
    126. 

  126. 			#address-cells = <1>;
    127. 

  127. 			#size-cells = <0>;
    128. 

  128. 			interrupts = <57>;
    129. 

  129. 		};
    130. 

  130. 

  131. 		mcspi1: spi@48098000 {
    132. 

  132. 			compatible = "ti,omap2-mcspi";
    133. 

  133. 			ti,hwmods = "mcspi1";
    134. 

  134. 			reg = <0x48098000 0x100>;
    135. 

  135. 			interrupts = <65>;
    136. 

  136. 			dmas = <&sdma 35 &sdma 36 &sdma 37 &sdma 38
    137. 

  137. 				&sdma 39 &sdma 40 &sdma 41 &sdma 42>;
    138. 

  138. 			dma-names = "tx0", "rx0", "tx1", "rx1",
    139. 

  139. 				    "tx2", "rx2", "tx3", "rx3";
    140. 

  140. 		};
    141. 

  141. 

  142. 		mcspi2: spi@4809a000 {
    143. 

  143. 			compatible = "ti,omap2-mcspi";
    144. 

  144. 			ti,hwmods = "mcspi2";
    145. 

  145. 			reg = <0x4809a000 0x100>;
    146. 

  146. 			interrupts = <66>;
    147. 

  147. 			dmas = <&sdma 43 &sdma 44 &sdma 45 &sdma 46>;
    148. 

  148. 			dma-names = "tx0", "rx0", "tx1", "rx1";
    149. 

  149. 		};
    150. 

  150. 

  151. 		rng: rng@480a0000 {
    152. 

  152. 			compatible = "ti,omap2-rng";
    153. 

  153. 			ti,hwmods = "rng";
    154. 

  154. 			reg = <0x480a0000 0x50>;
    155. 

  155. 			interrupts = <52>;
    156. 

  156. 		};
    157. 

  157. 

  158. 		sham: sham@480a4000 {
    159. 

  159. 			compatible = "ti,omap2-sham";
    160. 

  160. 			ti,hwmods = "sham";
    161. 

  161. 			reg = <0x480a4000 0x64>;
    162. 

  162. 			interrupts = <51>;
    163. 

  163. 			dmas = <&sdma 13>;
    164. 

  164. 			dma-names = "rx";
    165. 

  165. 		};
    166. 

  166. 

  167. 		uart1: serial@4806a000 {
    168. 

  168. 			compatible = "ti,omap2-uart";
    169. 

  169. 			ti,hwmods = "uart1";
    170. 

  170. 			reg = <0x4806a000 0x2000>;
    171. 

  171. 			interrupts = <72>;
    172. 

  172. 			dmas = <&sdma 49 &sdma 50>;
    173. 

  173. 			dma-names = "tx", "rx";
    174. 

  174. 			clock-frequency = <48000000>;
    175. 

  175. 		};
    176. 

  176. 

  177. 		uart2: serial@4806c000 {
    178. 

  178. 			compatible = "ti,omap2-uart";
    179. 

  179. 			ti,hwmods = "uart2";
    180. 

  180. 			reg = <0x4806c000 0x400>;
    181. 

  181. 			interrupts = <73>;
    182. 

  182. 			dmas = <&sdma 51 &sdma 52>;
    183. 

  183. 			dma-names = "tx", "rx";
    184. 

  184. 			clock-frequency = <48000000>;
    185. 

  185. 		};
    186. 

  186. 

  187. 		uart3: serial@4806e000 {
    188. 

  188. 			compatible = "ti,omap2-uart";
    189. 

  189. 			ti,hwmods = "uart3";
    190. 

  190. 			reg = <0x4806e000 0x400>;
    191. 

  191. 			interrupts = <74>;
    192. 

  192. 			dmas = <&sdma 53 &sdma 54>;
    193. 

  193. 			dma-names = "tx", "rx";
    194. 

  194. 			clock-frequency = <48000000>;
    195. 

  195. 		};
    196. 

  196. 

  197. 		timer2_target: target-module@4802a000 {
    198. 

  198. 			compatible = "ti,sysc-omap2-timer", "ti,sysc";
    199. 

  199. 			reg = <0x4802a000 0x4>,
    200. 

  200. 			      <0x4802a010 0x4>,
    201. 

  201. 			      <0x4802a014 0x4>;
    202. 

  202. 			reg-names = "rev", "sysc", "syss";
    203. 

  203. 			ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY |
    204. 

  204. 					 SYSC_OMAP2_EMUFREE |
    205. 

  205. 					 SYSC_OMAP2_ENAWAKEUP |
    206. 

  206. 					 SYSC_OMAP2_SOFTRESET |
    207. 

  207. 					 SYSC_OMAP2_AUTOIDLE)>;
    208. 

  208. 			ti,sysc-sidle = <SYSC_IDLE_FORCE>,
    209. 

  209. 					<SYSC_IDLE_NO>,
    210. 

  210. 					<SYSC_IDLE_SMART>;
    211. 

  211. 			ti,syss-mask = <1>;
    212. 

  212. 			clocks = <&gpt2_fck>, <&gpt2_ick>;
    213. 

  213. 			clock-names = "fck", "ick";
    214. 

  214. 			#address-cells = <1>;
    215. 

  215. 			#size-cells = <1>;
    216. 

  216. 			ranges = <0x0 0x4802a000 0x1000>;
    217. 

  217. 

  218. 			timer2: timer@0 {
    219. 

  219. 				compatible = "ti,omap2420-timer";
    220. 

  220. 				reg = <0 0x400>;
    221. 

  221. 				interrupts = <38>;
    222. 

  222. 			};
    223. 

  223. 		};
    224. 

  224. 

  225. 		timer3: timer@48078000 {
    226. 

  226. 			compatible = "ti,omap2420-timer";
    227. 

  227. 			reg = <0x48078000 0x400>;
    228. 

  228. 			interrupts = <39>;
    229. 

  229. 			ti,hwmods = "timer3";
    230. 

  230. 		};
    231. 

  231. 

  232. 		timer4: timer@4807a000 {
    233. 

  233. 			compatible = "ti,omap2420-timer";
    234. 

  234. 			reg = <0x4807a000 0x400>;
    235. 

  235. 			interrupts = <40>;
    236. 

  236. 			ti,hwmods = "timer4";
    237. 

  237. 		};
    238. 

  238. 

  239. 		timer5: timer@4807c000 {
    240. 

  240. 			compatible = "ti,omap2420-timer";
    241. 

  241. 			reg = <0x4807c000 0x400>;
    242. 

  242. 			interrupts = <41>;
    243. 

  243. 			ti,hwmods = "timer5";
    244. 

  244. 			ti,timer-dsp;
    245. 

  245. 		};
    246. 

  246. 

  247. 		timer6: timer@4807e000 {
    248. 

  248. 			compatible = "ti,omap2420-timer";
    249. 

  249. 			reg = <0x4807e000 0x400>;
    250. 

  250. 			interrupts = <42>;
    251. 

  251. 			ti,hwmods = "timer6";
    252. 

  252. 			ti,timer-dsp;
    253. 

  253. 		};
    254. 

  254. 

  255. 		timer7: timer@48080000 {
    256. 

  256. 			compatible = "ti,omap2420-timer";
    257. 

  257. 			reg = <0x48080000 0x400>;
    258. 

  258. 			interrupts = <43>;
    259. 

  259. 			ti,hwmods = "timer7";
    260. 

  260. 			ti,timer-dsp;
    261. 

  261. 		};
    262. 

  262. 

  263. 		timer8: timer@48082000 {
    264. 

  264. 			compatible = "ti,omap2420-timer";
    265. 

  265. 			reg = <0x48082000 0x400>;
    266. 

  266. 			interrupts = <44>;
    267. 

  267. 			ti,hwmods = "timer8";
    268. 

  268. 			ti,timer-dsp;
    269. 

  269. 		};
    270. 

  270. 

  271. 		timer9: timer@48084000 {
    272. 

  272. 			compatible = "ti,omap2420-timer";
    273. 

  273. 			reg = <0x48084000 0x400>;
    274. 

  274. 			interrupts = <45>;
    275. 

  275. 			ti,hwmods = "timer9";
    276. 

  276. 			ti,timer-pwm;
    277. 

  277. 		};
    278. 

  278. 

  279. 		timer10: timer@48086000 {
    280. 

  280. 			compatible = "ti,omap2420-timer";
    281. 

  281. 			reg = <0x48086000 0x400>;
    282. 

  282. 			interrupts = <46>;
    283. 

  283. 			ti,hwmods = "timer10";
    284. 

  284. 			ti,timer-pwm;
    285. 

  285. 		};
    286. 

  286. 

  287. 		timer11: timer@48088000 {
    288. 

  288. 			compatible = "ti,omap2420-timer";
    289. 

  289. 			reg = <0x48088000 0x400>;
    290. 

  290. 			interrupts = <47>;
    291. 

  291. 			ti,hwmods = "timer11";
    292. 

  292. 			ti,timer-pwm;
    293. 

  293. 		};
    294. 

  294. 

  295. 		timer12: timer@4808a000 {
    296. 

  296. 			compatible = "ti,omap2420-timer";
    297. 

  297. 			reg = <0x4808a000 0x400>;
    298. 

  298. 			interrupts = <48>;
    299. 

  299. 			ti,hwmods = "timer12";
    300. 

  300. 			ti,timer-pwm;
    301. 

  301. 		};
    302. 

  302. 

  303. 		dss: dss@48050000 {
    304. 

  304. 			compatible = "ti,omap2-dss";
    305. 

  305. 			reg = <0x48050000 0x400>;
    306. 

  306. 			status = "disabled";
    307. 

  307. 			ti,hwmods = "dss_core";
    308. 

  308. 			#address-cells = <1>;
    309. 

  309. 			#size-cells = <1>;
    310. 

  310. 			ranges;
    311. 

  311. 

  312. 			dispc@48050400 {
    313. 

  313. 				compatible = "ti,omap2-dispc";
    314. 

  314. 				reg = <0x48050400 0x400>;
    315. 

  315. 				interrupts = <25>;
    316. 

  316. 				ti,hwmods = "dss_dispc";
    317. 

  317. 			};
    318. 

  318. 

  319. 			rfbi: encoder@48050800 {
    320. 

  320. 				compatible = "ti,omap2-rfbi";
    321. 

  321. 				reg = <0x48050800 0x400>;
    322. 

  322. 				status = "disabled";
    323. 

  323. 				ti,hwmods = "dss_rfbi";
    324. 

  324. 			};
    325. 

  325. 

  326. 			venc: encoder@48050c00 {
    327. 

  327. 				compatible = "ti,omap2-venc";
    328. 

  328. 				reg = <0x48050c00 0x400>;
    329. 

  329. 				status = "disabled";
    330. 

  330. 				ti,hwmods = "dss_venc";
    331. 

  331. 			};
    332. 

  332. 		};
    333. 

  333. 	};
    334. 

  334. };
    335.