nuvoton-wpcm450.dtsi 7.4 KB

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  1. // SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
  2. // Copyright 2021 Jonathan Neuschäfer
  3. #include <dt-bindings/interrupt-controller/irq.h>
  4. / {
  5. compatible = "nuvoton,wpcm450";
  6. #address-cells = <1>;
  7. #size-cells = <1>;
  8. aliases {
  9. gpio0 = &gpio0;
  10. gpio1 = &gpio1;
  11. gpio2 = &gpio2;
  12. gpio3 = &gpio3;
  13. gpio4 = &gpio4;
  14. gpio5 = &gpio5;
  15. gpio6 = &gpio6;
  16. gpio7 = &gpio7;
  17. };
  18. cpus {
  19. #address-cells = <1>;
  20. #size-cells = <0>;
  21. cpu@0 {
  22. compatible = "arm,arm926ej-s";
  23. device_type = "cpu";
  24. reg = <0>;
  25. };
  26. };
  27. clk24m: clock-24mhz {
  28. /* 24 MHz dummy clock */
  29. compatible = "fixed-clock";
  30. clock-frequency = <24000000>;
  31. #clock-cells = <0>;
  32. };
  33. soc {
  34. compatible = "simple-bus";
  35. #address-cells = <1>;
  36. #size-cells = <1>;
  37. interrupt-parent = <&aic>;
  38. ranges;
  39. gcr: syscon@b0000000 {
  40. compatible = "nuvoton,wpcm450-gcr", "syscon", "simple-mfd";
  41. reg = <0xb0000000 0x200>;
  42. };
  43. serial0: serial@b8000000 {
  44. compatible = "nuvoton,wpcm450-uart";
  45. reg = <0xb8000000 0x20>;
  46. reg-shift = <2>;
  47. interrupts = <7 IRQ_TYPE_LEVEL_HIGH>;
  48. clocks = <&clk24m>;
  49. pinctrl-names = "default";
  50. pinctrl-0 = <&bsp_pins>;
  51. status = "disabled";
  52. };
  53. serial1: serial@b8000100 {
  54. compatible = "nuvoton,wpcm450-uart";
  55. reg = <0xb8000100 0x20>;
  56. reg-shift = <2>;
  57. interrupts = <8 IRQ_TYPE_LEVEL_HIGH>;
  58. clocks = <&clk24m>;
  59. status = "disabled";
  60. };
  61. timer0: timer@b8001000 {
  62. compatible = "nuvoton,wpcm450-timer";
  63. interrupts = <12 IRQ_TYPE_LEVEL_HIGH>;
  64. reg = <0xb8001000 0x1c>;
  65. clocks = <&clk24m>;
  66. };
  67. watchdog0: watchdog@b800101c {
  68. compatible = "nuvoton,wpcm450-wdt";
  69. interrupts = <1 IRQ_TYPE_LEVEL_HIGH>;
  70. reg = <0xb800101c 0x4>;
  71. clocks = <&clk24m>;
  72. status = "disabled";
  73. };
  74. aic: interrupt-controller@b8002000 {
  75. compatible = "nuvoton,wpcm450-aic";
  76. reg = <0xb8002000 0x1000>;
  77. interrupt-controller;
  78. #interrupt-cells = <2>;
  79. };
  80. pinctrl: pinctrl@b8003000 {
  81. compatible = "nuvoton,wpcm450-pinctrl";
  82. reg = <0xb8003000 0x1000>;
  83. #address-cells = <1>;
  84. #size-cells = <0>;
  85. gpio0: gpio@0 {
  86. reg = <0>;
  87. gpio-controller;
  88. #gpio-cells = <2>;
  89. interrupts = <2 IRQ_TYPE_LEVEL_HIGH>,
  90. <3 IRQ_TYPE_LEVEL_HIGH>,
  91. <4 IRQ_TYPE_LEVEL_HIGH>;
  92. interrupt-controller;
  93. };
  94. gpio1: gpio@1 {
  95. reg = <1>;
  96. gpio-controller;
  97. #gpio-cells = <2>;
  98. interrupts = <5 IRQ_TYPE_LEVEL_HIGH>;
  99. interrupt-controller;
  100. };
  101. gpio2: gpio@2 {
  102. reg = <2>;
  103. gpio-controller;
  104. #gpio-cells = <2>;
  105. };
  106. gpio3: gpio@3 {
  107. reg = <3>;
  108. gpio-controller;
  109. #gpio-cells = <2>;
  110. };
  111. gpio4: gpio@4 {
  112. reg = <4>;
  113. gpio-controller;
  114. #gpio-cells = <2>;
  115. };
  116. gpio5: gpio@5 {
  117. reg = <5>;
  118. gpio-controller;
  119. #gpio-cells = <2>;
  120. };
  121. gpio6: gpio@6 {
  122. reg = <6>;
  123. gpio-controller;
  124. #gpio-cells = <2>;
  125. };
  126. gpio7: gpio@7 {
  127. reg = <7>;
  128. gpio-controller;
  129. #gpio-cells = <2>;
  130. };
  131. smb3_pins: mux-smb3 {
  132. groups = "smb3";
  133. function = "smb3";
  134. };
  135. smb4_pins: mux-smb4 {
  136. groups = "smb4";
  137. function = "smb4";
  138. };
  139. smb5_pins: mux-smb5 {
  140. groups = "smb5";
  141. function = "smb5";
  142. };
  143. scs1_pins: mux-scs1 {
  144. groups = "scs1";
  145. function = "scs1";
  146. };
  147. scs2_pins: mux-scs2 {
  148. groups = "scs2";
  149. function = "scs2";
  150. };
  151. scs3_pins: mux-scs3 {
  152. groups = "scs3";
  153. function = "scs3";
  154. };
  155. smb0_pins: mux-smb0 {
  156. groups = "smb0";
  157. function = "smb0";
  158. };
  159. smb1_pins: mux-smb1 {
  160. groups = "smb1";
  161. function = "smb1";
  162. };
  163. smb2_pins: mux-smb2 {
  164. groups = "smb2";
  165. function = "smb2";
  166. };
  167. bsp_pins: mux-bsp {
  168. groups = "bsp";
  169. function = "bsp";
  170. };
  171. hsp1_pins: mux-hsp1 {
  172. groups = "hsp1";
  173. function = "hsp1";
  174. };
  175. hsp2_pins: mux-hsp2 {
  176. groups = "hsp2";
  177. function = "hsp2";
  178. };
  179. r1err_pins: mux-r1err {
  180. groups = "r1err";
  181. function = "r1err";
  182. };
  183. r1md_pins: mux-r1md {
  184. groups = "r1md";
  185. function = "r1md";
  186. };
  187. rmii2_pins: mux-rmii2 {
  188. groups = "rmii2";
  189. function = "rmii2";
  190. };
  191. r2err_pins: mux-r2err {
  192. groups = "r2err";
  193. function = "r2err";
  194. };
  195. r2md_pins: mux-r2md {
  196. groups = "r2md";
  197. function = "r2md";
  198. };
  199. kbcc_pins: mux-kbcc {
  200. groups = "kbcc";
  201. function = "kbcc";
  202. };
  203. dvo0_pins: mux-dvo0 {
  204. groups = "dvo";
  205. function = "dvo0";
  206. };
  207. dvo3_pins: mux-dvo3 {
  208. groups = "dvo";
  209. function = "dvo3";
  210. };
  211. clko_pins: mux-clko {
  212. groups = "clko";
  213. function = "clko";
  214. };
  215. smi_pins: mux-smi {
  216. groups = "smi";
  217. function = "smi";
  218. };
  219. uinc_pins: mux-uinc {
  220. groups = "uinc";
  221. function = "uinc";
  222. };
  223. gspi_pins: mux-gspi {
  224. groups = "gspi";
  225. function = "gspi";
  226. };
  227. mben_pins: mux-mben {
  228. groups = "mben";
  229. function = "mben";
  230. };
  231. xcs2_pins: mux-xcs2 {
  232. groups = "xcs2";
  233. function = "xcs2";
  234. };
  235. xcs1_pins: mux-xcs1 {
  236. groups = "xcs1";
  237. function = "xcs1";
  238. };
  239. sdio_pins: mux-sdio {
  240. groups = "sdio";
  241. function = "sdio";
  242. };
  243. sspi_pins: mux-sspi {
  244. groups = "sspi";
  245. function = "sspi";
  246. };
  247. fi0_pins: mux-fi0 {
  248. groups = "fi0";
  249. function = "fi0";
  250. };
  251. fi1_pins: mux-fi1 {
  252. groups = "fi1";
  253. function = "fi1";
  254. };
  255. fi2_pins: mux-fi2 {
  256. groups = "fi2";
  257. function = "fi2";
  258. };
  259. fi3_pins: mux-fi3 {
  260. groups = "fi3";
  261. function = "fi3";
  262. };
  263. fi4_pins: mux-fi4 {
  264. groups = "fi4";
  265. function = "fi4";
  266. };
  267. fi5_pins: mux-fi5 {
  268. groups = "fi5";
  269. function = "fi5";
  270. };
  271. fi6_pins: mux-fi6 {
  272. groups = "fi6";
  273. function = "fi6";
  274. };
  275. fi7_pins: mux-fi7 {
  276. groups = "fi7";
  277. function = "fi7";
  278. };
  279. fi8_pins: mux-fi8 {
  280. groups = "fi8";
  281. function = "fi8";
  282. };
  283. fi9_pins: mux-fi9 {
  284. groups = "fi9";
  285. function = "fi9";
  286. };
  287. fi10_pins: mux-fi10 {
  288. groups = "fi10";
  289. function = "fi10";
  290. };
  291. fi11_pins: mux-fi11 {
  292. groups = "fi11";
  293. function = "fi11";
  294. };
  295. fi12_pins: mux-fi12 {
  296. groups = "fi12";
  297. function = "fi12";
  298. };
  299. fi13_pins: mux-fi13 {
  300. groups = "fi13";
  301. function = "fi13";
  302. };
  303. fi14_pins: mux-fi14 {
  304. groups = "fi14";
  305. function = "fi14";
  306. };
  307. fi15_pins: mux-fi15 {
  308. groups = "fi15";
  309. function = "fi15";
  310. };
  311. pwm0_pins: mux-pwm0 {
  312. groups = "pwm0";
  313. function = "pwm0";
  314. };
  315. pwm1_pins: mux-pwm1 {
  316. groups = "pwm1";
  317. function = "pwm1";
  318. };
  319. pwm2_pins: mux-pwm2 {
  320. groups = "pwm2";
  321. function = "pwm2";
  322. };
  323. pwm3_pins: mux-pwm3 {
  324. groups = "pwm3";
  325. function = "pwm3";
  326. };
  327. pwm4_pins: mux-pwm4 {
  328. groups = "pwm4";
  329. function = "pwm4";
  330. };
  331. pwm5_pins: mux-pwm5 {
  332. groups = "pwm5";
  333. function = "pwm5";
  334. };
  335. pwm6_pins: mux-pwm6 {
  336. groups = "pwm6";
  337. function = "pwm6";
  338. };
  339. pwm7_pins: mux-pwm7 {
  340. groups = "pwm7";
  341. function = "pwm7";
  342. };
  343. hg0_pins: mux-hg0 {
  344. groups = "hg0";
  345. function = "hg0";
  346. };
  347. hg1_pins: mux-hg1 {
  348. groups = "hg1";
  349. function = "hg1";
  350. };
  351. hg2_pins: mux-hg2 {
  352. groups = "hg2";
  353. function = "hg2";
  354. };
  355. hg3_pins: mux-hg3 {
  356. groups = "hg3";
  357. function = "hg3";
  358. };
  359. hg4_pins: mux-hg4 {
  360. groups = "hg4";
  361. function = "hg4";
  362. };
  363. hg5_pins: mux-hg5 {
  364. groups = "hg5";
  365. function = "hg5";
  366. };
  367. hg6_pins: mux-hg6 {
  368. groups = "hg6";
  369. function = "hg6";
  370. };
  371. hg7_pins: mux-hg7 {
  372. groups = "hg7";
  373. function = "hg7";
  374. };
  375. };
  376. };
  377. };