nuvoton-npcm750.dtsi 1.3 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. // Copyright (c) 2018 Nuvoton Technology [email protected]
  3. // Copyright 2018 Google, Inc.
  4. #include "nuvoton-common-npcm7xx.dtsi"
  5. / {
  6. #address-cells = <1>;
  7. #size-cells = <1>;
  8. interrupt-parent = <&gic>;
  9. cpus {
  10. #address-cells = <1>;
  11. #size-cells = <0>;
  12. enable-method = "nuvoton,npcm750-smp";
  13. cpu@0 {
  14. device_type = "cpu";
  15. compatible = "arm,cortex-a9";
  16. clocks = <&clk NPCM7XX_CLK_CPU>;
  17. clock-names = "clk_cpu";
  18. reg = <0>;
  19. next-level-cache = <&l2>;
  20. };
  21. cpu@1 {
  22. device_type = "cpu";
  23. compatible = "arm,cortex-a9";
  24. clocks = <&clk NPCM7XX_CLK_CPU>;
  25. clock-names = "clk_cpu";
  26. reg = <1>;
  27. next-level-cache = <&l2>;
  28. };
  29. };
  30. soc {
  31. timer@3fe600 {
  32. compatible = "arm,cortex-a9-twd-timer";
  33. reg = <0x3fe600 0x20>;
  34. interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) |
  35. IRQ_TYPE_LEVEL_HIGH)>;
  36. clocks = <&clk NPCM7XX_CLK_AHB>;
  37. };
  38. };
  39. ahb {
  40. gmac1: eth@f0804000 {
  41. device_type = "network";
  42. compatible = "snps,dwmac";
  43. reg = <0xf0804000 0x2000>;
  44. interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
  45. interrupt-names = "macirq";
  46. ethernet = <1>;
  47. clocks = <&clk_rg2refck>, <&clk NPCM7XX_CLK_AHB>;
  48. clock-names = "stmmaceth", "clk_gmac";
  49. pinctrl-names = "default";
  50. pinctrl-0 = <&rg2_pins
  51. &rg2mdio_pins>;
  52. status = "disabled";
  53. };
  54. };
  55. };