nuvoton-npcm750-runbmc-olympus.dts 17 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. // Copyright (c) 2019 Nuvoton Technology <[email protected]>
  3. // Copyright (c) 2019 Quanta Computer Inc. <[email protected]>
  4. /dts-v1/;
  5. #include "nuvoton-npcm750.dtsi"
  6. #include "nuvoton-npcm750-runbmc-olympus-pincfg.dtsi"
  7. #include <dt-bindings/i2c/i2c.h>
  8. #include <dt-bindings/gpio/gpio.h>
  9. / {
  10. model = "Nuvoton npcm750 RunBMC Olympus";
  11. compatible = "nuvoton,npcm750";
  12. aliases {
  13. ethernet1 = &gmac0;
  14. serial0 = &serial0;
  15. serial1 = &serial1;
  16. serial2 = &serial2;
  17. serial3 = &serial3;
  18. i2c0 = &i2c0;
  19. i2c1 = &i2c1;
  20. i2c2 = &i2c2;
  21. i2c3 = &i2c3;
  22. i2c4 = &i2c4;
  23. i2c5 = &i2c5;
  24. i2c6 = &i2c6;
  25. i2c7 = &i2c7;
  26. i2c8 = &i2c8;
  27. i2c9 = &i2c9;
  28. i2c10 = &i2c10;
  29. i2c11 = &i2c11;
  30. i2c12 = &i2c12;
  31. i2c13 = &i2c13;
  32. spi0 = &spi0;
  33. spi1 = &spi1;
  34. fiu0 = &fiu0;
  35. fiu1 = &fiu3;
  36. };
  37. chosen {
  38. stdout-path = &serial3;
  39. };
  40. memory {
  41. reg = <0 0x40000000>;
  42. };
  43. iio-hwmon {
  44. compatible = "iio-hwmon";
  45. io-channels = <&adc 0>, <&adc 1>, <&adc 2>, <&adc 3>,
  46. <&adc 4>, <&adc 5>, <&adc 6>, <&adc 7>;
  47. };
  48. leds {
  49. compatible = "gpio-leds";
  50. heartbeat {
  51. label = "heartbeat";
  52. gpios = <&gpio3 14 1>;
  53. };
  54. identify {
  55. label = "identify";
  56. gpios = <&gpio3 15 1>;
  57. };
  58. };
  59. jtag {
  60. compatible = "nuvoton,npcm750-jtag";
  61. enable_pspi_jtag = <1>;
  62. pspi-index = <2>;
  63. tck {
  64. label = "tck";
  65. gpios = <&gpio0 19 0>; /* gpio19 */
  66. regbase = <0xf0010000 0x1000>;
  67. };
  68. tdi {
  69. label = "tdi";
  70. gpios = <&gpio0 18 0>; /* gpio18 */
  71. regbase = <0xf0010000 0x1000>;
  72. };
  73. tdo {
  74. label = "tdo";
  75. gpios = <&gpio0 17 0>; /* gpio17 */
  76. regbase = <0xf0010000 0x1000>;
  77. };
  78. tms {
  79. label = "tms";
  80. gpios = <&gpio0 16 0>; /* gpio16 */
  81. regbase = <0xf0010000 0x1000>;
  82. };
  83. };
  84. };
  85. &fiu0 {
  86. pinctrl-names = "default";
  87. pinctrl-0 = <&spi0cs1_pins>;
  88. status = "okay";
  89. flash@0 {
  90. compatible = "jedec,spi-nor";
  91. #address-cells = <1>;
  92. #size-cells = <1>;
  93. reg = <0>;
  94. spi-rx-bus-width = <2>;
  95. partitions {
  96. compatible = "fixed-partitions";
  97. #address-cells = <1>;
  98. #size-cells = <1>;
  99. bmc@0{
  100. label = "bmc";
  101. reg = <0x000000 0x2000000>;
  102. };
  103. u-boot@0 {
  104. label = "u-boot";
  105. reg = <0x0000000 0x80000>;
  106. read-only;
  107. };
  108. u-boot-env@100000{
  109. label = "u-boot-env";
  110. reg = <0x00100000 0x40000>;
  111. };
  112. kernel@200000 {
  113. label = "kernel";
  114. reg = <0x0200000 0x600000>;
  115. };
  116. rofs@800000 {
  117. label = "rofs";
  118. reg = <0x800000 0x1500000>;
  119. };
  120. rwfs@1d00000 {
  121. label = "rwfs";
  122. reg = <0x1d00000 0x300000>;
  123. };
  124. };
  125. };
  126. flash@1 {
  127. compatible = "jedec,spi-nor";
  128. #address-cells = <1>;
  129. #size-cells = <1>;
  130. reg = <1>;
  131. npcm,fiu-rx-bus-width = <2>;
  132. partitions {
  133. compatible = "fixed-partitions";
  134. #address-cells = <1>;
  135. #size-cells = <1>;
  136. spare1@0 {
  137. label = "spi0-cs1-spare1";
  138. reg = <0x0 0x800000>;
  139. };
  140. spare2@800000 {
  141. label = "spi0-cs1-spare2";
  142. reg = <0x800000 0x0>;
  143. };
  144. };
  145. };
  146. };
  147. &fiu3 {
  148. pinctrl-0 = <&spi3_pins>;
  149. status = "okay";
  150. flash@0 {
  151. compatible = "jedec,spi-nor";
  152. #address-cells = <1>;
  153. #size-cells = <1>;
  154. reg = <0>;
  155. spi-rx-bus-width = <2>;
  156. partitions {
  157. compatible = "fixed-partitions";
  158. #address-cells = <1>;
  159. #size-cells = <1>;
  160. system1@0 {
  161. label = "spi3-system1";
  162. reg = <0x0 0x800000>;
  163. };
  164. system2@800000 {
  165. label = "spi3-system2";
  166. reg = <0x800000 0x0>;
  167. };
  168. };
  169. };
  170. };
  171. &gcr {
  172. mux-controller {
  173. compatible = "mmio-mux";
  174. #mux-control-cells = <1>;
  175. mux-reg-masks = <0x38 0x07>;
  176. idle-states = <6>;
  177. };
  178. };
  179. &gmac0 {
  180. phy-mode = "rgmii-id";
  181. snps,eee-force-disable;
  182. status = "okay";
  183. };
  184. &i2c1 {
  185. status = "okay";
  186. i2c-switch@70 {
  187. compatible = "nxp,pca9548";
  188. #address-cells = <1>;
  189. #size-cells = <0>;
  190. reg = <0x70>;
  191. i2c-mux-idle-disconnect;
  192. i2c_slot1a: i2c-bus@0 {
  193. #address-cells = <1>;
  194. #size-cells = <0>;
  195. reg = <0>;
  196. };
  197. i2c_slot1b: i2c-bus@1 {
  198. #address-cells = <1>;
  199. #size-cells = <0>;
  200. reg = <1>;
  201. };
  202. i2c_slot2a: i2c-bus@2 {
  203. #address-cells = <1>;
  204. #size-cells = <0>;
  205. reg = <2>;
  206. };
  207. i2c_slot2b: i2c-bus@3 {
  208. #address-cells = <1>;
  209. #size-cells = <0>;
  210. reg = <3>;
  211. };
  212. i2c_slot3: i2c-bus@4 {
  213. #address-cells = <1>;
  214. #size-cells = <0>;
  215. reg = <4>;
  216. };
  217. i2c_slot4: i2c-bus@5 {
  218. #address-cells = <1>;
  219. #size-cells = <0>;
  220. reg = <5>;
  221. };
  222. i2c_slot5: i2c-bus@6 {
  223. #address-cells = <1>;
  224. #size-cells = <0>;
  225. reg = <6>;
  226. };
  227. };
  228. i2c-switch@71 {
  229. compatible = "nxp,pca9546";
  230. reg = <0x71>;
  231. #address-cells = <1>;
  232. #size-cells = <0>;
  233. i2c-mux-idle-disconnect;
  234. i2c_m2_s1: i2c-bus@0 {
  235. #address-cells = <1>;
  236. #size-cells = <0>;
  237. reg = <0>;
  238. };
  239. i2c_m2_s2: i2c-bus@1 {
  240. #address-cells = <1>;
  241. #size-cells = <0>;
  242. reg = <1>;
  243. };
  244. i2c_m2_s3: i2c-bus@2 {
  245. #address-cells = <1>;
  246. #size-cells = <0>;
  247. reg = <2>;
  248. };
  249. i2c_m2_s4: i2c-bus@3 {
  250. #address-cells = <1>;
  251. #size-cells = <0>;
  252. reg = <3>;
  253. };
  254. };
  255. };
  256. &i2c2 {
  257. status = "okay";
  258. tmp421@4c {
  259. compatible = "ti,tmp421";
  260. reg = <0x4c>;
  261. };
  262. power-supply@58 {
  263. compatible = "delta,dps800";
  264. reg = <0x58>;
  265. };
  266. };
  267. &i2c3 {
  268. status = "okay";
  269. };
  270. &i2c4 {
  271. status = "okay";
  272. eeprom@54 {
  273. compatible = "atmel,24c64";
  274. reg = <0x54>;
  275. };
  276. };
  277. &i2c5 {
  278. status = "okay";
  279. i2c-slave-mqueue@10 {
  280. compatible = "i2c-slave-mqueue";
  281. reg = <(I2C_OWN_SLAVE_ADDRESS | 0x10)>;
  282. };
  283. };
  284. &i2c6 {
  285. status = "okay";
  286. ina219@40 {
  287. compatible = "ti,ina219";
  288. reg = <0x40>;
  289. };
  290. ina219@41 {
  291. compatible = "ti,ina219";
  292. reg = <0x41>;
  293. };
  294. ina219@44 {
  295. compatible = "ti,ina219";
  296. reg = <0x44>;
  297. };
  298. ina219@45 {
  299. compatible = "ti,ina219";
  300. reg = <0x45>;
  301. };
  302. tps53679@60 {
  303. compatible = "ti,tps53679";
  304. reg = <0x60>;
  305. };
  306. tps53659@62 {
  307. compatible = "ti,tps53659";
  308. reg = <0x62>;
  309. };
  310. tps53659@64 {
  311. compatible = "ti,tps53659";
  312. reg = <0x64>;
  313. };
  314. tps53622@67 {
  315. compatible = "ti,tps53622";
  316. reg = <0x67>;
  317. };
  318. tps53622@69 {
  319. compatible = "ti,tps53622";
  320. reg = <0x69>;
  321. };
  322. tps53679@70 {
  323. compatible = "ti,tps53679";
  324. reg = <0x70>;
  325. };
  326. tps53659@72 {
  327. compatible = "ti,tps53659";
  328. reg = <0x72>;
  329. };
  330. tps53659@74 {
  331. compatible = "ti,tps53659";
  332. reg = <0x74>;
  333. };
  334. tps53622@77 {
  335. compatible = "ti,tps53622";
  336. reg = <0x77>;
  337. };
  338. };
  339. &i2c7 {
  340. status = "okay";
  341. tmp421@4c {
  342. compatible = "ti,tmp421";
  343. reg = <0x4c>;
  344. };
  345. };
  346. &i2c8 {
  347. status = "okay";
  348. adm1278@11 {
  349. compatible = "adm1278";
  350. reg = <0x11>;
  351. Rsense = <500>;
  352. };
  353. };
  354. &i2c9 {
  355. status = "okay";
  356. };
  357. &i2c10 {
  358. status = "okay";
  359. gpio: pca9555@27 {
  360. compatible = "nxp,pca9555";
  361. reg = <0x27>;
  362. gpio-controller;
  363. #gpio-cells = <2>;
  364. };
  365. };
  366. &i2c11 {
  367. status = "okay";
  368. pca9539_g1a: pca9539-g1a@74 {
  369. compatible = "nxp,pca9539";
  370. reg = <0x74>;
  371. gpio-controller;
  372. #gpio-cells = <2>;
  373. reset-gpios = <&gpio7 4 GPIO_ACTIVE_LOW>;
  374. G1A_P0_0 {
  375. gpio-hog;
  376. gpios = <0 0>;
  377. output-high;
  378. line-name = "TPM_BMC_ALERT_N";
  379. };
  380. G1A_P0_1 {
  381. gpio-hog;
  382. gpios = <1 0>;
  383. input;
  384. line-name = "FM_BIOS_TOP_SWAP";
  385. };
  386. G1A_P0_2 {
  387. gpio-hog;
  388. gpios = <2 0>;
  389. input;
  390. line-name = "FM_BIOS_PREFRB2_GOOD";
  391. };
  392. G1A_P0_3 {
  393. gpio-hog;
  394. gpios = <3 0>;
  395. input;
  396. line-name = "BMC_SATAXPCIE_0TO3_SEL";
  397. };
  398. G1A_P0_4 {
  399. gpio-hog;
  400. gpios = <4 0>;
  401. input;
  402. line-name = "BMC_SATAXPCIE_4TO7_SEL";
  403. };
  404. G1A_P0_5 {
  405. gpio-hog;
  406. gpios = <5 0>;
  407. output-low;
  408. line-name = "FM_UV_ADR_TRIGGER_EN_N";
  409. };
  410. G1A_P0_6 {
  411. gpio-hog;
  412. gpios = <6 0>;
  413. input;
  414. line-name = "RM_THROTTLE_EN_N";
  415. };
  416. G1A_P1_0 {
  417. gpio-hog;
  418. gpios = <8 0>;
  419. input;
  420. line-name = "FM_BMC_TPM_PRES_N";
  421. };
  422. G1A_P1_1 {
  423. gpio-hog;
  424. gpios = <9 0>;
  425. input;
  426. line-name = "FM_CPU0_SKTOCC_LVT3_N";
  427. };
  428. G1A_P1_2 {
  429. gpio-hog;
  430. gpios = <10 0>;
  431. input;
  432. line-name = "FM_CPU1_SKTOCC_LVT3_N";
  433. };
  434. G1A_P1_3 {
  435. gpio-hog;
  436. gpios = <11 0>;
  437. input;
  438. line-name = "PSU1_ALERT_N";
  439. };
  440. G1A_P1_4 {
  441. gpio-hog;
  442. gpios = <12 0>;
  443. input;
  444. line-name = "PSU2_ALERT_N";
  445. };
  446. G1A_P1_5 {
  447. gpio-hog;
  448. gpios = <13 0>;
  449. input;
  450. line-name = "H_CPU0_FAST_WAKE_LVT3_N";
  451. };
  452. G1A_P1_6 {
  453. gpio-hog;
  454. gpios = <14 0>;
  455. output-high;
  456. line-name = "I2C_MUX1_RESET_N";
  457. };
  458. G1A_P1_7 {
  459. gpio-hog;
  460. gpios = <15 0>;
  461. input;
  462. line-name = "FM_CPU_CATERR_LVT3_N";
  463. };
  464. };
  465. pca9539_g1b: pca9539-g1b@75 {
  466. compatible = "nxp,pca9539";
  467. reg = <0x75>;
  468. gpio-controller;
  469. #gpio-cells = <2>;
  470. G1B_P0_0 {
  471. gpio-hog;
  472. gpios = <0 0>;
  473. input;
  474. line-name = "PVDDQ_ABC_PINALERT_N";
  475. };
  476. G1B_P0_1 {
  477. gpio-hog;
  478. gpios = <1 0>;
  479. input;
  480. line-name = "PVDDQ_DEF_PINALERT_N";
  481. };
  482. G1B_P0_2 {
  483. gpio-hog;
  484. gpios = <2 0>;
  485. input;
  486. line-name = "PVDDQ_GHJ_PINALERT_N";
  487. };
  488. G1B_P0_3 {
  489. gpio-hog;
  490. gpios = <3 0>;
  491. input;
  492. line-name = "PVDDQ_KLM_PINALERT_N";
  493. };
  494. G1B_P0_5 {
  495. gpio-hog;
  496. gpios = <5 0>;
  497. input;
  498. line-name = "FM_BOARD_REV_ID0";
  499. };
  500. G1B_P0_6 {
  501. gpio-hog;
  502. gpios = <6 0>;
  503. input;
  504. line-name = "FM_BOARD_REV_ID1";
  505. };
  506. G1B_P0_7 {
  507. gpio-hog;
  508. gpios = <7 0>;
  509. input;
  510. line-name = "FM_BOARD_REV_ID2";
  511. };
  512. G1B_P1_0 {
  513. gpio-hog;
  514. gpios = <8 0>;
  515. input;
  516. line-name = "FM_OC_DETECT_EN_N";
  517. };
  518. G1B_P1_1 {
  519. gpio-hog;
  520. gpios = <9 0>;
  521. input;
  522. line-name = "FM_FLASH_DESC_OVERRIDE";
  523. };
  524. G1B_P1_2 {
  525. gpio-hog;
  526. gpios = <10 0>;
  527. output-low;
  528. line-name = "FP_PWR_ID_LED_N";
  529. };
  530. G1B_P1_3 {
  531. gpio-hog;
  532. gpios = <11 0>;
  533. output-low;
  534. line-name = "BMC_LED_PWR_GRN";
  535. };
  536. G1B_P1_4 {
  537. gpio-hog;
  538. gpios = <12 0>;
  539. output-low;
  540. line-name = "BMC_LED_PWR_AMBER";
  541. };
  542. G1B_P1_5 {
  543. gpio-hog;
  544. gpios = <13 0>;
  545. output-high;
  546. line-name = "FM_BMC_FAULT_LED_N";
  547. };
  548. G1B_P1_6 {
  549. gpio-hog;
  550. gpios = <14 0>;
  551. output-high;
  552. line-name = "FM_CPLD_BMC_PWRDN_N";
  553. };
  554. G1B_P1_7 {
  555. gpio-hog;
  556. gpios = <15 0>;
  557. output-high;
  558. line-name = "BMC_LED_CATERR_N";
  559. };
  560. };
  561. };
  562. &i2c12 {
  563. status = "okay";
  564. pca9539_g2a: pca9539-g2a@74 {
  565. compatible = "nxp,pca9539";
  566. reg = <0x74>;
  567. gpio-controller;
  568. #gpio-cells = <2>;
  569. reset-gpios = <&gpio5 28 GPIO_ACTIVE_LOW>;
  570. G2A_P0_0 {
  571. gpio-hog;
  572. gpios = <0 0>;
  573. output-high;
  574. line-name = "BMC_PON_RST_REQ_N";
  575. };
  576. G2A_P0_1 {
  577. gpio-hog;
  578. gpios = <1 0>;
  579. output-high;
  580. line-name = "BMC_RST_IND_REQ_N";
  581. };
  582. G2A_P0_2 {
  583. gpio-hog;
  584. gpios = <2 0>;
  585. input;
  586. line-name = "RST_BMC_RTCRST";
  587. };
  588. G2A_P0_3 {
  589. gpio-hog;
  590. gpios = <3 0>;
  591. output-high;
  592. line-name = "FM_BMC_PWRBTN_OUT_N";
  593. };
  594. G2A_P0_4 {
  595. gpio-hog;
  596. gpios = <4 0>;
  597. output-high;
  598. line-name = "RST_BMC_SYSRST_BTN_OUT_N";
  599. };
  600. G2A_P0_5 {
  601. gpio-hog;
  602. gpios = <5 0>;
  603. output-high;
  604. line-name = "FM_BATTERY_SENSE_EN_N";
  605. };
  606. G2A_P0_6 {
  607. gpio-hog;
  608. gpios = <6 0>;
  609. output-high;
  610. line-name = "FM_BMC_READY_N";
  611. };
  612. G2A_P0_7 {
  613. gpio-hog;
  614. gpios = <7 0>;
  615. input;
  616. line-name = "IRQ_BMC_PCH_SMI_LPC_N";
  617. };
  618. G2A_P1_0 {
  619. gpio-hog;
  620. gpios = <8 0>;
  621. input;
  622. line-name = "FM_SLOT4_CFG0";
  623. };
  624. G2A_P1_1 {
  625. gpio-hog;
  626. gpios = <9 0>;
  627. input;
  628. line-name = "FM_SLOT4_CFG1";
  629. };
  630. G2A_P1_2 {
  631. gpio-hog;
  632. gpios = <10 0>;
  633. input;
  634. line-name = "FM_NVDIMM_EVENT_N";
  635. };
  636. G2A_P1_3 {
  637. gpio-hog;
  638. gpios = <11 0>;
  639. input;
  640. line-name = "PSU1_BLADE_EN_N";
  641. };
  642. G2A_P1_4 {
  643. gpio-hog;
  644. gpios = <12 0>;
  645. input;
  646. line-name = "BMC_PCH_FNM";
  647. };
  648. G2A_P1_5 {
  649. gpio-hog;
  650. gpios = <13 0>;
  651. input;
  652. line-name = "FM_SOL_UART_CH_SEL";
  653. };
  654. G2A_P1_6 {
  655. gpio-hog;
  656. gpios = <14 0>;
  657. input;
  658. line-name = "FM_BIOS_POST_CMPLT_N";
  659. };
  660. };
  661. pca9539_g2b: pca9539-g2b@75 {
  662. compatible = "nxp,pca9539";
  663. reg = <0x75>;
  664. gpio-controller;
  665. #gpio-cells = <2>;
  666. G2B_P0_0 {
  667. gpio-hog;
  668. gpios = <0 0>;
  669. input;
  670. line-name = "FM_CPU_MSMI_LVT3_N";
  671. };
  672. G2B_P0_1 {
  673. gpio-hog;
  674. gpios = <1 0>;
  675. input;
  676. line-name = "FM_BIOS_MRC_DEBUG_MSG_DIS";
  677. };
  678. G2B_P0_2 {
  679. gpio-hog;
  680. gpios = <2 0>;
  681. input;
  682. line-name = "FM_CPU1_DISABLE_BMC_N";
  683. };
  684. G2B_P0_3 {
  685. gpio-hog;
  686. gpios = <3 0>;
  687. output-low;
  688. line-name = "BMC_JTAG_SELECT";
  689. };
  690. G2B_P0_4 {
  691. gpio-hog;
  692. gpios = <4 0>;
  693. output-high;
  694. line-name = "PECI_MUX_SELECT";
  695. };
  696. G2B_P0_5 {
  697. gpio-hog;
  698. gpios = <5 0>;
  699. output-high;
  700. line-name = "I2C_MUX2_RESET_N";
  701. };
  702. G2B_P0_6 {
  703. gpio-hog;
  704. gpios = <6 0>;
  705. input;
  706. line-name = "FM_BMC_CPLD_PSU2_ON";
  707. };
  708. G2B_P0_7 {
  709. gpio-hog;
  710. gpios = <7 0>;
  711. output-high;
  712. line-name = "PSU2_ALERT_EN_N";
  713. };
  714. G2B_P1_0 {
  715. gpio-hog;
  716. gpios = <8 0>;
  717. output-high;
  718. line-name = "FM_CPU_BMC_INIT";
  719. };
  720. G2B_P1_1 {
  721. gpio-hog;
  722. gpios = <9 0>;
  723. output-high;
  724. line-name = "IRQ_BMC_PCH_SCI_LPC_N";
  725. };
  726. G2B_P1_2 {
  727. gpio-hog;
  728. gpios = <10 0>;
  729. output-low;
  730. line-name = "PMB_ALERT_EN_N";
  731. };
  732. G2B_P1_3 {
  733. gpio-hog;
  734. gpios = <11 0>;
  735. output-high;
  736. line-name = "FM_FAST_PROCHOT_EN_N";
  737. };
  738. G2B_P1_4 {
  739. gpio-hog;
  740. gpios = <12 0>;
  741. output-high;
  742. line-name = "BMC_NVDIMM_PRSNT_N";
  743. };
  744. G2B_P1_5 {
  745. gpio-hog;
  746. gpios = <13 0>;
  747. output-low;
  748. line-name = "FM_BACKUP_BIOS_SEL_H_BMC";
  749. };
  750. G2B_P1_6 {
  751. gpio-hog;
  752. gpios = <14 0>;
  753. output-high;
  754. line-name = "FM_PWRBRK_N";
  755. };
  756. };
  757. };
  758. &i2c13 {
  759. status = "okay";
  760. tmp75@4a {
  761. compatible = "ti,tmp75";
  762. reg = <0x4a>;
  763. status = "okay";
  764. };
  765. m24128_fru@51 {
  766. compatible = "atmel,24c128";
  767. reg = <0x51>;
  768. pagesize = <64>;
  769. status = "okay";
  770. };
  771. };
  772. &pwm_fan {
  773. pinctrl-names = "default";
  774. pinctrl-0 = < &pwm0_pins &pwm1_pins
  775. &fanin0_pins &fanin1_pins
  776. &fanin2_pins &fanin3_pins
  777. &fanin4_pins &fanin5_pins
  778. &fanin6_pins &fanin7_pins
  779. &fanin8_pins &fanin9_pins
  780. &fanin10_pins &fanin11_pins>;
  781. status = "okay";
  782. fan@0 {
  783. reg = <0x00>;
  784. fan-tach-ch = /bits/ 8 <0x00 0x01>;
  785. cooling-levels = <127 255>;
  786. };
  787. fan@1 {
  788. reg = <0x01>;
  789. fan-tach-ch = /bits/ 8 <0x02 0x03>;
  790. cooling-levels = /bits/ 8 <127 255>;
  791. };
  792. fan@2 {
  793. reg = <0x02>;
  794. fan-tach-ch = /bits/ 8 <0x04 0x05>;
  795. cooling-levels = /bits/ 8 <127 255>;
  796. };
  797. fan@3 {
  798. reg = <0x03>;
  799. fan-tach-ch = /bits/ 8 <0x06 0x07>;
  800. cooling-levels = /bits/ 8 <127 255>;
  801. };
  802. fan@4 {
  803. reg = <0x04>;
  804. fan-tach-ch = /bits/ 8 <0x08 0x09>;
  805. cooling-levels = /bits/ 8 <127 255>;
  806. };
  807. fan@5 {
  808. reg = <0x05>;
  809. fan-tach-ch = /bits/ 8 <0x0A 0x0B>;
  810. cooling-levels = /bits/ 8 <127 255>;
  811. };
  812. fan@6 {
  813. reg = <0x06>;
  814. fan-tach-ch = /bits/ 8 <0x0C 0x0D>;
  815. cooling-levels = /bits/ 8 <127 255>;
  816. };
  817. fan@7 {
  818. reg = <0x07>;
  819. fan-tach-ch = /bits/ 8 <0x0E 0x0F>;
  820. cooling-levels = /bits/ 8 <127 255>;
  821. };
  822. };
  823. &ehci1 {
  824. status = "okay";
  825. };
  826. &watchdog1 {
  827. status = "okay";
  828. };
  829. &rng {
  830. status = "okay";
  831. };
  832. &serial0 {
  833. status = "okay";
  834. };
  835. &serial1 {
  836. status = "okay";
  837. };
  838. &serial2 {
  839. status = "okay";
  840. };
  841. &serial3 {
  842. status = "okay";
  843. };
  844. &adc {
  845. #io-channel-cells = <1>;
  846. status = "okay";
  847. };
  848. &kcs1 {
  849. status = "okay";
  850. };
  851. &kcs2 {
  852. status = "okay";
  853. };
  854. &kcs3 {
  855. status = "okay";
  856. };
  857. &spi0 {
  858. cs-gpios = <&gpio6 11 GPIO_ACTIVE_LOW>;
  859. status = "okay";
  860. };
  861. &spi1 {
  862. status = "okay";
  863. };
  864. &pinctrl {
  865. pinctrl-names = "default";
  866. pinctrl-0 = <
  867. /******* RunBMC inside Module pins *******/
  868. &gpio0ol_pins
  869. &gpio1ol_pins
  870. &gpio2ol_pins
  871. &gpio3ol_pins
  872. &gpio8o_pins
  873. &gpio9ol_pins
  874. &gpio12ol_pins
  875. &gpio13ol_pins
  876. &gpio14ol_pins
  877. &gpio15ol_pins
  878. &gpio37o_pins
  879. &gpio38_pins
  880. &gpio39_pins
  881. &gpio94ol_pins
  882. &gpio108ol_pins
  883. &gpio109ol_pins
  884. &gpio111ol_pins
  885. &gpio112ol_pins
  886. &gpio113ol_pins
  887. &gpio208_pins
  888. &gpio209ol_pins
  889. &gpio210ol_pins
  890. &gpio211ol_pins
  891. &gpio212ol_pins
  892. &gpio213ol_pins
  893. &gpio214ol_pins
  894. &gpio215ol_pins
  895. &gpio216ol_pins
  896. &gpio217ol_pins
  897. /******* RunBMC outside Connector pins *******/
  898. &gpio5_pins
  899. &gpio6_pins
  900. &gpio7_pins
  901. &gpio10_pins
  902. &gpio11_pins
  903. &gpio20_pins
  904. &gpio21_pins
  905. &gpio22o_pins
  906. &gpio23_pins
  907. &gpio24_pins
  908. &gpio25_pins
  909. &gpio30_pins
  910. &gpio31_pins
  911. &gpio40o_pins
  912. &gpio59_pins
  913. &gpio76_pins
  914. &gpio77_pins
  915. &gpio78o_pins
  916. &gpio79_pins
  917. &gpio82_pins
  918. &gpio83_pins
  919. &gpio84_pins
  920. &gpio85o_pins
  921. &gpio86ol_pins
  922. &gpio87_pins
  923. &gpio88_pins
  924. &gpio89_pins
  925. &gpio90_pins
  926. &gpio93_pins
  927. &gpio114o_pins
  928. &gpio115_pins
  929. &gpio120_pins
  930. &gpio121_pins
  931. &gpio122_pins
  932. &gpio123_pins
  933. &gpio124_pins
  934. &gpio125_pins
  935. &gpio126_pins
  936. &gpio127o_pins
  937. &gpio136_pins
  938. &gpio137_pins
  939. &gpio138_pins
  940. &gpio139_pins
  941. &gpio140_pins
  942. &gpio141_pins
  943. &gpio142_pins
  944. &gpio143_pins
  945. &gpio144_pins
  946. &gpio146_pins
  947. &gpio145_pins
  948. &gpio147_pins
  949. &gpio153o_pins
  950. &gpio155_pins
  951. &gpio160o_pins
  952. &gpio169o_pins
  953. &gpio188o_pins
  954. &gpio189_pins
  955. &gpio196_pins
  956. &gpio197_pins
  957. &gpio198o_pins
  958. &gpio199o_pins
  959. &gpio200_pins
  960. &gpio202_pins
  961. &gpio203o_pins
  962. &gpio224_pins
  963. &gpio225ol_pins
  964. &gpio226ol_pins
  965. &gpio227ol_pins
  966. &gpio228o_pins
  967. &gpio229o_pins
  968. &gpio230_pins
  969. &gpio231o_pins
  970. &ddc_pins
  971. &wdog1_pins
  972. &wdog2_pins
  973. >;
  974. };