lpc3250-phy3250.dts 4.1 KB

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  1. // SPDX-License-Identifier: GPL-2.0-or-later
  2. /*
  3. * PHYTEC phyCORE-LPC3250 board
  4. *
  5. * Copyright (C) 2015-2019 Vladimir Zapolskiy <[email protected]>
  6. * Copyright 2012 Roland Stigge <[email protected]>
  7. */
  8. /dts-v1/;
  9. #include "lpc32xx.dtsi"
  10. / {
  11. model = "PHYTEC phyCORE-LPC3250 board based on NXP LPC3250";
  12. compatible = "phytec,phy3250", "nxp,lpc3250";
  13. memory@80000000 {
  14. device_type = "memory";
  15. reg = <0x80000000 0x4000000>;
  16. };
  17. leds {
  18. compatible = "gpio-leds";
  19. led0 { /* red */
  20. gpios = <&gpio 5 1 0>; /* GPO_P3 1, GPIO 80, active high */
  21. default-state = "off";
  22. };
  23. led1 { /* green */
  24. gpios = <&gpio 5 14 0>; /* GPO_P3 14, GPIO 93, active high */
  25. linux,default-trigger = "heartbeat";
  26. };
  27. };
  28. panel: panel {
  29. compatible = "sharp,lq035q7db03";
  30. power-supply = <&reg_lcd>;
  31. port {
  32. panel_input: endpoint {
  33. remote-endpoint = <&cldc_output>;
  34. };
  35. };
  36. };
  37. reg_backlight: regulator-backlight {
  38. compatible = "regulator-fixed";
  39. regulator-name = "backlight";
  40. regulator-min-microvolt = <1800000>;
  41. regulator-max-microvolt = <1800000>;
  42. gpio = <&gpio 5 4 0>;
  43. enable-active-high;
  44. regulator-boot-on;
  45. };
  46. reg_lcd: regulator-lcd {
  47. compatible = "regulator-fixed";
  48. regulator-name = "lcd";
  49. regulator-min-microvolt = <1800000>;
  50. regulator-max-microvolt = <1800000>;
  51. gpio = <&gpio 5 0 0>;
  52. enable-active-high;
  53. regulator-boot-on;
  54. };
  55. reg_sd: regulator-sd {
  56. compatible = "regulator-fixed";
  57. regulator-name = "sd";
  58. regulator-min-microvolt = <3300000>;
  59. regulator-max-microvolt = <3300000>;
  60. gpio = <&gpio 5 5 0>;
  61. enable-active-high;
  62. regulator-boot-on;
  63. };
  64. };
  65. &clcd {
  66. max-memory-bandwidth = <18710000>;
  67. status = "okay";
  68. port {
  69. cldc_output: endpoint {
  70. remote-endpoint = <&panel_input>;
  71. arm,pl11x,tft-r0g0b0-pads = <0 8 16>;
  72. };
  73. };
  74. };
  75. &i2c1 {
  76. clock-frequency = <100000>;
  77. uda1380: uda1380@18 {
  78. compatible = "nxp,uda1380";
  79. reg = <0x18>;
  80. power-gpio = <&gpio 3 10 0>;
  81. reset-gpio = <&gpio 3 2 0>;
  82. dac-clk = "wspll";
  83. };
  84. pcf8563: rtc@51 {
  85. compatible = "nxp,pcf8563";
  86. reg = <0x51>;
  87. };
  88. };
  89. &i2c2 {
  90. clock-frequency = <100000>;
  91. };
  92. &i2cusb {
  93. clock-frequency = <100000>;
  94. isp1301: usb-transceiver@2c {
  95. compatible = "nxp,isp1301";
  96. reg = <0x2c>;
  97. };
  98. };
  99. &key {
  100. keypad,num-rows = <1>;
  101. keypad,num-columns = <1>;
  102. nxp,debounce-delay-ms = <3>;
  103. nxp,scan-delay-ms = <34>;
  104. linux,keymap = <0x00000002>;
  105. status = "okay";
  106. };
  107. &mac {
  108. phy-mode = "rmii";
  109. use-iram;
  110. status = "okay";
  111. };
  112. /* Here, choose exactly one from: ohci, usbd */
  113. &ohci /* &usbd */ {
  114. transceiver = <&isp1301>;
  115. status = "okay";
  116. };
  117. &sd {
  118. wp-gpios = <&gpio 3 0 0>;
  119. cd-gpios = <&gpio 3 1 0>;
  120. cd-inverted;
  121. bus-width = <4>;
  122. vmmc-supply = <&reg_sd>;
  123. status = "okay";
  124. };
  125. /* 64MB Flash via SLC NAND controller */
  126. &slc {
  127. status = "okay";
  128. nxp,wdr-clks = <14>;
  129. nxp,wwidth = <40000000>;
  130. nxp,whold = <100000000>;
  131. nxp,wsetup = <100000000>;
  132. nxp,rdr-clks = <14>;
  133. nxp,rwidth = <40000000>;
  134. nxp,rhold = <66666666>;
  135. nxp,rsetup = <100000000>;
  136. nand-on-flash-bbt;
  137. gpios = <&gpio 5 19 1>; /* GPO_P3 19, active low */
  138. partitions {
  139. compatible = "fixed-partitions";
  140. #address-cells = <1>;
  141. #size-cells = <1>;
  142. mtd0@0 {
  143. label = "phy3250-boot";
  144. reg = <0x00000000 0x00064000>;
  145. read-only;
  146. };
  147. mtd1@64000 {
  148. label = "phy3250-uboot";
  149. reg = <0x00064000 0x00190000>;
  150. read-only;
  151. };
  152. mtd2@1f4000 {
  153. label = "phy3250-ubt-prms";
  154. reg = <0x001f4000 0x00010000>;
  155. };
  156. mtd3@204000 {
  157. label = "phy3250-kernel";
  158. reg = <0x00204000 0x00400000>;
  159. };
  160. mtd4@604000 {
  161. label = "phy3250-rootfs";
  162. reg = <0x00604000 0x039fc000>;
  163. };
  164. };
  165. };
  166. &ssp0 {
  167. num-cs = <1>;
  168. cs-gpios = <&gpio 3 5 0>;
  169. status = "okay";
  170. eeprom: at25@0 {
  171. compatible = "atmel,at25";
  172. reg = <0>;
  173. spi-max-frequency = <5000000>;
  174. pl022,interface = <0>;
  175. pl022,com-mode = <0>;
  176. pl022,rx-level-trig = <1>;
  177. pl022,tx-level-trig = <1>;
  178. pl022,ctrl-len = <11>;
  179. pl022,wait-state = <0>;
  180. pl022,duplex = <0>;
  181. at25,byte-len = <0x8000>;
  182. at25,addr-mode = <2>;
  183. at25,page-size = <64>;
  184. };
  185. };
  186. &tsc {
  187. status = "okay";
  188. };
  189. &uart2 {
  190. status = "okay";
  191. };
  192. &uart3 {
  193. status = "okay";
  194. };
  195. &uart5 {
  196. status = "okay";
  197. };