logicpd-som-lv.dtsi 8.6 KB

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  1. // SPDX-License-Identifier: GPL-2.0-only
  2. #include <dt-bindings/input/input.h>
  3. / {
  4. cpus {
  5. cpu@0 {
  6. cpu0-supply = <&vcc>;
  7. };
  8. };
  9. memory@80000000 {
  10. device_type = "memory";
  11. reg = <0x80000000 0>;
  12. };
  13. wl12xx_vmmc: wl12xx_vmmc {
  14. compatible = "regulator-fixed";
  15. regulator-name = "vwl1271";
  16. regulator-min-microvolt = <1800000>;
  17. regulator-max-microvolt = <1800000>;
  18. gpio = <&gpio1 3 0>; /* gpio_3 */
  19. startup-delay-us = <70000>;
  20. enable-active-high;
  21. vin-supply = <&vaux3>;
  22. };
  23. /* HS USB Host PHY on PORT 1 */
  24. hsusb2_phy: hsusb2_phy {
  25. pinctrl-names = "default";
  26. pinctrl-0 = <&hsusb2_reset_pin>;
  27. compatible = "usb-nop-xceiv";
  28. reset-gpios = <&gpio1 4 GPIO_ACTIVE_LOW>; /* gpio_4 */
  29. #phy-cells = <0>;
  30. };
  31. /* fixed 26MHz oscillator */
  32. hfclk_26m: oscillator {
  33. #clock-cells = <0>;
  34. compatible = "fixed-clock";
  35. clock-frequency = <26000000>;
  36. };
  37. };
  38. &gpmc {
  39. ranges = <0 0 0x30000000 0x1000000>; /* CS0: 16MB for NAND */
  40. nand@0,0 {
  41. compatible = "ti,omap2-nand";
  42. reg = <0 0 4>; /* CS0, offset 0, IO size 4 */
  43. interrupt-parent = <&gpmc>;
  44. interrupts = <0 IRQ_TYPE_NONE>, /* fifoevent */
  45. <1 IRQ_TYPE_NONE>; /* termcount */
  46. linux,mtd-name = "micron,mt29f4g16abbda3w";
  47. nand-bus-width = <16>;
  48. ti,nand-ecc-opt = "bch8";
  49. rb-gpios = <&gpmc 0 GPIO_ACTIVE_HIGH>; /* gpmc_wait0 */
  50. gpmc,sync-clk-ps = <0>;
  51. gpmc,cs-on-ns = <0>;
  52. gpmc,cs-rd-off-ns = <44>;
  53. gpmc,cs-wr-off-ns = <44>;
  54. gpmc,adv-on-ns = <6>;
  55. gpmc,adv-rd-off-ns = <34>;
  56. gpmc,adv-wr-off-ns = <44>;
  57. gpmc,we-off-ns = <40>;
  58. gpmc,oe-off-ns = <54>;
  59. gpmc,access-ns = <64>;
  60. gpmc,rd-cycle-ns = <82>;
  61. gpmc,wr-cycle-ns = <82>;
  62. gpmc,wr-access-ns = <40>;
  63. gpmc,wr-data-mux-bus-ns = <0>;
  64. gpmc,device-width = <2>;
  65. #address-cells = <1>;
  66. #size-cells = <1>;
  67. };
  68. };
  69. &i2c1 {
  70. pinctrl-names = "default";
  71. pinctrl-0 = <&i2c1_pins>;
  72. clock-frequency = <2600000>;
  73. twl: twl@48 {
  74. reg = <0x48>;
  75. interrupts = <7>; /* SYS_NIRQ cascaded to intc */
  76. interrupt-parent = <&intc>;
  77. clocks = <&hfclk_26m>;
  78. clock-names = "fck";
  79. twl_audio: audio {
  80. compatible = "ti,twl4030-audio";
  81. codec {
  82. ti,hs_extmute_gpio = <&gpio2 25 GPIO_ACTIVE_HIGH>;
  83. };
  84. };
  85. };
  86. };
  87. &i2c2 {
  88. pinctrl-names = "default";
  89. pinctrl-0 = <&i2c2_pins>;
  90. clock-frequency = <400000>;
  91. };
  92. &i2c3 {
  93. pinctrl-names = "default";
  94. pinctrl-0 = <&i2c3_pins>;
  95. clock-frequency = <400000>;
  96. touchscreen: tsc2004@48 {
  97. compatible = "ti,tsc2004";
  98. reg = <0x48>;
  99. vio-supply = <&vaux1>;
  100. pinctrl-names = "default";
  101. pinctrl-0 = <&tsc2004_pins>;
  102. interrupts-extended = <&gpio5 25 IRQ_TYPE_EDGE_RISING>; /* gpio 153 */
  103. touchscreen-fuzz-x = <4>;
  104. touchscreen-fuzz-y = <7>;
  105. touchscreen-fuzz-pressure = <2>;
  106. touchscreen-size-x = <4096>;
  107. touchscreen-size-y = <4096>;
  108. touchscreen-max-pressure = <2048>;
  109. ti,x-plate-ohms = <280>;
  110. ti,esd-recovery-timeout-ms = <8000>;
  111. };
  112. };
  113. &mmc3 {
  114. interrupts-extended = <&intc 94 &omap3_pmx_core 0x136>;
  115. pinctrl-0 = <&mmc3_pins &wl127x_gpio>;
  116. pinctrl-names = "default";
  117. vmmc-supply = <&wl12xx_vmmc>;
  118. non-removable;
  119. bus-width = <4>;
  120. cap-power-off-card;
  121. #address-cells = <1>;
  122. #size-cells = <0>;
  123. wlcore: wlcore@2 {
  124. compatible = "ti,wl1273";
  125. reg = <2>;
  126. interrupt-parent = <&gpio1>;
  127. interrupts = <2 IRQ_TYPE_EDGE_RISING>; /* gpio 2 */
  128. ref-clock-frequency = <26000000>;
  129. };
  130. };
  131. &usbhshost {
  132. pinctrl-names = "default";
  133. pinctrl-0 = <&hsusb2_pins>;
  134. port2-mode = "ehci-phy";
  135. };
  136. &usbhsehci {
  137. phys = <0 &hsusb2_phy>;
  138. };
  139. &omap3_pmx_core {
  140. mmc3_pins: pinmux_mm3_pins {
  141. pinctrl-single,pins = <
  142. OMAP3_CORE1_IOPAD(0x2164, PIN_INPUT_PULLUP | MUX_MODE3) /* sdmmc2_dat4.sdmmc3_dat0 */
  143. OMAP3_CORE1_IOPAD(0x2166, PIN_INPUT_PULLUP | MUX_MODE3) /* sdmmc2_dat5.sdmmc3_dat1 */
  144. OMAP3_CORE1_IOPAD(0x2168, PIN_INPUT_PULLUP | MUX_MODE3) /* sdmmc2_dat6.sdmmc3_dat2 */
  145. OMAP3_CORE1_IOPAD(0x216a, PIN_INPUT_PULLUP | MUX_MODE3) /* sdmmc2_dat6.sdmmc3_dat3 */
  146. OMAP3_CORE1_IOPAD(0x21d0, PIN_INPUT_PULLUP | MUX_MODE3) /* mcspi1_cs1.sdmmc3_cmd */
  147. OMAP3_CORE1_IOPAD(0x21d2, PIN_INPUT_PULLUP | MUX_MODE3) /* mcspi1_cs2.sdmmc_clk */
  148. >;
  149. };
  150. mcbsp2_pins: pinmux_mcbsp2_pins {
  151. pinctrl-single,pins = <
  152. OMAP3_CORE1_IOPAD(0x213c, PIN_INPUT | MUX_MODE0) /* mcbsp2_fsx */
  153. OMAP3_CORE1_IOPAD(0x213e, PIN_INPUT | MUX_MODE0) /* mcbsp2_clkx */
  154. OMAP3_CORE1_IOPAD(0x2140, PIN_INPUT | MUX_MODE0) /* mcbsp2_dr */
  155. OMAP3_CORE1_IOPAD(0x2142, PIN_OUTPUT | MUX_MODE0) /* mcbsp2_dx */
  156. >;
  157. };
  158. uart2_pins: pinmux_uart2_pins {
  159. pinctrl-single,pins = <
  160. OMAP3_CORE1_IOPAD(0x2174, PIN_INPUT | MUX_MODE0) /* uart2_cts.uart2_cts */
  161. OMAP3_CORE1_IOPAD(0x2176, PIN_OUTPUT | MUX_MODE0) /* uart2_rts .uart2_rts*/
  162. OMAP3_CORE1_IOPAD(0x2178, PIN_OUTPUT | MUX_MODE0) /* uart2_tx.uart2_tx */
  163. OMAP3_CORE1_IOPAD(0x217a, PIN_INPUT | MUX_MODE0) /* uart2_rx.uart2_rx */
  164. OMAP3_CORE1_IOPAD(0x2198, PIN_OUTPUT | MUX_MODE4) /* GPIO_162,BT_EN */
  165. >;
  166. };
  167. mcspi1_pins: pinmux_mcspi1_pins {
  168. pinctrl-single,pins = <
  169. OMAP3_CORE1_IOPAD(0x21c8, PIN_INPUT | MUX_MODE0) /* mcspi1_clk.mcspi1_clk */
  170. OMAP3_CORE1_IOPAD(0x21ca, PIN_OUTPUT | MUX_MODE0) /* mcspi1_simo.mcspi1_simo */
  171. OMAP3_CORE1_IOPAD(0x21cc, PIN_INPUT_PULLUP | MUX_MODE0) /* mcspi1_somi.mcspi1_somi */
  172. OMAP3_CORE1_IOPAD(0x21ce, PIN_OUTPUT | MUX_MODE0) /* mcspi1_cs0.mcspi1_cs0 */
  173. >;
  174. };
  175. hsusb2_pins: pinmux_hsusb2_pins {
  176. pinctrl-single,pins = <
  177. OMAP3_CORE1_IOPAD(0x21d4, PIN_INPUT_PULLDOWN | MUX_MODE3) /* mcspi1_cs3.hsusb2_data2 */
  178. OMAP3_CORE1_IOPAD(0x21d6, PIN_INPUT_PULLDOWN | MUX_MODE3) /* mcspi2_clk.hsusb2_data7 */
  179. OMAP3_CORE1_IOPAD(0x21d8, PIN_INPUT_PULLDOWN | MUX_MODE3) /* mcspi2_simo.hsusb2_data4 */
  180. OMAP3_CORE1_IOPAD(0x21da, PIN_INPUT_PULLDOWN | MUX_MODE3) /* mcspi2_somi.hsusb2_data5 */
  181. OMAP3_CORE1_IOPAD(0x21dc, PIN_INPUT_PULLDOWN | MUX_MODE3) /* mcspi2_cs0.hsusb2_data6 */
  182. OMAP3_CORE1_IOPAD(0x21de, PIN_INPUT_PULLDOWN | MUX_MODE3) /* mcspi2_cs1.hsusb2_data3 */
  183. >;
  184. };
  185. hsusb_otg_pins: pinmux_hsusb_otg_pins {
  186. pinctrl-single,pins = <
  187. OMAP3_CORE1_IOPAD(0x21a2, PIN_INPUT | MUX_MODE0) /* hsusb0_clk.hsusb0_clk */
  188. OMAP3_CORE1_IOPAD(0x21a4, PIN_OUTPUT | MUX_MODE0) /* hsusb0_stp.hsusb0_stp */
  189. OMAP3_CORE1_IOPAD(0x21a6, PIN_INPUT | MUX_MODE0) /* hsusb0_dir.hsusb0_dir */
  190. OMAP3_CORE1_IOPAD(0x21a8, PIN_INPUT | MUX_MODE0) /* hsusb0_nxt.hsusb0_nxt */
  191. OMAP3_CORE1_IOPAD(0x21aa, PIN_INPUT | MUX_MODE0) /* hsusb0_data0.hsusb0_data0 */
  192. OMAP3_CORE1_IOPAD(0x21ac, PIN_INPUT | MUX_MODE0) /* hsusb0_data1.hsusb0_data1 */
  193. OMAP3_CORE1_IOPAD(0x21ae, PIN_INPUT | MUX_MODE0) /* hsusb0_data2.hsusb0_data2 */
  194. OMAP3_CORE1_IOPAD(0x21b0, PIN_INPUT | MUX_MODE0) /* hsusb0_data3.hsusb0_data3 */
  195. OMAP3_CORE1_IOPAD(0x21b2, PIN_INPUT | MUX_MODE0) /* hsusb0_data4.hsusb0_data4 */
  196. OMAP3_CORE1_IOPAD(0x21b4, PIN_INPUT | MUX_MODE0) /* hsusb0_data5.hsusb0_data5 */
  197. OMAP3_CORE1_IOPAD(0x21b6, PIN_INPUT | MUX_MODE0) /* hsusb0_data6.hsusb0_data6 */
  198. OMAP3_CORE1_IOPAD(0x21b8, PIN_INPUT | MUX_MODE0) /* hsusb0_data7.hsusb0_data7 */
  199. >;
  200. };
  201. i2c1_pins: pinmux_i2c1_pins {
  202. pinctrl-single,pins = <
  203. OMAP3_CORE1_IOPAD(0x21ba, PIN_INPUT | MUX_MODE0) /* i2c1_scl.i2c1_scl */
  204. OMAP3_CORE1_IOPAD(0x21bc, PIN_INPUT | MUX_MODE0) /* i2c1_sda.i2c1_sda */
  205. OMAP3_CORE1_IOPAD(0x20ba, PIN_OUTPUT | MUX_MODE4) /* gpmc_ncs6.gpio_57 */
  206. >;
  207. };
  208. i2c2_pins: pinmux_i2c2_pins {
  209. pinctrl-single,pins = <
  210. OMAP3_CORE1_IOPAD(0x21be, PIN_INPUT | MUX_MODE0) /* i2c2_scl */
  211. OMAP3_CORE1_IOPAD(0x21c0, PIN_INPUT | MUX_MODE0) /* i2c2_sda */
  212. >;
  213. };
  214. i2c3_pins: pinmux_i2c3_pins {
  215. pinctrl-single,pins = <
  216. OMAP3_CORE1_IOPAD(0x21c2, PIN_INPUT | MUX_MODE0) /* i2c3_scl */
  217. OMAP3_CORE1_IOPAD(0x21c4, PIN_INPUT | MUX_MODE0) /* i2c3_sda */
  218. >;
  219. };
  220. tsc2004_pins: pinmux_tsc2004_pins {
  221. pinctrl-single,pins = <
  222. OMAP3_CORE1_IOPAD(0x2186, PIN_INPUT | MUX_MODE4) /* mcbsp4_dr.gpio_153 */
  223. >;
  224. };
  225. };
  226. &omap3_pmx_wkup {
  227. hsusb2_reset_pin: pinmux_hsusb1_reset_pin {
  228. pinctrl-single,pins = <
  229. OMAP3_WKUP_IOPAD(0x2a0e, PIN_OUTPUT | MUX_MODE4) /* sys_boot2.gpio_4 */
  230. >;
  231. };
  232. wl127x_gpio: pinmux_wl127x_gpio_pin {
  233. pinctrl-single,pins = <
  234. OMAP3_WKUP_IOPAD(0x2a0a, PIN_INPUT | MUX_MODE4) /* sys_boot0.gpio_2 */
  235. OMAP3_WKUP_IOPAD(0x2a0c, PIN_OUTPUT | MUX_MODE4) /* sys_boot1.gpio_3 */
  236. >;
  237. };
  238. };
  239. &uart2 {
  240. interrupts-extended = <&intc 73 &omap3_pmx_core OMAP3_UART2_RX>;
  241. pinctrl-names = "default";
  242. pinctrl-0 = <&uart2_pins>;
  243. };
  244. &mcspi1 {
  245. pinctrl-names = "default";
  246. pinctrl-0 = <&mcspi1_pins>;
  247. };
  248. #include "twl4030.dtsi"
  249. #include "twl4030_omap3.dtsi"
  250. &vaux3 {
  251. regulator-min-microvolt = <2800000>;
  252. regulator-max-microvolt = <2800000>;
  253. };
  254. &twl {
  255. twl_power: power {
  256. compatible = "ti,twl4030-power-idle-osc-off", "ti,twl4030-power-idle";
  257. ti,use_poweroff;
  258. };
  259. };
  260. &twl_gpio {
  261. ti,use-leds;
  262. };