intel-ixp42x-adi-coyote.dts 2.6 KB

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  1. // SPDX-License-Identifier: ISC
  2. /*
  3. * Device Tree file for ADI Engineering Coyote platform.
  4. * Derived from boardfiles written by MontaVista software.
  5. * Ethernet set-up from OpenWrt.
  6. */
  7. /dts-v1/;
  8. #include "intel-ixp42x.dtsi"
  9. #include <dt-bindings/input/input.h>
  10. / {
  11. model = "ADI Engineering Coyote reference design";
  12. compatible = "adieng,coyote", "intel,ixp42x";
  13. #address-cells = <1>;
  14. #size-cells = <1>;
  15. memory@0 {
  16. /* CHECKME: 16 MB SDRAM minimum, maybe the Coyote actually has more */
  17. device_type = "memory";
  18. reg = <0x00000000 0x01000000>;
  19. };
  20. chosen {
  21. bootargs = "console=ttyS0,115200n8 root=/dev/sda1 rw rootwait";
  22. stdout-path = "uart1:115200n8";
  23. };
  24. aliases {
  25. /* These are switched around */
  26. serial0 = &uart1;
  27. serial1 = &uart0;
  28. };
  29. soc {
  30. bus@c4000000 {
  31. flash@0,0 {
  32. compatible = "intel,ixp4xx-flash", "cfi-flash";
  33. bank-width = <2>;
  34. /*
  35. * 32 MB of Flash in 128 0x20000 sized blocks
  36. * mapped in at CS0 and CS1
  37. */
  38. reg = <0 0x00000000 0x2000000>;
  39. /* Configure expansion bus to allow writes */
  40. intel,ixp4xx-eb-write-enable = <1>;
  41. partitions {
  42. compatible = "redboot-fis";
  43. /* CHECKME: guess this is Redboot FIS */
  44. fis-index-block = <0x1ff>;
  45. };
  46. };
  47. };
  48. pci@c0000000 {
  49. status = "ok";
  50. /*
  51. * Taken from Coyote PCI boardfile.
  52. * We have slots (IDSEL) 1 and 2 with one assigned IRQ
  53. * each handling all IRQs.
  54. */
  55. #interrupt-cells = <1>;
  56. interrupt-map-mask = <0xf800 0 0 7>;
  57. interrupt-map =
  58. /* IDSEL 1 */
  59. <0x0800 0 0 1 &gpio0 6 IRQ_TYPE_LEVEL_LOW>, /* INT A on slot 1 is irq 6 */
  60. <0x0800 0 0 2 &gpio0 6 IRQ_TYPE_LEVEL_LOW>, /* INT B on slot 1 is irq 6 */
  61. <0x0800 0 0 3 &gpio0 6 IRQ_TYPE_LEVEL_LOW>, /* INT C on slot 1 is irq 6 */
  62. <0x0800 0 0 4 &gpio0 6 IRQ_TYPE_LEVEL_LOW>, /* INT D on slot 1 is irq 6 */
  63. /* IDSEL 2 */
  64. <0x1000 0 0 1 &gpio0 11 IRQ_TYPE_LEVEL_LOW>, /* INT A on slot 2 is irq 11 */
  65. <0x1000 0 0 2 &gpio0 11 IRQ_TYPE_LEVEL_LOW>, /* INT B on slot 2 is irq 11 */
  66. <0x1000 0 0 3 &gpio0 11 IRQ_TYPE_LEVEL_LOW>, /* INT C on slot 2 is irq 11 */
  67. <0x1000 0 0 4 &gpio0 11 IRQ_TYPE_LEVEL_LOW>; /* INT D on slot 2 is irq 11 */
  68. };
  69. /* EthB */
  70. ethernet@c8009000 {
  71. status = "ok";
  72. queue-rx = <&qmgr 3>;
  73. queue-txready = <&qmgr 20>;
  74. phy-mode = "rgmii";
  75. phy-handle = <&phy5>;
  76. mdio {
  77. #address-cells = <1>;
  78. #size-cells = <0>;
  79. phy4: ethernet-phy@4 {
  80. reg = <4>;
  81. };
  82. phy5: ethernet-phy@5 {
  83. reg = <5>;
  84. };
  85. };
  86. };
  87. /* EthC */
  88. ethernet@c800a000 {
  89. status = "ok";
  90. queue-rx = <&qmgr 4>;
  91. queue-txready = <&qmgr 21>;
  92. phy-mode = "rgmii";
  93. phy-handle = <&phy4>;
  94. };
  95. };
  96. };