imx7d-zii-rmu2.dts 7.3 KB

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  1. // SPDX-License-Identifier: (GPL-2.0 OR MIT)
  2. /*
  3. * Device tree file for ZII's RMU2 board
  4. *
  5. * RMU - Remote Modem Unit
  6. *
  7. * Copyright (C) 2019 Zodiac Inflight Innovations
  8. */
  9. /dts-v1/;
  10. #include <dt-bindings/thermal/thermal.h>
  11. #include "imx7d.dtsi"
  12. / {
  13. model = "ZII RMU2 Board";
  14. compatible = "zii,imx7d-rmu2", "fsl,imx7d";
  15. chosen {
  16. stdout-path = &uart2;
  17. };
  18. gpio-leds {
  19. compatible = "gpio-leds";
  20. pinctrl-0 = <&pinctrl_leds_debug>;
  21. pinctrl-names = "default";
  22. led-debug {
  23. label = "zii:green:debug1";
  24. gpios = <&gpio2 8 GPIO_ACTIVE_HIGH>;
  25. linux,default-trigger = "heartbeat";
  26. };
  27. };
  28. };
  29. &cpu0 {
  30. cpu-supply = <&sw1a_reg>;
  31. };
  32. &ecspi1 {
  33. pinctrl-names = "default";
  34. pinctrl-0 = <&pinctrl_ecspi1>;
  35. cs-gpios = <&gpio4 19 GPIO_ACTIVE_LOW>;
  36. status = "okay";
  37. flash@0 {
  38. compatible = "jedec,spi-nor";
  39. spi-max-frequency = <20000000>;
  40. reg = <0>;
  41. #address-cells = <1>;
  42. #size-cells = <1>;
  43. };
  44. };
  45. &fec1 {
  46. pinctrl-names = "default";
  47. pinctrl-0 = <&pinctrl_enet1>;
  48. assigned-clocks = <&clks IMX7D_ENET1_TIME_ROOT_SRC>,
  49. <&clks IMX7D_ENET1_TIME_ROOT_CLK>;
  50. assigned-clock-parents = <&clks IMX7D_PLL_ENET_MAIN_100M_CLK>;
  51. assigned-clock-rates = <0>, <100000000>;
  52. phy-mode = "rgmii-id";
  53. phy-handle = <&fec1_phy>;
  54. status = "okay";
  55. mdio {
  56. #address-cells = <1>;
  57. #size-cells = <0>;
  58. fec1_phy: ethernet-phy@0 {
  59. pinctrl-names = "default";
  60. pinctrl-0 = <&pinctrl_enet1_phy_reset>,
  61. <&pinctrl_enet1_phy_interrupt>;
  62. reg = <0>;
  63. interrupt-parent = <&gpio1>;
  64. interrupts = <2 IRQ_TYPE_LEVEL_LOW>;
  65. reset-gpios = <&gpio5 11 GPIO_ACTIVE_LOW>;
  66. };
  67. };
  68. };
  69. &i2c1 {
  70. clock-frequency = <100000>;
  71. pinctrl-names = "default";
  72. pinctrl-0 = <&pinctrl_i2c1>;
  73. status = "okay";
  74. pmic@8 {
  75. compatible = "fsl,pfuze3000";
  76. reg = <0x08>;
  77. regulators {
  78. sw1a_reg: sw1a {
  79. regulator-min-microvolt = <700000>;
  80. regulator-max-microvolt = <3300000>;
  81. regulator-boot-on;
  82. regulator-always-on;
  83. regulator-ramp-delay = <6250>;
  84. };
  85. sw1c_reg: sw1b {
  86. regulator-min-microvolt = <700000>;
  87. regulator-max-microvolt = <1475000>;
  88. regulator-boot-on;
  89. regulator-always-on;
  90. regulator-ramp-delay = <6250>;
  91. };
  92. sw2_reg: sw2 {
  93. regulator-min-microvolt = <1500000>;
  94. regulator-max-microvolt = <1850000>;
  95. regulator-boot-on;
  96. regulator-always-on;
  97. };
  98. sw3a_reg: sw3 {
  99. regulator-min-microvolt = <900000>;
  100. regulator-max-microvolt = <1650000>;
  101. regulator-boot-on;
  102. regulator-always-on;
  103. };
  104. swbst_reg: swbst {
  105. regulator-min-microvolt = <5000000>;
  106. regulator-max-microvolt = <5150000>;
  107. };
  108. snvs_reg: vsnvs {
  109. regulator-min-microvolt = <1000000>;
  110. regulator-max-microvolt = <3000000>;
  111. regulator-boot-on;
  112. regulator-always-on;
  113. };
  114. vref_reg: vrefddr {
  115. regulator-boot-on;
  116. regulator-always-on;
  117. };
  118. vgen1_reg: vldo1 {
  119. regulator-min-microvolt = <1800000>;
  120. regulator-max-microvolt = <3300000>;
  121. regulator-always-on;
  122. };
  123. vgen2_reg: vldo2 {
  124. regulator-min-microvolt = <800000>;
  125. regulator-max-microvolt = <1550000>;
  126. regulator-always-on;
  127. };
  128. vgen3_reg: vccsd {
  129. regulator-min-microvolt = <2850000>;
  130. regulator-max-microvolt = <3300000>;
  131. regulator-always-on;
  132. };
  133. vgen4_reg: v33 {
  134. regulator-min-microvolt = <2850000>;
  135. regulator-max-microvolt = <3300000>;
  136. regulator-always-on;
  137. };
  138. vgen5_reg: vldo3 {
  139. regulator-min-microvolt = <1800000>;
  140. regulator-max-microvolt = <3300000>;
  141. regulator-always-on;
  142. };
  143. vgen6_reg: vldo4 {
  144. regulator-min-microvolt = <1800000>;
  145. regulator-max-microvolt = <3300000>;
  146. regulator-always-on;
  147. };
  148. };
  149. };
  150. eeprom@50 {
  151. compatible = "atmel,24c04";
  152. reg = <0x50>;
  153. };
  154. eeprom@52 {
  155. compatible = "atmel,24c04";
  156. reg = <0x52>;
  157. };
  158. };
  159. &snvs_rtc {
  160. status = "disabled";
  161. };
  162. &uart2 {
  163. pinctrl-names = "default";
  164. pinctrl-0 = <&pinctrl_uart2>;
  165. assigned-clocks = <&clks IMX7D_UART2_ROOT_SRC>;
  166. assigned-clock-parents = <&clks IMX7D_OSC_24M_CLK>;
  167. status = "okay";
  168. };
  169. &uart4 {
  170. pinctrl-names = "default";
  171. pinctrl-0 = <&pinctrl_uart4>;
  172. assigned-clocks = <&clks IMX7D_UART4_ROOT_SRC>;
  173. assigned-clock-parents = <&clks IMX7D_PLL_SYS_MAIN_240M_CLK>;
  174. status = "okay";
  175. rave-sp {
  176. compatible = "zii,rave-sp-rdu2";
  177. current-speed = <1000000>;
  178. #address-cells = <1>;
  179. #size-cells = <1>;
  180. watchdog {
  181. compatible = "zii,rave-sp-watchdog";
  182. };
  183. eeprom@a3 {
  184. compatible = "zii,rave-sp-eeprom";
  185. reg = <0xa3 0x4000>;
  186. #address-cells = <1>;
  187. #size-cells = <1>;
  188. zii,eeprom-name = "main-eeprom";
  189. };
  190. };
  191. };
  192. &usbotg2 {
  193. dr_mode = "host";
  194. disable-over-current;
  195. status = "okay";
  196. };
  197. &usdhc1 {
  198. pinctrl-names = "default";
  199. pinctrl-0 = <&pinctrl_usdhc1>;
  200. bus-width = <4>;
  201. no-1-8-v;
  202. no-sdio;
  203. keep-power-in-suspend;
  204. status = "okay";
  205. };
  206. &usdhc3 {
  207. pinctrl-names = "default";
  208. pinctrl-0 = <&pinctrl_usdhc3>;
  209. bus-width = <8>;
  210. no-1-8-v;
  211. non-removable;
  212. no-sdio;
  213. no-sd;
  214. keep-power-in-suspend;
  215. status = "okay";
  216. };
  217. &wdog1 {
  218. status = "disabled";
  219. };
  220. &iomuxc {
  221. pinctrl_ecspi1: ecspi1grp {
  222. fsl,pins = <
  223. MX7D_PAD_ECSPI1_SCLK__ECSPI1_SCLK 0x2
  224. MX7D_PAD_ECSPI1_MOSI__ECSPI1_MOSI 0x2
  225. MX7D_PAD_ECSPI1_MISO__ECSPI1_MISO 0x2
  226. MX7D_PAD_ECSPI1_SS0__GPIO4_IO19 0x59
  227. >;
  228. };
  229. pinctrl_enet1: enet1grp {
  230. fsl,pins = <
  231. MX7D_PAD_SD2_CD_B__ENET1_MDIO 0x3
  232. MX7D_PAD_SD2_WP__ENET1_MDC 0x3
  233. MX7D_PAD_ENET1_RGMII_TXC__ENET1_RGMII_TXC 0x1
  234. MX7D_PAD_ENET1_RGMII_TD0__ENET1_RGMII_TD0 0x1
  235. MX7D_PAD_ENET1_RGMII_TD1__ENET1_RGMII_TD1 0x1
  236. MX7D_PAD_ENET1_RGMII_TD2__ENET1_RGMII_TD2 0x1
  237. MX7D_PAD_ENET1_RGMII_TD3__ENET1_RGMII_TD3 0x1
  238. MX7D_PAD_ENET1_RGMII_TX_CTL__ENET1_RGMII_TX_CTL 0x1
  239. MX7D_PAD_ENET1_RGMII_RXC__ENET1_RGMII_RXC 0x1
  240. MX7D_PAD_ENET1_RGMII_RD0__ENET1_RGMII_RD0 0x1
  241. MX7D_PAD_ENET1_RGMII_RD1__ENET1_RGMII_RD1 0x1
  242. MX7D_PAD_ENET1_RGMII_RD2__ENET1_RGMII_RD2 0x1
  243. MX7D_PAD_ENET1_RGMII_RD3__ENET1_RGMII_RD3 0x1
  244. MX7D_PAD_ENET1_RGMII_RX_CTL__ENET1_RGMII_RX_CTL 0x1
  245. >;
  246. };
  247. pinctrl_enet1_phy_reset: enet1phyresetgrp {
  248. fsl,pins = <
  249. MX7D_PAD_SD2_RESET_B__GPIO5_IO11 0x14
  250. >;
  251. };
  252. pinctrl_i2c1: i2c1grp {
  253. fsl,pins = <
  254. MX7D_PAD_I2C1_SDA__I2C1_SDA 0x4000007f
  255. MX7D_PAD_I2C1_SCL__I2C1_SCL 0x4000007f
  256. >;
  257. };
  258. pinctrl_leds_debug: ledsgrp {
  259. fsl,pins = <
  260. MX7D_PAD_EPDC_DATA08__GPIO2_IO8 0x59
  261. >;
  262. };
  263. pinctrl_uart2: uart2grp {
  264. fsl,pins = <
  265. MX7D_PAD_UART2_RX_DATA__UART2_DCE_RX 0x79
  266. MX7D_PAD_UART2_TX_DATA__UART2_DCE_TX 0x79
  267. >;
  268. };
  269. pinctrl_uart4: uart4grp {
  270. fsl,pins = <
  271. MX7D_PAD_SD2_DATA0__UART4_DCE_RX 0x79
  272. MX7D_PAD_SD2_DATA1__UART4_DCE_TX 0x79
  273. >;
  274. };
  275. pinctrl_usdhc1: usdhc1grp {
  276. fsl,pins = <
  277. MX7D_PAD_SD1_CMD__SD1_CMD 0x59
  278. MX7D_PAD_SD1_CLK__SD1_CLK 0x19
  279. MX7D_PAD_SD1_DATA0__SD1_DATA0 0x59
  280. MX7D_PAD_SD1_DATA1__SD1_DATA1 0x59
  281. MX7D_PAD_SD1_DATA2__SD1_DATA2 0x59
  282. MX7D_PAD_SD1_DATA3__SD1_DATA3 0x59
  283. >;
  284. };
  285. pinctrl_usdhc3: usdhc3grp {
  286. fsl,pins = <
  287. MX7D_PAD_SD3_CMD__SD3_CMD 0x59
  288. MX7D_PAD_SD3_CLK__SD3_CLK 0x19
  289. MX7D_PAD_SD3_DATA0__SD3_DATA0 0x59
  290. MX7D_PAD_SD3_DATA1__SD3_DATA1 0x59
  291. MX7D_PAD_SD3_DATA2__SD3_DATA2 0x59
  292. MX7D_PAD_SD3_DATA3__SD3_DATA3 0x59
  293. MX7D_PAD_SD3_DATA4__SD3_DATA4 0x59
  294. MX7D_PAD_SD3_DATA5__SD3_DATA5 0x59
  295. MX7D_PAD_SD3_DATA6__SD3_DATA6 0x59
  296. MX7D_PAD_SD3_DATA7__SD3_DATA7 0x59
  297. MX7D_PAD_SD3_RESET_B__SD3_RESET_B 0x59
  298. >;
  299. };
  300. };
  301. &iomuxc_lpsr {
  302. pinctrl_enet1_phy_interrupt: enet1phyinterruptgrp {
  303. fsl,phy = <
  304. MX7D_PAD_LPSR_GPIO1_IO02__GPIO1_IO2 0x08
  305. >;
  306. };
  307. };