imx6ul-pico.dtsi 10.0 KB

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  1. // SPDX-License-Identifier: (GPL-2.0 OR MIT)
  2. //
  3. // Copyright 2015 Technexion Ltd.
  4. //
  5. // Author: Wig Cheng <[email protected]>
  6. // Richard Hu <[email protected]>
  7. // Tapani Utriainen <[email protected]>
  8. /dts-v1/;
  9. #include "imx6ul.dtsi"
  10. / {
  11. /* Will be filled by the bootloader */
  12. memory@80000000 {
  13. device_type = "memory";
  14. reg = <0x80000000 0>;
  15. };
  16. chosen {
  17. stdout-path = &uart6;
  18. };
  19. backlight: backlight {
  20. compatible = "pwm-backlight";
  21. pwms = <&pwm3 0 5000000>;
  22. brightness-levels = <0 4 8 16 32 64 128 255>;
  23. default-brightness-level = <6>;
  24. status = "okay";
  25. };
  26. reg_2p5v: regulator-2p5v {
  27. compatible = "regulator-fixed";
  28. regulator-name = "2P5V";
  29. regulator-min-microvolt = <2500000>;
  30. regulator-max-microvolt = <2500000>;
  31. };
  32. reg_3p3v: regulator-3p3v {
  33. compatible = "regulator-fixed";
  34. regulator-name = "3P3V";
  35. regulator-min-microvolt = <3300000>;
  36. regulator-max-microvolt = <3300000>;
  37. };
  38. reg_sd1_vmmc: regulator-sd1-vmmc {
  39. compatible = "regulator-fixed";
  40. regulator-name = "VSD_3V3";
  41. regulator-min-microvolt = <3300000>;
  42. regulator-max-microvolt = <3300000>;
  43. gpio = <&gpio1 9 GPIO_ACTIVE_HIGH>;
  44. enable-active-high;
  45. };
  46. reg_usb_otg_vbus: regulator-usb-otg-vbus {
  47. compatible = "regulator-fixed";
  48. pinctrl-names = "default";
  49. pinctrl-0 = <&pinctrl_usb_otg1>;
  50. regulator-name = "usb_otg_vbus";
  51. regulator-min-microvolt = <5000000>;
  52. regulator-max-microvolt = <5000000>;
  53. gpio = <&gpio1 6 0>;
  54. };
  55. reg_brcm: regulator-brcm {
  56. compatible = "regulator-fixed";
  57. enable-active-high;
  58. gpio = <&gpio4 8 GPIO_ACTIVE_HIGH>;
  59. pinctrl-names = "default";
  60. pinctrl-0 = <&pinctrl_brcm_reg>;
  61. regulator-name = "brcm_reg";
  62. regulator-min-microvolt = <3300000>;
  63. regulator-max-microvolt = <3300000>;
  64. startup-delay-us = <200000>;
  65. };
  66. panel {
  67. compatible = "vxt,vl050-8048nt-c01";
  68. backlight = <&backlight>;
  69. port {
  70. panel_in: endpoint {
  71. remote-endpoint = <&display_out>;
  72. };
  73. };
  74. };
  75. };
  76. &can1 {
  77. pinctrl-names = "default";
  78. pinctrl-0 = <&pinctrl_flexcan1>;
  79. status = "okay";
  80. };
  81. &can2 {
  82. pinctrl-names = "default";
  83. pinctrl-0 = <&pinctrl_flexcan2>;
  84. status = "okay";
  85. };
  86. &clks {
  87. assigned-clocks = <&clks IMX6UL_CLK_PLL4_AUDIO_DIV>;
  88. assigned-clock-rates = <786432000>;
  89. };
  90. &fec2 {
  91. pinctrl-names = "default";
  92. pinctrl-0 = <&pinctrl_enet2>;
  93. phy-mode = "rmii";
  94. phy-handle = <&ethphy1>;
  95. status = "okay";
  96. phy-reset-gpios = <&gpio1 28 GPIO_ACTIVE_LOW>;
  97. phy-reset-duration = <1>;
  98. mdio {
  99. #address-cells = <1>;
  100. #size-cells = <0>;
  101. ethphy1: ethernet-phy@1 {
  102. compatible = "ethernet-phy-ieee802.3-c22";
  103. reg = <1>;
  104. max-speed = <100>;
  105. interrupt-parent = <&gpio5>;
  106. interrupts = <6 IRQ_TYPE_LEVEL_LOW>;
  107. clocks = <&clks IMX6UL_CLK_ENET_REF>;
  108. clock-names = "rmii-ref";
  109. };
  110. };
  111. };
  112. &i2c1 {
  113. clock-frequency = <100000>;
  114. pinctrl-names = "default";
  115. pinctrl-0 = <&pinctrl_i2c1>;
  116. status = "okay";
  117. pmic: pfuze3000@8 {
  118. compatible = "fsl,pfuze3000";
  119. reg = <0x08>;
  120. regulators {
  121. /* VDD_ARM_SOC_IN*/
  122. sw1b_reg: sw1b {
  123. regulator-min-microvolt = <700000>;
  124. regulator-max-microvolt = <1475000>;
  125. regulator-boot-on;
  126. regulator-always-on;
  127. regulator-ramp-delay = <6250>;
  128. };
  129. /* DRAM */
  130. sw3a_reg: sw3 {
  131. regulator-min-microvolt = <900000>;
  132. regulator-max-microvolt = <1650000>;
  133. regulator-boot-on;
  134. regulator-always-on;
  135. };
  136. /* DRAM */
  137. vref_reg: vrefddr {
  138. regulator-boot-on;
  139. regulator-always-on;
  140. };
  141. };
  142. };
  143. };
  144. &lcdif {
  145. pinctrl-names = "default";
  146. pinctrl-0 = <&pinctrl_lcdif_dat &pinctrl_lcdif_ctrl>;
  147. status = "okay";
  148. port {
  149. display_out: endpoint {
  150. remote-endpoint = <&panel_in>;
  151. };
  152. };
  153. };
  154. &pwm3 {
  155. #pwm-cells = <2>;
  156. pinctrl-names = "default";
  157. pinctrl-0 = <&pinctrl_pwm3>;
  158. status = "okay";
  159. };
  160. &pwm7 {
  161. pinctrl-names = "default";
  162. pinctrl-0 = <&pinctrl_pwm7>;
  163. status = "okay";
  164. };
  165. &pwm8 {
  166. pinctrl-names = "default";
  167. pinctrl-0 = <&pinctrl_pwm8>;
  168. status = "okay";
  169. };
  170. &sai1 {
  171. pinctrl-names = "default";
  172. pinctrl-0 = <&pinctrl_sai1>;
  173. status = "okay";
  174. };
  175. &uart3 {
  176. pinctrl-names = "default";
  177. pinctrl-0 = <&pinctrl_uart3>;
  178. uart-has-rtscts;
  179. status = "okay";
  180. };
  181. &uart6 {
  182. pinctrl-names = "default";
  183. pinctrl-0 = <&pinctrl_uart6>;
  184. status = "okay";
  185. };
  186. &usbotg1 {
  187. vbus-supply = <&reg_usb_otg_vbus>;
  188. pinctrl-names = "default";
  189. pinctrl-0 = <&pinctrl_usb_otg1_id>;
  190. dr_mode = "otg";
  191. disable-over-current;
  192. status = "okay";
  193. };
  194. &usbotg2 {
  195. dr_mode = "host";
  196. disable-over-current;
  197. status = "okay";
  198. };
  199. &usdhc1 {
  200. pinctrl-names = "default";
  201. pinctrl-0 = <&pinctrl_usdhc1>;
  202. bus-width = <8>;
  203. no-1-8-v;
  204. non-removable;
  205. keep-power-in-suspend;
  206. status = "okay";
  207. };
  208. &usdhc2 { /* Wifi SDIO */
  209. pinctrl-names = "default";
  210. pinctrl-0 = <&pinctrl_usdhc2>;
  211. no-1-8-v;
  212. non-removable;
  213. keep-power-in-suspend;
  214. wakeup-source;
  215. vmmc-supply = <&reg_brcm>;
  216. status = "okay";
  217. };
  218. &wdog1 {
  219. pinctrl-names = "default";
  220. pinctrl-0 = <&pinctrl_wdog>;
  221. fsl,ext-reset-output;
  222. };
  223. &iomuxc {
  224. pinctrl_brcm_reg: brcmreggrp {
  225. fsl,pins = <
  226. MX6UL_PAD_NAND_DATA06__GPIO4_IO08 0x10b0 /* WL_REG_ON */
  227. MX6UL_PAD_NAND_DATA04__GPIO4_IO06 0x10b0 /* WL_HOST_WAKE */
  228. >;
  229. };
  230. pinctrl_enet2: enet2grp {
  231. fsl,pins = <
  232. MX6UL_PAD_ENET1_TX_DATA1__ENET2_MDIO 0x1b0b0
  233. MX6UL_PAD_ENET1_TX_EN__ENET2_MDC 0x1b0b0
  234. MX6UL_PAD_ENET2_RX_EN__ENET2_RX_EN 0x1b0b0
  235. MX6UL_PAD_ENET2_RX_ER__ENET2_RX_ER 0x1b0b0
  236. MX6UL_PAD_ENET2_RX_DATA0__ENET2_RDATA00 0x1b0b0
  237. MX6UL_PAD_ENET2_RX_DATA1__ENET2_RDATA01 0x1b0b0
  238. MX6UL_PAD_ENET2_TX_EN__ENET2_TX_EN 0x1b0b0
  239. MX6UL_PAD_ENET2_TX_DATA0__ENET2_TDATA00 0x1b0b0
  240. MX6UL_PAD_ENET2_TX_DATA1__ENET2_TDATA01 0x1b0b0
  241. MX6UL_PAD_ENET2_TX_CLK__ENET2_REF_CLK2 0x4001b031
  242. MX6UL_PAD_SNVS_TAMPER6__GPIO5_IO06 0x800
  243. MX6UL_PAD_UART4_TX_DATA__GPIO1_IO28 0x79
  244. >;
  245. };
  246. pinctrl_flexcan1: flexcan1grp {
  247. fsl,pins = <
  248. MX6UL_PAD_ENET1_RX_DATA0__FLEXCAN1_TX 0x1b020
  249. MX6UL_PAD_ENET1_RX_DATA1__FLEXCAN1_RX 0x1b020
  250. >;
  251. };
  252. pinctrl_flexcan2: flexcan2grp {
  253. fsl,pins = <
  254. MX6UL_PAD_ENET1_TX_DATA0__FLEXCAN2_RX 0x1b020
  255. MX6UL_PAD_ENET1_RX_EN__FLEXCAN2_TX 0x1b020
  256. >;
  257. };
  258. pinctrl_i2c1: i2c1grp {
  259. fsl,pins = <
  260. MX6UL_PAD_GPIO1_IO02__I2C1_SCL 0x4001b8b0
  261. MX6UL_PAD_GPIO1_IO03__I2C1_SDA 0x4001b8b0
  262. >;
  263. };
  264. pinctrl_i2c2: i2c2grp {
  265. fsl,pins = <
  266. MX6UL_PAD_UART5_TX_DATA__I2C2_SCL 0x4001b8b0
  267. MX6UL_PAD_UART5_RX_DATA__I2C2_SDA 0x4001b8b0
  268. >;
  269. };
  270. pinctrl_i2c3: i2c3grp {
  271. fsl,pins = <
  272. MX6UL_PAD_UART1_TX_DATA__I2C3_SCL 0x4001b8b0
  273. MX6UL_PAD_UART1_RX_DATA__I2C3_SDA 0x4001b8b0
  274. >;
  275. };
  276. pinctrl_lcdif_dat: lcdifdatgrp {
  277. fsl,pins = <
  278. MX6UL_PAD_LCD_DATA00__LCDIF_DATA00 0x79
  279. MX6UL_PAD_LCD_DATA01__LCDIF_DATA01 0x79
  280. MX6UL_PAD_LCD_DATA02__LCDIF_DATA02 0x79
  281. MX6UL_PAD_LCD_DATA03__LCDIF_DATA03 0x79
  282. MX6UL_PAD_LCD_DATA04__LCDIF_DATA04 0x79
  283. MX6UL_PAD_LCD_DATA05__LCDIF_DATA05 0x79
  284. MX6UL_PAD_LCD_DATA06__LCDIF_DATA06 0x79
  285. MX6UL_PAD_LCD_DATA07__LCDIF_DATA07 0x79
  286. MX6UL_PAD_LCD_DATA08__LCDIF_DATA08 0x79
  287. MX6UL_PAD_LCD_DATA09__LCDIF_DATA09 0x79
  288. MX6UL_PAD_LCD_DATA10__LCDIF_DATA10 0x79
  289. MX6UL_PAD_LCD_DATA11__LCDIF_DATA11 0x79
  290. MX6UL_PAD_LCD_DATA12__LCDIF_DATA12 0x79
  291. MX6UL_PAD_LCD_DATA13__LCDIF_DATA13 0x79
  292. MX6UL_PAD_LCD_DATA14__LCDIF_DATA14 0x79
  293. MX6UL_PAD_LCD_DATA15__LCDIF_DATA15 0x79
  294. MX6UL_PAD_LCD_DATA16__LCDIF_DATA16 0x79
  295. MX6UL_PAD_LCD_DATA17__LCDIF_DATA17 0x79
  296. MX6UL_PAD_LCD_DATA18__LCDIF_DATA18 0x79
  297. MX6UL_PAD_LCD_DATA19__LCDIF_DATA19 0x79
  298. MX6UL_PAD_LCD_DATA20__LCDIF_DATA20 0x79
  299. MX6UL_PAD_LCD_DATA21__LCDIF_DATA21 0x79
  300. MX6UL_PAD_LCD_DATA22__LCDIF_DATA22 0x79
  301. MX6UL_PAD_LCD_DATA23__LCDIF_DATA23 0x79
  302. >;
  303. };
  304. pinctrl_lcdif_ctrl: lcdifctrlgrp {
  305. fsl,pins = <
  306. MX6UL_PAD_LCD_CLK__LCDIF_CLK 0x79
  307. MX6UL_PAD_LCD_ENABLE__LCDIF_ENABLE 0x79
  308. MX6UL_PAD_LCD_HSYNC__LCDIF_HSYNC 0x79
  309. MX6UL_PAD_LCD_VSYNC__LCDIF_VSYNC 0x79
  310. /* LCD reset */
  311. MX6UL_PAD_SNVS_TAMPER9__GPIO5_IO09 0x79
  312. >;
  313. };
  314. pinctrl_pwm3: pwm3grp {
  315. fsl,pins = <
  316. MX6UL_PAD_NAND_ALE__PWM3_OUT 0x110b0
  317. >;
  318. };
  319. pinctrl_pwm7: pwm7grp {
  320. fsl,pins = <
  321. MX6UL_PAD_ENET1_TX_CLK__PWM7_OUT 0x110b0
  322. >;
  323. };
  324. pinctrl_pwm8: pwm8grp {
  325. fsl,pins = <
  326. MX6UL_PAD_ENET1_RX_ER__PWM8_OUT 0x110b0
  327. >;
  328. };
  329. pinctrl_sai1: sai1grp {
  330. fsl,pins = <
  331. MX6UL_PAD_CSI_DATA04__SAI1_TX_SYNC 0x1b0b0
  332. MX6UL_PAD_CSI_DATA05__SAI1_TX_BCLK 0x1b0b0
  333. MX6UL_PAD_CSI_DATA06__SAI1_RX_DATA 0x110b0
  334. MX6UL_PAD_CSI_DATA07__SAI1_TX_DATA 0x1f0b8
  335. >;
  336. };
  337. pinctrl_uart3: uart3grp {
  338. fsl,pins = <
  339. MX6UL_PAD_UART3_TX_DATA__UART3_DCE_TX 0x1b0b0
  340. MX6UL_PAD_UART3_RX_DATA__UART3_DCE_RX 0x1b0b0
  341. MX6UL_PAD_UART3_RTS_B__UART3_DCE_RTS 0x1b0b0
  342. MX6UL_PAD_UART3_CTS_B__UART3_DCE_CTS 0x1b0b0
  343. >;
  344. };
  345. pinctrl_uart5: uart5grp {
  346. fsl,pins = <
  347. MX6UL_PAD_GPIO1_IO04__UART5_DCE_TX 0x1b0b1
  348. MX6UL_PAD_GPIO1_IO05__UART5_DCE_RX 0x1b0b1
  349. MX6UL_PAD_GPIO1_IO08__UART5_DCE_RTS 0x1b0b1
  350. MX6UL_PAD_GPIO1_IO09__UART5_DCE_CTS 0x1b0b1
  351. >;
  352. };
  353. pinctrl_uart6: uart6grp {
  354. fsl,pins = <
  355. MX6UL_PAD_CSI_MCLK__UART6_DCE_TX 0x1b0b1
  356. MX6UL_PAD_CSI_PIXCLK__UART6_DCE_RX 0x1b0b1
  357. >;
  358. };
  359. pinctrl_usb_otg1: usbotg1grp {
  360. fsl,pins = <
  361. MX6UL_PAD_GPIO1_IO06__GPIO1_IO06 0x10b0
  362. >;
  363. };
  364. pinctrl_usb_otg1_id: usbotg1idgrp {
  365. fsl,pins = <
  366. MX6UL_PAD_GPIO1_IO00__ANATOP_OTG1_ID 0x17059
  367. >;
  368. };
  369. pinctrl_usdhc1: usdhc1grp {
  370. fsl,pins = <
  371. MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x17059
  372. MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x10071
  373. MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x17059
  374. MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x17059
  375. MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x17059
  376. MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x17059
  377. MX6UL_PAD_UART1_RTS_B__USDHC1_CD_B 0x03029
  378. MX6UL_PAD_NAND_READY_B__USDHC1_DATA4 0x17059
  379. MX6UL_PAD_NAND_CE0_B__USDHC1_DATA5 0x17059
  380. MX6UL_PAD_NAND_CE1_B__USDHC1_DATA6 0x17059
  381. MX6UL_PAD_NAND_CLE__USDHC1_DATA7 0x17059
  382. >;
  383. };
  384. pinctrl_usdhc2: usdhc2grp {
  385. fsl,pins = <
  386. MX6UL_PAD_NAND_WE_B__USDHC2_CMD 0x17059
  387. MX6UL_PAD_NAND_RE_B__USDHC2_CLK 0x10059
  388. MX6UL_PAD_NAND_DATA00__USDHC2_DATA0 0x17059
  389. MX6UL_PAD_NAND_DATA01__USDHC2_DATA1 0x17059
  390. MX6UL_PAD_NAND_DATA02__USDHC2_DATA2 0x17059
  391. MX6UL_PAD_NAND_DATA03__USDHC2_DATA3 0x17059
  392. >;
  393. };
  394. pinctrl_wdog: wdoggrp {
  395. fsl,pins = <
  396. MX6UL_PAD_LCD_RESET__WDOG1_WDOG_ANY 0x30b0
  397. >;
  398. };
  399. };