imx6ul-imx6ull-opos6ul.dtsi 3.5 KB

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  1. // SPDX-License-Identifier: GPL-2.0 OR MIT
  2. //
  3. // Copyright 2019 Armadeus Systems <[email protected]>
  4. / {
  5. memory@80000000 {
  6. device_type = "memory";
  7. reg = <0x80000000 0>; /* will be filled by U-Boot */
  8. };
  9. reg_3v3: regulator-3v3 {
  10. compatible = "regulator-fixed";
  11. regulator-name = "3V3";
  12. regulator-min-microvolt = <3300000>;
  13. regulator-max-microvolt = <3300000>;
  14. };
  15. usdhc3_pwrseq: usdhc3-pwrseq {
  16. compatible = "mmc-pwrseq-simple";
  17. reset-gpios = <&gpio2 9 GPIO_ACTIVE_LOW>;
  18. };
  19. };
  20. &fec1 {
  21. pinctrl-names = "default";
  22. pinctrl-0 = <&pinctrl_enet1>;
  23. phy-mode = "rmii";
  24. phy-reset-duration = <1>;
  25. phy-reset-gpios = <&gpio4 2 GPIO_ACTIVE_LOW>;
  26. phy-handle = <&ethphy1>;
  27. phy-supply = <&reg_3v3>;
  28. status = "okay";
  29. mdio: mdio {
  30. #address-cells = <1>;
  31. #size-cells = <0>;
  32. ethphy1: ethernet-phy@1 {
  33. compatible = "ethernet-phy-ieee802.3-c22";
  34. reg = <1>;
  35. interrupt-parent = <&gpio4>;
  36. interrupts = <16 IRQ_TYPE_LEVEL_LOW>;
  37. status = "okay";
  38. };
  39. };
  40. };
  41. /* Bluetooth */
  42. &uart8 {
  43. pinctrl-names = "default";
  44. pinctrl-0 = <&pinctrl_uart8>;
  45. uart-has-rtscts;
  46. status = "okay";
  47. };
  48. /* eMMC */
  49. &usdhc1 {
  50. pinctrl-names = "default";
  51. pinctrl-0 = <&pinctrl_usdhc1>;
  52. bus-width = <8>;
  53. no-1-8-v;
  54. non-removable;
  55. status = "okay";
  56. };
  57. /* WiFi */
  58. &usdhc2 {
  59. pinctrl-names = "default";
  60. pinctrl-0 = <&pinctrl_usdhc2>;
  61. bus-width = <4>;
  62. no-1-8-v;
  63. non-removable;
  64. mmc-pwrseq = <&usdhc3_pwrseq>;
  65. status = "okay";
  66. #address-cells = <1>;
  67. #size-cells = <0>;
  68. brcmf: wifi@1 {
  69. compatible = "brcm,bcm4329-fmac";
  70. reg = <1>;
  71. interrupt-parent = <&gpio2>;
  72. interrupts = <8 IRQ_TYPE_LEVEL_LOW>;
  73. interrupt-names = "host-wake";
  74. };
  75. };
  76. &iomuxc {
  77. pinctrl_enet1: enet1grp {
  78. fsl,pins = <
  79. MX6UL_PAD_GPIO1_IO06__ENET1_MDIO 0x1b0b0
  80. MX6UL_PAD_GPIO1_IO07__ENET1_MDC 0x1b0b0
  81. MX6UL_PAD_ENET1_RX_ER__ENET1_RX_ER 0x130b0
  82. MX6UL_PAD_ENET1_RX_EN__ENET1_RX_EN 0x130b0
  83. MX6UL_PAD_ENET1_RX_DATA1__ENET1_RDATA01 0x130b0
  84. MX6UL_PAD_ENET1_RX_DATA0__ENET1_RDATA00 0x130b0
  85. MX6UL_PAD_ENET1_TX_DATA0__ENET1_TDATA00 0x1b0b0
  86. MX6UL_PAD_ENET1_TX_DATA1__ENET1_TDATA01 0x1b0b0
  87. MX6UL_PAD_ENET1_TX_EN__ENET1_TX_EN 0x1b0b0
  88. /* INT# */
  89. MX6UL_PAD_NAND_DQS__GPIO4_IO16 0x1b0b0
  90. /* RST# */
  91. MX6UL_PAD_NAND_DATA00__GPIO4_IO02 0x130b0
  92. MX6UL_PAD_ENET1_TX_CLK__ENET1_REF_CLK1 0x4001b031
  93. >;
  94. };
  95. pinctrl_uart8: uart8grp {
  96. fsl,pins = <
  97. MX6UL_PAD_ENET2_TX_EN__UART8_DCE_RX 0x1b0b0
  98. MX6UL_PAD_ENET2_TX_DATA1__UART8_DCE_TX 0x1b0b0
  99. MX6UL_PAD_ENET2_RX_ER__UART8_DCE_RTS 0x1b0b0
  100. MX6UL_PAD_ENET2_TX_CLK__UART8_DCE_CTS 0x1b0b0
  101. /* BT_REG_ON */
  102. MX6UL_PAD_ENET2_RX_EN__GPIO2_IO10 0x130b0
  103. >;
  104. };
  105. pinctrl_usdhc1: usdhc1grp {
  106. fsl,pins = <
  107. MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x17059
  108. MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x10059
  109. MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x17059
  110. MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x17059
  111. MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x17059
  112. MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x17059
  113. MX6UL_PAD_NAND_READY_B__USDHC1_DATA4 0x17059
  114. MX6UL_PAD_NAND_CE0_B__USDHC1_DATA5 0x17059
  115. MX6UL_PAD_NAND_CE1_B__USDHC1_DATA6 0x17059
  116. MX6UL_PAD_NAND_CLE__USDHC1_DATA7 0x17059
  117. >;
  118. };
  119. pinctrl_usdhc2: usdhc2grp {
  120. fsl,pins = <
  121. MX6UL_PAD_LCD_DATA18__USDHC2_CMD 0x1b0b0
  122. MX6UL_PAD_LCD_DATA19__USDHC2_CLK 0x100b0
  123. MX6UL_PAD_LCD_DATA20__USDHC2_DATA0 0x1b0b0
  124. MX6UL_PAD_LCD_DATA21__USDHC2_DATA1 0x1b0b0
  125. MX6UL_PAD_LCD_DATA22__USDHC2_DATA2 0x1b0b0
  126. MX6UL_PAD_LCD_DATA23__USDHC2_DATA3 0x1b0b0
  127. /* WL_REG_ON */
  128. MX6UL_PAD_ENET2_RX_DATA1__GPIO2_IO09 0x130b0
  129. /* WL_IRQ */
  130. MX6UL_PAD_ENET2_RX_DATA0__GPIO2_IO08 0x1b0b0
  131. >;
  132. };
  133. };