imx6ul-ccimx6ulsbcpro.dts 9.3 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241242243244245246247248249250251252253254255256257258259260261262263264265266267268269270271272273274275276277278279280281282283284285286287288289290291292293294295296297298299300301302303304305306307308309310311312313314315316317318319320321322323324325326327328329330331332333334335336337338339340341342343344345346347348349350351352353354355356357358359360361362363364365366367368369370371372373374375376377378379380381382383384385386387388389390391392393394395396397398399400401402403404405406407408409410411412413414415416417418419420421422423424425426427428
  1. // SPDX-License-Identifier: GPL-2.0
  2. /*
  3. * Digi International's ConnectCore6UL SBC Pro board device tree source
  4. *
  5. * Copyright 2018 Digi International, Inc.
  6. *
  7. */
  8. /dts-v1/;
  9. #include <dt-bindings/input/input.h>
  10. #include <dt-bindings/interrupt-controller/irq.h>
  11. #include "imx6ul.dtsi"
  12. #include "imx6ul-ccimx6ulsom.dtsi"
  13. / {
  14. model = "Digi International ConnectCore 6UL SBC Pro.";
  15. compatible = "digi,ccimx6ulsbcpro", "digi,ccimx6ulsom", "fsl,imx6ul";
  16. lcd_backlight: backlight {
  17. compatible = "pwm-backlight";
  18. pwms = <&pwm5 0 50000>;
  19. brightness-levels = <0 4 8 16 32 64 128 255>;
  20. default-brightness-level = <6>;
  21. status = "okay";
  22. };
  23. panel {
  24. compatible = "auo,g101evn010";
  25. power-supply = <&ldo4_ext>;
  26. backlight = <&lcd_backlight>;
  27. port {
  28. panel_in: endpoint {
  29. remote-endpoint = <&display_out>;
  30. };
  31. };
  32. };
  33. reg_usb_otg1_vbus: regulator-usb-otg1 {
  34. compatible = "regulator-fixed";
  35. regulator-name = "usb_otg1_vbus";
  36. regulator-min-microvolt = <5000000>;
  37. regulator-max-microvolt = <5000000>;
  38. gpio = <&gpio1 4 GPIO_ACTIVE_HIGH>;
  39. enable-active-high;
  40. };
  41. };
  42. &adc1 {
  43. pinctrl-names = "default";
  44. pinctrl-0 = <&pinctrl_adc1>;
  45. status = "okay";
  46. };
  47. &can1 {
  48. pinctrl-names = "default";
  49. pinctrl-0 = <&pinctrl_flexcan1>;
  50. xceiver-supply = <&ext_3v3>;
  51. status = "okay";
  52. };
  53. /* CAN2 is multiplexed with UART2 RTS/CTS */
  54. &can2 {
  55. pinctrl-names = "default";
  56. pinctrl-0 = <&pinctrl_flexcan2>;
  57. xceiver-supply = <&ext_3v3>;
  58. status = "disabled";
  59. };
  60. &ecspi1 {
  61. cs-gpios = <&gpio3 26 GPIO_ACTIVE_LOW>;
  62. pinctrl-names = "default";
  63. pinctrl-0 = <&pinctrl_ecspi1_master>;
  64. status = "okay";
  65. };
  66. &fec1 {
  67. pinctrl-names = "default";
  68. pinctrl-0 = <&pinctrl_enet1>;
  69. phy-mode = "rmii";
  70. phy-handle = <&ethphy0>;
  71. status = "okay";
  72. };
  73. &fec2 {
  74. pinctrl-names = "default";
  75. pinctrl-0 = <&pinctrl_enet2 &pinctrl_enet2_mdio>;
  76. phy-mode = "rmii";
  77. phy-handle = <&ethphy1>;
  78. phy-reset-gpios = <&gpio5 6 GPIO_ACTIVE_LOW>;
  79. phy-reset-duration = <26>;
  80. status = "okay";
  81. mdio {
  82. #address-cells = <1>;
  83. #size-cells = <0>;
  84. ethphy0: ethernet-phy@0 {
  85. compatible = "ethernet-phy-ieee802.3-c22";
  86. smsc,disable-energy-detect;
  87. reg = <0>;
  88. };
  89. ethphy1: ethernet-phy@1 {
  90. compatible = "ethernet-phy-ieee802.3-c22";
  91. smsc,disable-energy-detect;
  92. reg = <1>;
  93. };
  94. };
  95. };
  96. &gpio5 {
  97. emmc-usd-mux-hog {
  98. gpio-hog;
  99. gpios = <1 GPIO_ACTIVE_LOW>;
  100. output-high;
  101. };
  102. };
  103. &i2c1 {
  104. touchscreen@14 {
  105. compatible = "goodix,gt911";
  106. reg = <0x14>;
  107. pinctrl-names = "default";
  108. pinctrl-0 = <&pinctrl_goodix_touch>;
  109. interrupt-parent = <&gpio5>;
  110. interrupts = <2 IRQ_TYPE_EDGE_RISING>;
  111. irq-gpios = <&gpio5 2 GPIO_ACTIVE_HIGH>;
  112. status = "okay";
  113. };
  114. };
  115. &lcdif {
  116. pinctrl-names = "default";
  117. pinctrl-0 = <&pinctrl_lcdif_dat0_17
  118. &pinctrl_lcdif_clken
  119. &pinctrl_lcdif_hvsync>;
  120. lcd-supply = <&ldo4_ext>; /* BU90T82 LVDS bridge power */
  121. status = "okay";
  122. port {
  123. display_out: endpoint {
  124. remote-endpoint = <&panel_in>;
  125. };
  126. };
  127. };
  128. &ldo4_ext {
  129. regulator-max-microvolt = <1800000>;
  130. };
  131. &pwm1 {
  132. status = "okay";
  133. };
  134. &pwm2 {
  135. status = "okay";
  136. };
  137. &pwm3 {
  138. status = "okay";
  139. };
  140. &pwm4 {
  141. pinctrl-names = "default";
  142. pinctrl-0 = <&pinctrl_pwm4>;
  143. status = "okay";
  144. };
  145. &pwm5 {
  146. #pwm-cells = <2>;
  147. pinctrl-names = "default";
  148. pinctrl-0 = <&pinctrl_pwm5>;
  149. status = "okay";
  150. };
  151. &pwm6 {
  152. status = "okay";
  153. };
  154. &pwm7 {
  155. status = "okay";
  156. };
  157. &pwm8 {
  158. status = "okay";
  159. };
  160. &sai2 {
  161. pinctrl-names = "default", "sleep";
  162. pinctrl-0 = <&pinctrl_sai2>;
  163. pinctrl-1 = <&pinctrl_sai2_sleep>;
  164. assigned-clocks = <&clks IMX6UL_CLK_SAI2_SEL>,
  165. <&clks IMX6UL_CLK_PLL4_AUDIO_DIV>,
  166. <&clks IMX6UL_CLK_SAI2>;
  167. assigned-clock-rates = <0>, <786432000>, <12288000>;
  168. assigned-clock-parents = <&clks IMX6UL_CLK_PLL4_AUDIO_DIV>;
  169. status = "okay";
  170. };
  171. /* UART2 RTS/CTS muxed with CAN2 */
  172. &uart2 {
  173. pinctrl-names = "default";
  174. pinctrl-0 = <&pinctrl_uart2_4wires>;
  175. uart-has-rtscts;
  176. status = "okay";
  177. };
  178. /* UART3 RTS/CTS muxed with CAN 1 */
  179. &uart3 {
  180. pinctrl-names = "default";
  181. pinctrl-0 = <&pinctrl_uart3_2wires>;
  182. status = "okay";
  183. };
  184. &uart5 {
  185. pinctrl-names = "default";
  186. pinctrl-0 = <&pinctrl_uart5>;
  187. status = "okay";
  188. };
  189. &usbotg1 {
  190. dr_mode = "otg";
  191. vbus-supply = <&reg_usb_otg1_vbus>;
  192. pinctrl-0 = <&pinctrl_usbotg1>;
  193. status = "okay";
  194. };
  195. &usbotg2 {
  196. dr_mode = "host";
  197. disable-over-current;
  198. status = "okay";
  199. };
  200. /* USDHC2 (microSD conflicts with eMMC) */
  201. &usdhc2 {
  202. pinctrl-names = "default";
  203. pinctrl-0 = <&pinctrl_usdhc2>;
  204. no-1-8-v;
  205. broken-cd; /* no carrier detect line (use polling) */
  206. status = "okay";
  207. };
  208. &iomuxc {
  209. pinctrl_adc1: adc1grp {
  210. fsl,pins = <
  211. /* EXP_GPIO_2 -> GPIO1_3/ADC1_IN3 */
  212. MX6UL_PAD_GPIO1_IO03__GPIO1_IO03 0xb0
  213. >;
  214. };
  215. pinctrl_ecspi1_master: ecspi1grp1 {
  216. fsl,pins = <
  217. MX6UL_PAD_LCD_DATA20__ECSPI1_SCLK 0x10b0
  218. MX6UL_PAD_LCD_DATA22__ECSPI1_MOSI 0x10b0
  219. MX6UL_PAD_LCD_DATA23__ECSPI1_MISO 0x10b0
  220. MX6UL_PAD_LCD_DATA21__GPIO3_IO26 0x10b0
  221. >;
  222. };
  223. pinctrl_enet1: enet1grp {
  224. fsl,pins = <
  225. MX6UL_PAD_ENET1_RX_EN__ENET1_RX_EN 0x1b0b0
  226. MX6UL_PAD_ENET1_RX_ER__ENET1_RX_ER 0x1b0b0
  227. MX6UL_PAD_ENET1_RX_DATA0__ENET1_RDATA00 0x1b0b0
  228. MX6UL_PAD_ENET1_RX_DATA1__ENET1_RDATA01 0x1b0b0
  229. MX6UL_PAD_ENET1_TX_EN__ENET1_TX_EN 0x1b0b0
  230. MX6UL_PAD_ENET1_TX_DATA0__ENET1_TDATA00 0x1b0b0
  231. MX6UL_PAD_ENET1_TX_DATA1__ENET1_TDATA01 0x1b0b0
  232. MX6UL_PAD_ENET1_TX_CLK__ENET1_REF_CLK1 0x40017051
  233. >;
  234. };
  235. pinctrl_enet2: enet2grp {
  236. fsl,pins = <
  237. MX6UL_PAD_ENET2_RX_EN__ENET2_RX_EN 0x1b0b0
  238. MX6UL_PAD_ENET2_RX_ER__ENET2_RX_ER 0x1b0b0
  239. MX6UL_PAD_ENET2_RX_DATA0__ENET2_RDATA00 0x1b0b0
  240. MX6UL_PAD_ENET2_RX_DATA1__ENET2_RDATA01 0x1b0b0
  241. MX6UL_PAD_ENET2_TX_EN__ENET2_TX_EN 0x1b0b0
  242. MX6UL_PAD_ENET2_TX_DATA0__ENET2_TDATA00 0x1b0b0
  243. MX6UL_PAD_ENET2_TX_DATA1__ENET2_TDATA01 0x1b0b0
  244. MX6UL_PAD_ENET2_TX_CLK__ENET2_REF_CLK2 0x40017051
  245. >;
  246. };
  247. pinctrl_enet2_mdio: mdioenet2grp {
  248. fsl,pins = <
  249. MX6UL_PAD_GPIO1_IO07__ENET2_MDC 0x1b0b0
  250. MX6UL_PAD_GPIO1_IO06__ENET2_MDIO 0x1b0b0
  251. >;
  252. };
  253. pinctrl_flexcan1: flexcan1grp{
  254. fsl,pins = <
  255. MX6UL_PAD_UART3_CTS_B__FLEXCAN1_TX 0x1b020
  256. MX6UL_PAD_UART3_RTS_B__FLEXCAN1_RX 0x1b020
  257. >;
  258. };
  259. pinctrl_flexcan2: flexcan2grp{
  260. fsl,pins = <
  261. MX6UL_PAD_UART2_CTS_B__FLEXCAN2_TX 0x1b020
  262. MX6UL_PAD_UART2_RTS_B__FLEXCAN2_RX 0x1b020
  263. >;
  264. };
  265. pinctrl_goodix_touch: goodixgrp{
  266. fsl,pins = <
  267. MX6UL_PAD_SNVS_TAMPER2__GPIO5_IO02 0x1020
  268. >;
  269. };
  270. pinctrl_lcdif_dat0_17: lcdifdatgrp0-17 {
  271. fsl,pins = <
  272. MX6UL_PAD_LCD_DATA00__LCDIF_DATA00 0x79
  273. MX6UL_PAD_LCD_DATA01__LCDIF_DATA01 0x79
  274. MX6UL_PAD_LCD_DATA02__LCDIF_DATA02 0x79
  275. MX6UL_PAD_LCD_DATA03__LCDIF_DATA03 0x79
  276. MX6UL_PAD_LCD_DATA04__LCDIF_DATA04 0x79
  277. MX6UL_PAD_LCD_DATA05__LCDIF_DATA05 0x79
  278. MX6UL_PAD_LCD_DATA06__LCDIF_DATA06 0x79
  279. MX6UL_PAD_LCD_DATA07__LCDIF_DATA07 0x79
  280. MX6UL_PAD_LCD_DATA08__LCDIF_DATA08 0x79
  281. MX6UL_PAD_LCD_DATA09__LCDIF_DATA09 0x79
  282. MX6UL_PAD_LCD_DATA10__LCDIF_DATA10 0x79
  283. MX6UL_PAD_LCD_DATA11__LCDIF_DATA11 0x79
  284. MX6UL_PAD_LCD_DATA12__LCDIF_DATA12 0x79
  285. MX6UL_PAD_LCD_DATA13__LCDIF_DATA13 0x79
  286. MX6UL_PAD_LCD_DATA14__LCDIF_DATA14 0x79
  287. MX6UL_PAD_LCD_DATA15__LCDIF_DATA15 0x79
  288. MX6UL_PAD_LCD_DATA16__LCDIF_DATA16 0x79
  289. MX6UL_PAD_LCD_DATA17__LCDIF_DATA17 0x79
  290. >;
  291. };
  292. pinctrl_lcdif_clken: lcdifctrlgrp1 {
  293. fsl,pins = <
  294. MX6UL_PAD_LCD_CLK__LCDIF_CLK 0x17050
  295. MX6UL_PAD_LCD_ENABLE__LCDIF_ENABLE 0x79
  296. >;
  297. };
  298. pinctrl_lcdif_hvsync: lcdifctrlgrp2 {
  299. fsl,pins = <
  300. MX6UL_PAD_LCD_HSYNC__LCDIF_HSYNC 0x79
  301. MX6UL_PAD_LCD_VSYNC__LCDIF_VSYNC 0x79
  302. >;
  303. };
  304. pinctrl_pwm4: pwm4grp {
  305. fsl,pins = <
  306. MX6UL_PAD_GPIO1_IO05__PWM4_OUT 0x110b0
  307. >;
  308. };
  309. pinctrl_pwm5: pwm5grp {
  310. fsl,pins = <
  311. MX6UL_PAD_NAND_DQS__PWM5_OUT 0x110b0
  312. >;
  313. };
  314. pinctrl_sai2: sai2grp {
  315. fsl,pins = <
  316. MX6UL_PAD_JTAG_TRST_B__SAI2_TX_DATA 0x11088
  317. MX6UL_PAD_JTAG_TCK__SAI2_RX_DATA 0x11088
  318. MX6UL_PAD_JTAG_TMS__SAI2_MCLK 0x17088
  319. MX6UL_PAD_JTAG_TDI__SAI2_TX_BCLK 0x17088
  320. MX6UL_PAD_JTAG_TDO__SAI2_TX_SYNC 0x17088
  321. /* Interrupt */
  322. MX6UL_PAD_SNVS_TAMPER7__GPIO5_IO07 0x10b0
  323. >;
  324. };
  325. pinctrl_sai2_sleep: sai2grp-sleep {
  326. fsl,pins = <
  327. MX6UL_PAD_JTAG_TRST_B__GPIO1_IO15 0x3000
  328. MX6UL_PAD_JTAG_TCK__GPIO1_IO14 0x3000
  329. MX6UL_PAD_JTAG_TMS__GPIO1_IO11 0x3000
  330. MX6UL_PAD_JTAG_TDO__GPIO1_IO12 0x3000
  331. /* Interrupt */
  332. MX6UL_PAD_SNVS_TAMPER7__GPIO5_IO07 0x3000
  333. >;
  334. };
  335. pinctrl_uart2_4wires: uart2grp-4wires {
  336. fsl,pins = <
  337. MX6UL_PAD_UART2_TX_DATA__UART2_DCE_TX 0x1b0b1
  338. MX6UL_PAD_UART2_RX_DATA__UART2_DCE_RX 0x1b0b1
  339. MX6UL_PAD_UART2_CTS_B__UART2_DCE_CTS 0x1b0b1
  340. MX6UL_PAD_UART2_RTS_B__UART2_DCE_RTS 0x1b0b1
  341. >;
  342. };
  343. pinctrl_uart3_2wires: uart3grp-2wires {
  344. fsl,pins = <
  345. MX6UL_PAD_UART3_TX_DATA__UART3_DCE_TX 0x1b0b1
  346. MX6UL_PAD_UART3_RX_DATA__UART3_DCE_RX 0x1b0b1
  347. >;
  348. };
  349. pinctrl_uart5: uart5grp {
  350. fsl,pins = <
  351. MX6UL_PAD_UART5_TX_DATA__UART5_DCE_TX 0x1b0b1
  352. MX6UL_PAD_UART5_RX_DATA__UART5_DCE_RX 0x1b0b1
  353. >;
  354. };
  355. pinctrl_usdhc2: usdhc2grp {
  356. fsl,pins = <
  357. MX6UL_PAD_CSI_HSYNC__USDHC2_CMD 0x17059
  358. MX6UL_PAD_CSI_VSYNC__USDHC2_CLK 0x10039
  359. MX6UL_PAD_CSI_DATA00__USDHC2_DATA0 0x17059
  360. MX6UL_PAD_CSI_DATA01__USDHC2_DATA1 0x17059
  361. MX6UL_PAD_CSI_DATA02__USDHC2_DATA2 0x17059
  362. MX6UL_PAD_CSI_DATA03__USDHC2_DATA3 0x17059
  363. /* Mux selector between eMMC/SD# */
  364. MX6UL_PAD_SNVS_TAMPER1__GPIO5_IO01 0x79
  365. >;
  366. };
  367. pinctrl_usbotg1: usbotg1grp {
  368. fsl,pins = <
  369. MX6UL_PAD_GPIO1_IO00__ANATOP_OTG1_ID 0x17059
  370. MX6UL_PAD_GPIO1_IO04__GPIO1_IO04 0x17059
  371. MX6UL_PAD_GPIO1_IO01__USB_OTG1_OC 0x17059
  372. >;
  373. };
  374. };