imx6sx-sabreauto.dts 13 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. //
  3. // Copyright (C) 2014 Freescale Semiconductor, Inc.
  4. /dts-v1/;
  5. #include "imx6sx.dtsi"
  6. / {
  7. model = "Freescale i.MX6 SoloX Sabre Auto Board";
  8. compatible = "fsl,imx6sx-sabreauto", "fsl,imx6sx";
  9. memory@80000000 {
  10. device_type = "memory";
  11. reg = <0x80000000 0x80000000>;
  12. };
  13. leds {
  14. compatible = "gpio-leds";
  15. pinctrl-names = "default";
  16. pinctrl-0 = <&pinctrl_led>;
  17. led-user {
  18. label = "debug";
  19. gpios = <&gpio1 24 GPIO_ACTIVE_HIGH>;
  20. linux,default-trigger = "heartbeat";
  21. };
  22. };
  23. vcc_sd3: regulator-vcc-sd3 {
  24. compatible = "regulator-fixed";
  25. pinctrl-names = "default";
  26. pinctrl-0 = <&pinctrl_vcc_sd3>;
  27. regulator-name = "VCC_SD3";
  28. regulator-min-microvolt = <3000000>;
  29. regulator-max-microvolt = <3000000>;
  30. gpio = <&gpio2 11 GPIO_ACTIVE_HIGH>;
  31. enable-active-high;
  32. };
  33. reg_can_wake: regulator-can-wake {
  34. compatible = "regulator-fixed";
  35. regulator-name = "can-wake";
  36. regulator-min-microvolt = <3300000>;
  37. regulator-max-microvolt = <3300000>;
  38. gpio = <&max7310_b 7 GPIO_ACTIVE_HIGH>;
  39. enable-active-high;
  40. };
  41. reg_can_en: regulator-can-en {
  42. compatible = "regulator-fixed";
  43. regulator-name = "can-en";
  44. regulator-min-microvolt = <3300000>;
  45. regulator-max-microvolt = <3300000>;
  46. gpio = <&max7310_b 5 GPIO_ACTIVE_HIGH>;
  47. enable-active-high;
  48. vin-supply = <&reg_can_wake>;
  49. };
  50. reg_can_stby: regulator-can-stby {
  51. compatible = "regulator-fixed";
  52. regulator-name = "can-stby";
  53. regulator-min-microvolt = <3300000>;
  54. regulator-max-microvolt = <3300000>;
  55. gpio = <&max7310_b 4 GPIO_ACTIVE_HIGH>;
  56. enable-active-high;
  57. vin-supply = <&reg_can_en>;
  58. };
  59. reg_cs42888: cs42888_supply {
  60. compatible = "regulator-fixed";
  61. regulator-name = "cs42888_supply";
  62. regulator-min-microvolt = <3300000>;
  63. regulator-max-microvolt = <3300000>;
  64. regulator-always-on;
  65. };
  66. sound-cs42888 {
  67. compatible = "fsl,imx6-sabreauto-cs42888",
  68. "fsl,imx-audio-cs42888";
  69. model = "imx-cs42888";
  70. audio-cpu = <&esai>;
  71. audio-asrc = <&asrc>;
  72. audio-codec = <&cs42888>;
  73. audio-routing =
  74. "Line Out Jack", "AOUT1L",
  75. "Line Out Jack", "AOUT1R",
  76. "Line Out Jack", "AOUT2L",
  77. "Line Out Jack", "AOUT2R",
  78. "Line Out Jack", "AOUT3L",
  79. "Line Out Jack", "AOUT3R",
  80. "Line Out Jack", "AOUT4L",
  81. "Line Out Jack", "AOUT4R",
  82. "AIN1L", "Line In Jack",
  83. "AIN1R", "Line In Jack",
  84. "AIN2L", "Line In Jack",
  85. "AIN2R", "Line In Jack";
  86. };
  87. sound-spdif {
  88. compatible = "fsl,imx-audio-spdif";
  89. model = "imx-spdif";
  90. spdif-controller = <&spdif>;
  91. spdif-in;
  92. };
  93. };
  94. &anaclk2 {
  95. clock-frequency = <24576000>;
  96. };
  97. &clks {
  98. assigned-clocks = <&clks IMX6SX_PLL4_BYPASS_SRC>,
  99. <&clks IMX6SX_PLL4_BYPASS>,
  100. <&clks IMX6SX_CLK_PLL4_POST_DIV>;
  101. assigned-clock-parents = <&clks IMX6SX_CLK_LVDS2_IN>,
  102. <&clks IMX6SX_PLL4_BYPASS_SRC>;
  103. assigned-clock-rates = <0>, <0>, <24576000>;
  104. };
  105. &esai {
  106. pinctrl-names = "default";
  107. pinctrl-0 = <&pinctrl_esai>;
  108. assigned-clocks = <&clks IMX6SX_CLK_ESAI_SEL>,
  109. <&clks IMX6SX_CLK_ESAI_EXTAL>;
  110. assigned-clock-parents = <&clks IMX6SX_CLK_PLL4_AUDIO_DIV>;
  111. assigned-clock-rates = <0>, <24576000>;
  112. status = "okay";
  113. };
  114. &fec1 {
  115. pinctrl-names = "default";
  116. pinctrl-0 = <&pinctrl_enet1>;
  117. phy-mode = "rgmii-id";
  118. phy-handle = <&ethphy1>;
  119. fsl,magic-packet;
  120. status = "okay";
  121. mdio {
  122. #address-cells = <1>;
  123. #size-cells = <0>;
  124. ethphy0: ethernet-phy@0 {
  125. compatible = "ethernet-phy-ieee802.3-c22";
  126. reg = <0>;
  127. };
  128. ethphy1: ethernet-phy@1 {
  129. compatible = "ethernet-phy-ieee802.3-c22";
  130. reg = <1>;
  131. };
  132. };
  133. };
  134. &fec2 {
  135. pinctrl-names = "default";
  136. pinctrl-0 = <&pinctrl_enet2>;
  137. phy-mode = "rgmii-id";
  138. phy-handle = <&ethphy0>;
  139. fsl,magic-packet;
  140. status = "okay";
  141. };
  142. &flexcan1 {
  143. pinctrl-names = "default";
  144. pinctrl-0 = <&pinctrl_flexcan1>;
  145. xceiver-supply = <&reg_can_stby>;
  146. status = "okay";
  147. };
  148. &flexcan2 {
  149. pinctrl-names = "default";
  150. pinctrl-0 = <&pinctrl_flexcan2>;
  151. xceiver-supply = <&reg_can_stby>;
  152. status = "okay";
  153. };
  154. &uart1 {
  155. pinctrl-names = "default";
  156. pinctrl-0 = <&pinctrl_uart1>;
  157. status = "okay";
  158. };
  159. &usdhc3 {
  160. pinctrl-names = "default", "state_100mhz", "state_200mhz";
  161. pinctrl-0 = <&pinctrl_usdhc3>;
  162. pinctrl-1 = <&pinctrl_usdhc3_100mhz>;
  163. pinctrl-2 = <&pinctrl_usdhc3_200mhz>;
  164. bus-width = <8>;
  165. cd-gpios = <&gpio7 10 GPIO_ACTIVE_LOW>;
  166. wp-gpios = <&gpio3 19 GPIO_ACTIVE_HIGH>;
  167. keep-power-in-suspend;
  168. wakeup-source;
  169. vmmc-supply = <&vcc_sd3>;
  170. status = "okay";
  171. };
  172. &usdhc4 {
  173. pinctrl-names = "default";
  174. pinctrl-0 = <&pinctrl_usdhc4>;
  175. bus-width = <8>;
  176. cd-gpios = <&gpio7 11 GPIO_ACTIVE_LOW>;
  177. no-1-8-v;
  178. keep-power-in-suspend;
  179. wakeup-source;
  180. status = "okay";
  181. };
  182. &iomuxc {
  183. pinctrl_egalax_int: egalax-intgrp {
  184. fsl,pins = <
  185. MX6SX_PAD_SD4_RESET_B__GPIO6_IO_22 0x10b0
  186. >;
  187. };
  188. pinctrl_enet1: enet1grp {
  189. fsl,pins = <
  190. MX6SX_PAD_ENET1_MDIO__ENET1_MDIO 0xa0b1
  191. MX6SX_PAD_ENET1_MDC__ENET1_MDC 0xa0b1
  192. MX6SX_PAD_RGMII1_TXC__ENET1_RGMII_TXC 0xa0b9
  193. MX6SX_PAD_RGMII1_TD0__ENET1_TX_DATA_0 0xa0b1
  194. MX6SX_PAD_RGMII1_TD1__ENET1_TX_DATA_1 0xa0b1
  195. MX6SX_PAD_RGMII1_TD2__ENET1_TX_DATA_2 0xa0b1
  196. MX6SX_PAD_RGMII1_TD3__ENET1_TX_DATA_3 0xa0b1
  197. MX6SX_PAD_RGMII1_TX_CTL__ENET1_TX_EN 0xa0b1
  198. MX6SX_PAD_RGMII1_RXC__ENET1_RX_CLK 0x3081
  199. MX6SX_PAD_RGMII1_RD0__ENET1_RX_DATA_0 0x3081
  200. MX6SX_PAD_RGMII1_RD1__ENET1_RX_DATA_1 0x3081
  201. MX6SX_PAD_RGMII1_RD2__ENET1_RX_DATA_2 0x3081
  202. MX6SX_PAD_RGMII1_RD3__ENET1_RX_DATA_3 0x3081
  203. MX6SX_PAD_RGMII1_RX_CTL__ENET1_RX_EN 0x3081
  204. >;
  205. };
  206. pinctrl_enet2: enet2grp {
  207. fsl,pins = <
  208. MX6SX_PAD_RGMII2_TXC__ENET2_RGMII_TXC 0xa0b9
  209. MX6SX_PAD_RGMII2_TD0__ENET2_TX_DATA_0 0xa0b1
  210. MX6SX_PAD_RGMII2_TD1__ENET2_TX_DATA_1 0xa0b1
  211. MX6SX_PAD_RGMII2_TD2__ENET2_TX_DATA_2 0xa0b1
  212. MX6SX_PAD_RGMII2_TD3__ENET2_TX_DATA_3 0xa0b1
  213. MX6SX_PAD_RGMII2_TX_CTL__ENET2_TX_EN 0xa0b1
  214. MX6SX_PAD_RGMII2_RXC__ENET2_RX_CLK 0x3081
  215. MX6SX_PAD_RGMII2_RD0__ENET2_RX_DATA_0 0x3081
  216. MX6SX_PAD_RGMII2_RD1__ENET2_RX_DATA_1 0x3081
  217. MX6SX_PAD_RGMII2_RD2__ENET2_RX_DATA_2 0x3081
  218. MX6SX_PAD_RGMII2_RD3__ENET2_RX_DATA_3 0x3081
  219. MX6SX_PAD_RGMII2_RX_CTL__ENET2_RX_EN 0x3081
  220. >;
  221. };
  222. pinctrl_esai: esaigrp {
  223. fsl,pins = <
  224. MX6SX_PAD_CSI_DATA00__ESAI_TX_CLK 0x1b030
  225. MX6SX_PAD_CSI_DATA01__ESAI_TX_FS 0x1b030
  226. MX6SX_PAD_CSI_HSYNC__ESAI_TX0 0x1b030
  227. MX6SX_PAD_CSI_DATA04__ESAI_TX1 0x1b030
  228. MX6SX_PAD_CSI_DATA06__ESAI_TX2_RX3 0x1b030
  229. MX6SX_PAD_CSI_DATA07__ESAI_TX3_RX2 0x1b030
  230. MX6SX_PAD_CSI_DATA02__ESAI_RX_CLK 0x1b030
  231. MX6SX_PAD_CSI_DATA03__ESAI_RX_FS 0x1b030
  232. MX6SX_PAD_CSI_VSYNC__ESAI_TX5_RX0 0x1b030
  233. MX6SX_PAD_CSI_DATA05__ESAI_TX4_RX1 0x1b030
  234. >;
  235. };
  236. pinctrl_flexcan1: flexcan1grp {
  237. fsl,pins = <
  238. MX6SX_PAD_QSPI1B_DQS__CAN1_TX 0x1b020
  239. MX6SX_PAD_QSPI1A_SS1_B__CAN1_RX 0x1b020
  240. >;
  241. };
  242. pinctrl_flexcan2: flexcan2grp {
  243. fsl,pins = <
  244. MX6SX_PAD_QSPI1B_SS1_B__CAN2_RX 0x1b020
  245. MX6SX_PAD_QSPI1A_DQS__CAN2_TX 0x1b020
  246. >;
  247. };
  248. pinctrl_i2c2: i2c2grp {
  249. fsl,pins = <
  250. MX6SX_PAD_GPIO1_IO03__I2C2_SDA 0x4001b8b1
  251. MX6SX_PAD_GPIO1_IO02__I2C2_SCL 0x4001b8b1
  252. >;
  253. };
  254. pinctrl_i2c3: i2c3grp {
  255. fsl,pins = <
  256. MX6SX_PAD_KEY_ROW4__I2C3_SDA 0x4001b8b1
  257. MX6SX_PAD_KEY_COL4__I2C3_SCL 0x4001b8b1
  258. >;
  259. };
  260. pinctrl_led: ledgrp {
  261. fsl,pins = <
  262. MX6SX_PAD_CSI_PIXCLK__GPIO1_IO_24 0x17059
  263. >;
  264. };
  265. pinctrl_spdif: spdifgrp {
  266. fsl,pins = <
  267. MX6SX_PAD_ENET2_COL__SPDIF_IN 0x1b0b0
  268. >;
  269. };
  270. pinctrl_uart1: uart1grp {
  271. fsl,pins = <
  272. MX6SX_PAD_GPIO1_IO04__UART1_DCE_TX 0x1b0b1
  273. MX6SX_PAD_GPIO1_IO05__UART1_DCE_RX 0x1b0b1
  274. >;
  275. };
  276. pinctrl_usdhc3: usdhc3grp {
  277. fsl,pins = <
  278. MX6SX_PAD_SD3_CMD__USDHC3_CMD 0x17059
  279. MX6SX_PAD_SD3_CLK__USDHC3_CLK 0x10059
  280. MX6SX_PAD_SD3_DATA0__USDHC3_DATA0 0x17059
  281. MX6SX_PAD_SD3_DATA1__USDHC3_DATA1 0x17059
  282. MX6SX_PAD_SD3_DATA2__USDHC3_DATA2 0x17059
  283. MX6SX_PAD_SD3_DATA3__USDHC3_DATA3 0x17059
  284. MX6SX_PAD_SD3_DATA4__USDHC3_DATA4 0x17059
  285. MX6SX_PAD_SD3_DATA5__USDHC3_DATA5 0x17059
  286. MX6SX_PAD_SD3_DATA6__USDHC3_DATA6 0x17059
  287. MX6SX_PAD_SD3_DATA7__USDHC3_DATA7 0x17059
  288. MX6SX_PAD_KEY_COL0__GPIO2_IO_10 0x17059 /* CD */
  289. MX6SX_PAD_KEY_ROW0__GPIO2_IO_15 0x17059 /* WP */
  290. >;
  291. };
  292. pinctrl_usdhc3_100mhz: usdhc3grp-100mhz {
  293. fsl,pins = <
  294. MX6SX_PAD_SD3_CMD__USDHC3_CMD 0x170b9
  295. MX6SX_PAD_SD3_CLK__USDHC3_CLK 0x100b9
  296. MX6SX_PAD_SD3_DATA0__USDHC3_DATA0 0x170b9
  297. MX6SX_PAD_SD3_DATA1__USDHC3_DATA1 0x170b9
  298. MX6SX_PAD_SD3_DATA2__USDHC3_DATA2 0x170b9
  299. MX6SX_PAD_SD3_DATA3__USDHC3_DATA3 0x170b9
  300. MX6SX_PAD_SD3_DATA4__USDHC3_DATA4 0x170b9
  301. MX6SX_PAD_SD3_DATA5__USDHC3_DATA5 0x170b9
  302. MX6SX_PAD_SD3_DATA6__USDHC3_DATA6 0x170b9
  303. MX6SX_PAD_SD3_DATA7__USDHC3_DATA7 0x170b9
  304. >;
  305. };
  306. pinctrl_usdhc3_200mhz: usdhc3grp-200mhz {
  307. fsl,pins = <
  308. MX6SX_PAD_SD3_CMD__USDHC3_CMD 0x170f9
  309. MX6SX_PAD_SD3_CLK__USDHC3_CLK 0x100f9
  310. MX6SX_PAD_SD3_DATA0__USDHC3_DATA0 0x170f9
  311. MX6SX_PAD_SD3_DATA1__USDHC3_DATA1 0x170f9
  312. MX6SX_PAD_SD3_DATA2__USDHC3_DATA2 0x170f9
  313. MX6SX_PAD_SD3_DATA3__USDHC3_DATA3 0x170f9
  314. MX6SX_PAD_SD3_DATA4__USDHC3_DATA4 0x170f9
  315. MX6SX_PAD_SD3_DATA5__USDHC3_DATA5 0x170f9
  316. MX6SX_PAD_SD3_DATA6__USDHC3_DATA6 0x170f9
  317. MX6SX_PAD_SD3_DATA7__USDHC3_DATA7 0x170f9
  318. >;
  319. };
  320. pinctrl_usdhc4: usdhc4grp {
  321. fsl,pins = <
  322. MX6SX_PAD_SD4_CMD__USDHC4_CMD 0x17059
  323. MX6SX_PAD_SD4_CLK__USDHC4_CLK 0x10059
  324. MX6SX_PAD_SD4_DATA0__USDHC4_DATA0 0x17059
  325. MX6SX_PAD_SD4_DATA1__USDHC4_DATA1 0x17059
  326. MX6SX_PAD_SD4_DATA2__USDHC4_DATA2 0x17059
  327. MX6SX_PAD_SD4_DATA3__USDHC4_DATA3 0x17059
  328. MX6SX_PAD_SD4_DATA7__GPIO6_IO_21 0x17059 /* CD */
  329. MX6SX_PAD_SD4_DATA6__GPIO6_IO_20 0x17059 /* WP */
  330. >;
  331. };
  332. pinctrl_vcc_sd3: vccsd3grp {
  333. fsl,pins = <
  334. MX6SX_PAD_KEY_COL1__GPIO2_IO_11 0x17059
  335. >;
  336. };
  337. pinctrl_wdog: wdoggrp {
  338. fsl,pins = <
  339. MX6SX_PAD_GPIO1_IO13__WDOG1_WDOG_ANY 0x30b0
  340. >;
  341. };
  342. };
  343. &i2c2 {
  344. clock-frequency = <100000>;
  345. pinctrl-names = "default";
  346. pinctrl-0 = <&pinctrl_i2c2>;
  347. status = "okay";
  348. cs42888: cs42888@48 {
  349. compatible = "cirrus,cs42888";
  350. reg = <0x48>;
  351. clocks = <&anaclk2 0>;
  352. clock-names = "mclk";
  353. VA-supply = <&reg_cs42888>;
  354. VD-supply = <&reg_cs42888>;
  355. VLS-supply = <&reg_cs42888>;
  356. VLC-supply = <&reg_cs42888>;
  357. };
  358. touchscreen@4 {
  359. compatible = "eeti,egalax_ts";
  360. reg = <0x04>;
  361. pinctrl-names = "default";
  362. pinctrl-0 = <&pinctrl_egalax_int>;
  363. interrupt-parent = <&gpio6>;
  364. interrupts = <22 IRQ_TYPE_EDGE_FALLING>;
  365. wakeup-gpios = <&gpio6 22 GPIO_ACTIVE_HIGH>;
  366. };
  367. pfuze100: pmic@8 {
  368. compatible = "fsl,pfuze100";
  369. reg = <0x08>;
  370. regulators {
  371. sw1a_reg: sw1ab {
  372. regulator-min-microvolt = <300000>;
  373. regulator-max-microvolt = <1875000>;
  374. regulator-boot-on;
  375. regulator-always-on;
  376. regulator-ramp-delay = <6250>;
  377. };
  378. sw1c_reg: sw1c {
  379. regulator-min-microvolt = <300000>;
  380. regulator-max-microvolt = <1875000>;
  381. regulator-boot-on;
  382. regulator-always-on;
  383. regulator-ramp-delay = <6250>;
  384. };
  385. sw2_reg: sw2 {
  386. regulator-min-microvolt = <800000>;
  387. regulator-max-microvolt = <3300000>;
  388. regulator-boot-on;
  389. regulator-always-on;
  390. };
  391. sw3a_reg: sw3a {
  392. regulator-min-microvolt = <400000>;
  393. regulator-max-microvolt = <1975000>;
  394. regulator-boot-on;
  395. regulator-always-on;
  396. };
  397. sw3b_reg: sw3b {
  398. regulator-min-microvolt = <400000>;
  399. regulator-max-microvolt = <1975000>;
  400. regulator-boot-on;
  401. regulator-always-on;
  402. };
  403. sw4_reg: sw4 {
  404. regulator-min-microvolt = <800000>;
  405. regulator-max-microvolt = <3300000>;
  406. regulator-always-on;
  407. };
  408. swbst_reg: swbst {
  409. regulator-min-microvolt = <5000000>;
  410. regulator-max-microvolt = <5150000>;
  411. };
  412. snvs_reg: vsnvs {
  413. regulator-min-microvolt = <1000000>;
  414. regulator-max-microvolt = <3000000>;
  415. regulator-boot-on;
  416. regulator-always-on;
  417. };
  418. vref_reg: vrefddr {
  419. regulator-boot-on;
  420. regulator-always-on;
  421. };
  422. vgen1_reg: vgen1 {
  423. regulator-min-microvolt = <800000>;
  424. regulator-max-microvolt = <1550000>;
  425. regulator-always-on;
  426. };
  427. vgen2_reg: vgen2 {
  428. regulator-min-microvolt = <800000>;
  429. regulator-max-microvolt = <1550000>;
  430. };
  431. vgen3_reg: vgen3 {
  432. regulator-min-microvolt = <1800000>;
  433. regulator-max-microvolt = <3300000>;
  434. regulator-always-on;
  435. };
  436. vgen4_reg: vgen4 {
  437. regulator-min-microvolt = <1800000>;
  438. regulator-max-microvolt = <3300000>;
  439. regulator-always-on;
  440. };
  441. vgen5_reg: vgen5 {
  442. regulator-min-microvolt = <1800000>;
  443. regulator-max-microvolt = <3300000>;
  444. regulator-always-on;
  445. };
  446. vgen6_reg: vgen6 {
  447. regulator-min-microvolt = <1800000>;
  448. regulator-max-microvolt = <3300000>;
  449. regulator-always-on;
  450. };
  451. };
  452. };
  453. max7322: gpio@68 {
  454. compatible = "maxim,max7322";
  455. reg = <0x68>;
  456. gpio-controller;
  457. #gpio-cells = <2>;
  458. };
  459. };
  460. &i2c3 {
  461. clock-frequency = <100000>;
  462. pinctrl-names = "default";
  463. pinctrl-0 = <&pinctrl_i2c3>;
  464. status = "okay";
  465. max7310_a: gpio@30 {
  466. compatible = "maxim,max7310";
  467. reg = <0x30>;
  468. gpio-controller;
  469. #gpio-cells = <2>;
  470. };
  471. max7310_b: gpio@32 {
  472. compatible = "maxim,max7310";
  473. reg = <0x32>;
  474. gpio-controller;
  475. #gpio-cells = <2>;
  476. };
  477. };
  478. &spdif {
  479. pinctrl-names = "default";
  480. pinctrl-0 = <&pinctrl_spdif>;
  481. assigned-clocks = <&clks IMX6SX_CLK_SPDIF_PODF>;
  482. assigned-clock-rates = <24576000>;
  483. status = "okay";
  484. };
  485. &wdog1 {
  486. pinctrl-names = "default";
  487. pinctrl-0 = <&pinctrl_wdog>;
  488. fsl,ext-reset-output;
  489. };