imx6sll-kobo-librah2o.dts 8.6 KB

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  1. // SPDX-License-Identifier: (GPL-2.0)
  2. /*
  3. * Device tree for the Kobo Libra H2O ebook reader
  4. *
  5. * Name on mainboard is: 37NB-E70K0M+6A3
  6. * Serials start with: E70K02 (a number also seen in
  7. * vendor kernel sources)
  8. *
  9. * This mainboard seems to be equipped with different SoCs.
  10. * In the Kobo Libra H2O ebook reader it is an i.MX6SLL
  11. *
  12. * Copyright 2021 Andreas Kemnade
  13. * based on works
  14. * Copyright 2016 Freescale Semiconductor, Inc.
  15. */
  16. /dts-v1/;
  17. #include <dt-bindings/input/input.h>
  18. #include <dt-bindings/gpio/gpio.h>
  19. #include "imx6sll.dtsi"
  20. #include "e70k02.dtsi"
  21. / {
  22. model = "Kobo Libra H2O";
  23. compatible = "kobo,librah2o", "fsl,imx6sll";
  24. };
  25. &clks {
  26. assigned-clocks = <&clks IMX6SLL_CLK_PLL4_AUDIO_DIV>;
  27. assigned-clock-rates = <393216000>;
  28. };
  29. &cpu0 {
  30. arm-supply = <&dcdc3_reg>;
  31. soc-supply = <&dcdc1_reg>;
  32. };
  33. &gpio_keys {
  34. pinctrl-names = "default";
  35. pinctrl-0 = <&pinctrl_gpio_keys>;
  36. };
  37. &i2c1 {
  38. pinctrl-names = "default","sleep";
  39. pinctrl-0 = <&pinctrl_i2c1>;
  40. pinctrl-1 = <&pinctrl_i2c1_sleep>;
  41. };
  42. &i2c2 {
  43. pinctrl-names = "default","sleep";
  44. pinctrl-0 = <&pinctrl_i2c2>;
  45. pinctrl-1 = <&pinctrl_i2c2_sleep>;
  46. };
  47. &i2c3 {
  48. pinctrl-names = "default";
  49. pinctrl-0 = <&pinctrl_i2c3>;
  50. };
  51. &iomuxc {
  52. pinctrl-names = "default";
  53. pinctrl-0 = <&pinctrl_hog>;
  54. pinctrl_gpio_keys: gpio-keysgrp {
  55. fsl,pins = <
  56. MX6SLL_PAD_GPIO4_IO25__GPIO4_IO25 0x17059 /* PWR_SW */
  57. MX6SLL_PAD_GPIO4_IO23__GPIO4_IO23 0x17059 /* HALL_EN */
  58. MX6SLL_PAD_KEY_COL4__GPIO4_IO00 0x17059 /* PAGE_UP */
  59. MX6SLL_PAD_KEY_COL5__GPIO4_IO02 0x17059 /* PAGE_DOWN */
  60. >;
  61. };
  62. pinctrl_hog: hoggrp {
  63. fsl,pins = <
  64. MX6SLL_PAD_LCD_DATA01__GPIO2_IO21 0x79
  65. MX6SLL_PAD_LCD_DATA04__GPIO2_IO24 0x79
  66. MX6SLL_PAD_LCD_DATA05__GPIO2_IO25 0x79
  67. MX6SLL_PAD_LCD_DATA06__GPIO2_IO26 0x79
  68. MX6SLL_PAD_LCD_DATA07__GPIO2_IO27 0x79
  69. MX6SLL_PAD_LCD_DATA08__GPIO2_IO28 0x79
  70. MX6SLL_PAD_LCD_DATA09__GPIO2_IO29 0x79
  71. MX6SLL_PAD_LCD_DATA10__GPIO2_IO30 0x79
  72. MX6SLL_PAD_LCD_DATA11__GPIO2_IO31 0x79
  73. MX6SLL_PAD_LCD_DATA12__GPIO3_IO00 0x79
  74. MX6SLL_PAD_LCD_DATA13__GPIO3_IO01 0x79
  75. MX6SLL_PAD_LCD_DATA14__GPIO3_IO02 0x79
  76. MX6SLL_PAD_LCD_DATA15__GPIO3_IO03 0x79
  77. MX6SLL_PAD_LCD_DATA16__GPIO3_IO04 0x79
  78. MX6SLL_PAD_LCD_DATA17__GPIO3_IO05 0x79
  79. MX6SLL_PAD_LCD_DATA18__GPIO3_IO06 0x79
  80. MX6SLL_PAD_LCD_DATA19__GPIO3_IO07 0x79
  81. MX6SLL_PAD_LCD_DATA20__GPIO3_IO08 0x79
  82. MX6SLL_PAD_LCD_DATA21__GPIO3_IO09 0x79
  83. MX6SLL_PAD_LCD_DATA22__GPIO3_IO10 0x79
  84. MX6SLL_PAD_LCD_DATA23__GPIO3_IO11 0x79
  85. MX6SLL_PAD_LCD_CLK__GPIO2_IO15 0x79
  86. MX6SLL_PAD_LCD_ENABLE__GPIO2_IO16 0x79
  87. MX6SLL_PAD_LCD_HSYNC__GPIO2_IO17 0x79
  88. MX6SLL_PAD_LCD_VSYNC__GPIO2_IO18 0x79
  89. MX6SLL_PAD_LCD_RESET__GPIO2_IO19 0x79
  90. MX6SLL_PAD_GPIO4_IO21__GPIO4_IO21 0x79
  91. MX6SLL_PAD_GPIO4_IO26__GPIO4_IO26 0x79
  92. MX6SLL_PAD_KEY_COL3__GPIO3_IO30 0x79
  93. MX6SLL_PAD_KEY_ROW7__GPIO4_IO07 0x79
  94. MX6SLL_PAD_ECSPI2_MOSI__GPIO4_IO13 0x79
  95. >;
  96. };
  97. pinctrl_i2c1: i2c1grp {
  98. fsl,pins = <
  99. MX6SLL_PAD_I2C1_SCL__I2C1_SCL 0x4001f8b1
  100. MX6SLL_PAD_I2C1_SDA__I2C1_SDA 0x4001f8b1
  101. >;
  102. };
  103. pinctrl_i2c1_sleep: i2c1grp-sleep {
  104. fsl,pins = <
  105. MX6SLL_PAD_I2C1_SCL__I2C1_SCL 0x400108b1
  106. MX6SLL_PAD_I2C1_SDA__I2C1_SDA 0x400108b1
  107. >;
  108. };
  109. pinctrl_i2c2: i2c2grp {
  110. fsl,pins = <
  111. MX6SLL_PAD_I2C2_SCL__I2C2_SCL 0x4001f8b1
  112. MX6SLL_PAD_I2C2_SDA__I2C2_SDA 0x4001f8b1
  113. >;
  114. };
  115. pinctrl_i2c2_sleep: i2c2grp-sleep {
  116. fsl,pins = <
  117. MX6SLL_PAD_I2C2_SCL__I2C2_SCL 0x400108b1
  118. MX6SLL_PAD_I2C2_SDA__I2C2_SDA 0x400108b1
  119. >;
  120. };
  121. pinctrl_i2c3: i2c3grp {
  122. fsl,pins = <
  123. MX6SLL_PAD_REF_CLK_24M__I2C3_SCL 0x4001f8b1
  124. MX6SLL_PAD_REF_CLK_32K__I2C3_SDA 0x4001f8b1
  125. >;
  126. };
  127. pinctrl_led: ledgrp {
  128. fsl,pins = <
  129. MX6SLL_PAD_GPIO4_IO17__GPIO4_IO17 0x10059
  130. >;
  131. };
  132. pinctrl_lm3630a_bl_gpio: lm3630a-bl-gpiogrp {
  133. fsl,pins = <
  134. MX6SLL_PAD_EPDC_PWR_CTRL3__GPIO2_IO10 0x10059 /* HWEN */
  135. >;
  136. };
  137. pinctrl_ricoh_gpio: ricoh-gpiogrp {
  138. fsl,pins = <
  139. MX6SLL_PAD_GPIO4_IO20__GPIO4_IO20 0x1b8b1 /* ricoh619 chg */
  140. MX6SLL_PAD_GPIO4_IO19__GPIO4_IO19 0x1b8b1 /* ricoh619 irq */
  141. MX6SLL_PAD_KEY_COL2__GPIO3_IO28 0x1b8b1 /* ricoh619 bat_low_int */
  142. >;
  143. };
  144. pinctrl_uart1: uart1grp {
  145. fsl,pins = <
  146. MX6SLL_PAD_UART1_TXD__UART1_DCE_TX 0x1b0b1
  147. MX6SLL_PAD_UART1_RXD__UART1_DCE_RX 0x1b0b1
  148. >;
  149. };
  150. pinctrl_usbotg1: usbotg1grp {
  151. fsl,pins = <
  152. MX6SLL_PAD_EPDC_PWR_COM__USB_OTG1_ID 0x17059
  153. >;
  154. };
  155. pinctrl_usdhc1: usdhc1grp {
  156. fsl,pins = <
  157. MX6SLL_PAD_SD1_CMD__SD1_CMD 0x17059
  158. MX6SLL_PAD_SD1_CLK__SD1_CLK 0x17059
  159. MX6SLL_PAD_SD1_DATA0__SD1_DATA0 0x17059
  160. MX6SLL_PAD_SD1_DATA1__SD1_DATA1 0x17059
  161. MX6SLL_PAD_SD1_DATA2__SD1_DATA2 0x17059
  162. MX6SLL_PAD_SD1_DATA3__SD1_DATA3 0x17059
  163. MX6SLL_PAD_SD1_DATA4__SD1_DATA4 0x17059
  164. MX6SLL_PAD_SD1_DATA5__SD1_DATA5 0x17059
  165. MX6SLL_PAD_SD1_DATA6__SD1_DATA6 0x17059
  166. MX6SLL_PAD_SD1_DATA7__SD1_DATA7 0x17059
  167. >;
  168. };
  169. pinctrl_usdhc1_100mhz: usdhc1-100mhzgrp {
  170. fsl,pins = <
  171. MX6SLL_PAD_SD1_CMD__SD1_CMD 0x170b9
  172. MX6SLL_PAD_SD1_CLK__SD1_CLK 0x170b9
  173. MX6SLL_PAD_SD1_DATA0__SD1_DATA0 0x170b9
  174. MX6SLL_PAD_SD1_DATA1__SD1_DATA1 0x170b9
  175. MX6SLL_PAD_SD1_DATA2__SD1_DATA2 0x170b9
  176. MX6SLL_PAD_SD1_DATA3__SD1_DATA3 0x170b9
  177. MX6SLL_PAD_SD1_DATA4__SD1_DATA4 0x170b9
  178. MX6SLL_PAD_SD1_DATA5__SD1_DATA5 0x170b9
  179. MX6SLL_PAD_SD1_DATA6__SD1_DATA6 0x170b9
  180. MX6SLL_PAD_SD1_DATA7__SD1_DATA7 0x170b9
  181. >;
  182. };
  183. pinctrl_usdhc1_200mhz: usdhc1-200mhzgrp {
  184. fsl,pins = <
  185. MX6SLL_PAD_SD1_CMD__SD1_CMD 0x170f9
  186. MX6SLL_PAD_SD1_CLK__SD1_CLK 0x170f9
  187. MX6SLL_PAD_SD1_DATA0__SD1_DATA0 0x170f9
  188. MX6SLL_PAD_SD1_DATA1__SD1_DATA1 0x170f9
  189. MX6SLL_PAD_SD1_DATA2__SD1_DATA2 0x170f9
  190. MX6SLL_PAD_SD1_DATA3__SD1_DATA3 0x170f9
  191. MX6SLL_PAD_SD1_DATA4__SD1_DATA4 0x170b9
  192. MX6SLL_PAD_SD1_DATA5__SD1_DATA5 0x170b9
  193. MX6SLL_PAD_SD1_DATA6__SD1_DATA6 0x170b9
  194. MX6SLL_PAD_SD1_DATA7__SD1_DATA7 0x170b9
  195. >;
  196. };
  197. pinctrl_usdhc1_sleep: usdhc1-sleepgrp {
  198. fsl,pins = <
  199. MX6SLL_PAD_SD1_CMD__SD1_CMD 0x10059
  200. MX6SLL_PAD_SD1_CLK__SD1_CLK 0x10059
  201. MX6SLL_PAD_SD1_DATA0__SD1_DATA0 0x10059
  202. MX6SLL_PAD_SD1_DATA1__SD1_DATA1 0x10059
  203. MX6SLL_PAD_SD1_DATA2__SD1_DATA2 0x10059
  204. MX6SLL_PAD_SD1_DATA3__SD1_DATA3 0x10059
  205. MX6SLL_PAD_SD1_DATA4__SD1_DATA4 0x10059
  206. MX6SLL_PAD_SD1_DATA5__SD1_DATA5 0x10059
  207. MX6SLL_PAD_SD1_DATA6__SD1_DATA6 0x10059
  208. MX6SLL_PAD_SD1_DATA7__SD1_DATA7 0x10059
  209. >;
  210. };
  211. pinctrl_usdhc3: usdhc3grp {
  212. fsl,pins = <
  213. MX6SLL_PAD_SD3_CMD__SD3_CMD 0x11059
  214. MX6SLL_PAD_SD3_CLK__SD3_CLK 0x11059
  215. MX6SLL_PAD_SD3_DATA0__SD3_DATA0 0x11059
  216. MX6SLL_PAD_SD3_DATA1__SD3_DATA1 0x11059
  217. MX6SLL_PAD_SD3_DATA2__SD3_DATA2 0x11059
  218. MX6SLL_PAD_SD3_DATA3__SD3_DATA3 0x11059
  219. >;
  220. };
  221. pinctrl_usdhc3_100mhz: usdhc3-100mhzgrp {
  222. fsl,pins = <
  223. MX6SLL_PAD_SD3_CMD__SD3_CMD 0x170b9
  224. MX6SLL_PAD_SD3_CLK__SD3_CLK 0x170b9
  225. MX6SLL_PAD_SD3_DATA0__SD3_DATA0 0x170b9
  226. MX6SLL_PAD_SD3_DATA1__SD3_DATA1 0x170b9
  227. MX6SLL_PAD_SD3_DATA2__SD3_DATA2 0x170b9
  228. MX6SLL_PAD_SD3_DATA3__SD3_DATA3 0x170b9
  229. >;
  230. };
  231. pinctrl_usdhc3_200mhz: usdhc3-200mhzgrp {
  232. fsl,pins = <
  233. MX6SLL_PAD_SD3_CMD__SD3_CMD 0x170f9
  234. MX6SLL_PAD_SD3_CLK__SD3_CLK 0x170f9
  235. MX6SLL_PAD_SD3_DATA0__SD3_DATA0 0x170f9
  236. MX6SLL_PAD_SD3_DATA1__SD3_DATA1 0x170f9
  237. MX6SLL_PAD_SD3_DATA2__SD3_DATA2 0x170f9
  238. MX6SLL_PAD_SD3_DATA3__SD3_DATA3 0x170f9
  239. >;
  240. };
  241. pinctrl_usdhc3_sleep: usdhc3-sleepgrp {
  242. fsl,pins = <
  243. MX6SLL_PAD_SD3_CMD__GPIO5_IO21 0x100c1
  244. MX6SLL_PAD_SD3_CLK__GPIO5_IO18 0x100c1
  245. MX6SLL_PAD_SD3_DATA0__GPIO5_IO19 0x100c1
  246. MX6SLL_PAD_SD3_DATA1__GPIO5_IO20 0x100c1
  247. MX6SLL_PAD_SD3_DATA2__GPIO5_IO16 0x100c1
  248. MX6SLL_PAD_SD3_DATA3__GPIO5_IO17 0x100c1
  249. >;
  250. };
  251. pinctrl_wifi_power: wifi-powergrp {
  252. fsl,pins = <
  253. MX6SLL_PAD_SD2_DATA6__GPIO4_IO29 0x10059 /* WIFI_3V3_ON */
  254. >;
  255. };
  256. pinctrl_wifi_reset: wifi-resetgrp {
  257. fsl,pins = <
  258. MX6SLL_PAD_SD2_DATA7__GPIO5_IO00 0x10059 /* WIFI_RST */
  259. >;
  260. };
  261. };
  262. &leds {
  263. pinctrl-names = "default";
  264. pinctrl-0 = <&pinctrl_led>;
  265. };
  266. &lm3630a {
  267. pinctrl-names = "default";
  268. pinctrl-0 = <&pinctrl_lm3630a_bl_gpio>;
  269. };
  270. &reg_wifi {
  271. pinctrl-names = "default";
  272. pinctrl-0 = <&pinctrl_wifi_power>;
  273. };
  274. &ricoh619 {
  275. pinctrl-names = "default";
  276. pinctrl-0 = <&pinctrl_ricoh_gpio>;
  277. };
  278. &uart1 {
  279. pinctrl-names = "default";
  280. pinctrl-0 = <&pinctrl_uart1>;
  281. };
  282. &usdhc1 {
  283. pinctrl-names = "default", "state_100mhz", "state_200mhz","sleep";
  284. pinctrl-0 = <&pinctrl_usdhc1>;
  285. pinctrl-1 = <&pinctrl_usdhc1_100mhz>;
  286. pinctrl-2 = <&pinctrl_usdhc1_200mhz>;
  287. pinctrl-3 = <&pinctrl_usdhc1_sleep>;
  288. };
  289. &usdhc3 {
  290. pinctrl-names = "default", "state_100mhz", "state_200mhz","sleep";
  291. pinctrl-0 = <&pinctrl_usdhc3>;
  292. pinctrl-1 = <&pinctrl_usdhc3_100mhz>;
  293. pinctrl-2 = <&pinctrl_usdhc3_200mhz>;
  294. pinctrl-3 = <&pinctrl_usdhc3_sleep>;
  295. };
  296. &wifi_pwrseq {
  297. pinctrl-names = "default";
  298. pinctrl-0 = <&pinctrl_wifi_reset>;
  299. };