imx6qdl-var-dart.dtsi 10 KB

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  1. // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
  2. /*
  3. * Support for Variscite DART-MX6 Module
  4. *
  5. * Copyright 2017 BayLibre, SAS
  6. * Author: Neil Armstrong <[email protected]>
  7. */
  8. #include <dt-bindings/gpio/gpio.h>
  9. #include <dt-bindings/sound/fsl-imx-audmux.h>
  10. / {
  11. memory@10000000 {
  12. device_type = "memory";
  13. reg = <0x10000000 0x40000000>;
  14. };
  15. reg_3p3v: regulator-3p3v {
  16. compatible = "regulator-fixed";
  17. regulator-name = "3P3V";
  18. regulator-min-microvolt = <3300000>;
  19. regulator-max-microvolt = <3300000>;
  20. regulator-always-on;
  21. };
  22. reg_wl18xx_vmmc: regulator-wl18xx {
  23. compatible = "regulator-fixed";
  24. regulator-name = "vwl1807";
  25. regulator-min-microvolt = <1800000>;
  26. regulator-max-microvolt = <1800000>;
  27. gpio = <&gpio7 8 GPIO_ACTIVE_HIGH>;
  28. enable-active-high;
  29. startup-delay-us = <70000>;
  30. };
  31. };
  32. &audmux {
  33. pinctrl-names = "default";
  34. pinctrl-0 = <&pinctrl_audmux>;
  35. status = "okay";
  36. ssi2 {
  37. fsl,audmux-port = <1>;
  38. fsl,port-config = <
  39. (IMX_AUDMUX_V2_PTCR_SYN |
  40. IMX_AUDMUX_V2_PTCR_TFSDIR |
  41. IMX_AUDMUX_V2_PTCR_TFSEL(2) |
  42. IMX_AUDMUX_V2_PTCR_TCLKDIR |
  43. IMX_AUDMUX_V2_PTCR_TCSEL(2))
  44. IMX_AUDMUX_V2_PDCR_RXDSEL(2)
  45. >;
  46. };
  47. aud3 {
  48. fsl,audmux-port = <2>;
  49. fsl,port-config = <
  50. IMX_AUDMUX_V2_PTCR_SYN
  51. IMX_AUDMUX_V2_PDCR_RXDSEL(1)
  52. >;
  53. };
  54. };
  55. &can1 {
  56. pinctrl-names = "default";
  57. pinctrl-0 = <&pinctrl_flexcan1>;
  58. status = "disabled";
  59. };
  60. &can2 {
  61. pinctrl-names = "default";
  62. pinctrl-0 = <&pinctrl_flexcan2>;
  63. status = "disabled";
  64. };
  65. &ecspi1 {
  66. pinctrl-names = "default";
  67. pinctrl-0 = <&pinctrl_ecspi1>;
  68. status = "disabled";
  69. };
  70. &fec {
  71. pinctrl-names = "default";
  72. pinctrl-0 = <&pinctrl_enet>;
  73. phy-mode = "rgmii";
  74. status = "disabled";
  75. };
  76. &hdmi {
  77. pinctrl-names = "default";
  78. pinctrl-0 = <&pinctrl_hdmicec>;
  79. ddc-i2c-bus = <&i2c1>;
  80. status = "disabled";
  81. };
  82. &i2c1 {
  83. pinctrl-names = "default";
  84. pinctrl-0 = <&pinctrl_i2c1>;
  85. status = "disabled";
  86. };
  87. &i2c2 {
  88. clock-frequency = <100000>;
  89. pinctrl-names = "default";
  90. pinctrl-0 = <&pinctrl_i2c2>;
  91. status = "okay";
  92. pmic@8 {
  93. pinctrl-names = "default";
  94. pinctrl-0 = <&pinctrl_pmic>;
  95. compatible = "fsl,pfuze100";
  96. reg = <0x08>;
  97. regulators {
  98. sw1a_reg: sw1ab {
  99. regulator-min-microvolt = <300000>;
  100. regulator-max-microvolt = <1875000>;
  101. regulator-boot-on;
  102. regulator-always-on;
  103. regulator-ramp-delay = <6250>;
  104. };
  105. sw1c_reg: sw1c {
  106. regulator-min-microvolt = <300000>;
  107. regulator-max-microvolt = <1875000>;
  108. regulator-boot-on;
  109. regulator-always-on;
  110. regulator-ramp-delay = <6250>;
  111. };
  112. sw2_reg: sw2 {
  113. regulator-min-microvolt = <800000>;
  114. regulator-max-microvolt = <3300000>;
  115. regulator-boot-on;
  116. regulator-always-on;
  117. };
  118. sw3a_reg: sw3a {
  119. regulator-min-microvolt = <800000>;
  120. regulator-max-microvolt = <3950000>;
  121. regulator-boot-on;
  122. regulator-always-on;
  123. };
  124. sw3b_reg: sw3b {
  125. regulator-min-microvolt = <800000>;
  126. regulator-max-microvolt = <3950000>;
  127. regulator-boot-on;
  128. regulator-always-on;
  129. };
  130. sw4_reg: sw4 {
  131. regulator-min-microvolt = <800000>;
  132. regulator-max-microvolt = <3950000>;
  133. };
  134. snvs_reg: vsnvs {
  135. regulator-min-microvolt = <1200000>;
  136. regulator-max-microvolt = <3000000>;
  137. regulator-boot-on;
  138. regulator-always-on;
  139. };
  140. vref_reg: vrefddr {
  141. regulator-boot-on;
  142. regulator-always-on;
  143. };
  144. vgen6_reg: vgen6 {
  145. regulator-min-microvolt = <2800000>;
  146. regulator-max-microvolt = <2800000>;
  147. regulator-always-on;
  148. regulator-boot-on;
  149. };
  150. };
  151. };
  152. tlv320aic3106: codec@1b {
  153. compatible = "ti,tlv320aic3106";
  154. reg = <0x1b>;
  155. #sound-dai-cells = <0>;
  156. DRVDD-supply = <&reg_3p3v>;
  157. AVDD-supply = <&reg_3p3v>;
  158. IOVDD-supply = <&reg_3p3v>;
  159. DVDD-supply = <&reg_3p3v>;
  160. ai3x-ocmv = <0>;
  161. reset-gpios = <&gpio5 5 GPIO_ACTIVE_LOW>;
  162. };
  163. };
  164. &i2c3 {
  165. pinctrl-names = "default";
  166. pinctrl-0 = <&pinctrl_i2c3>;
  167. status = "disabled";
  168. };
  169. &iomuxc {
  170. pinctrl_audmux: audmux {
  171. fsl,pins = <
  172. MX6QDL_PAD_CSI0_DAT7__AUD3_RXD 0x130b0
  173. MX6QDL_PAD_CSI0_DAT4__AUD3_TXC 0x130b0
  174. MX6QDL_PAD_CSI0_DAT5__AUD3_TXD 0x110b0
  175. MX6QDL_PAD_CSI0_DAT6__AUD3_TXFS 0x130b0
  176. /* Audio Clock */
  177. MX6QDL_PAD_GPIO_0__CCM_CLKO1 0x130b0
  178. >;
  179. };
  180. pinctrl_bt: bt {
  181. fsl,pins = <
  182. /* Bluetooth enable */
  183. MX6QDL_PAD_SD3_DAT6__GPIO6_IO18 0x1b0b1
  184. /* Bluetooth Slow Clock */
  185. MX6QDL_PAD_ENET_RXD0__OSC32K_32K_OUT 0x000b0
  186. >;
  187. };
  188. pinctrl_ecspi1: ecspi1grp {
  189. fsl,pins = <
  190. MX6QDL_PAD_KEY_COL1__ECSPI1_MISO 0x100b1
  191. MX6QDL_PAD_KEY_ROW0__ECSPI1_MOSI 0x100b1
  192. MX6QDL_PAD_KEY_COL0__ECSPI1_SCLK 0x100b1
  193. /* SPI1 CS0 */
  194. MX6QDL_PAD_KEY_ROW1__GPIO4_IO09 0x1b0b0
  195. /* SPI1 CS1 */
  196. MX6QDL_PAD_KEY_COL2__GPIO4_IO10 0x1b0b0
  197. >;
  198. };
  199. pinctrl_enet: enetgrp {
  200. fsl,pins = <
  201. MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x100b0
  202. MX6QDL_PAD_ENET_MDC__ENET_MDC 0x100b0
  203. MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x10030
  204. MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x10030
  205. MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x10030
  206. MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x10030
  207. MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x10030
  208. MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x10030
  209. MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x100b0
  210. MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b030
  211. MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b030
  212. MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b030
  213. MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b030
  214. MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b030
  215. MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b030
  216. >;
  217. };
  218. pinctrl_flexcan1: flexcan1grp {
  219. fsl,pins = <
  220. MX6QDL_PAD_GPIO_7__FLEXCAN1_TX 0x1b0b0
  221. MX6QDL_PAD_GPIO_8__FLEXCAN1_RX 0x1b0b0
  222. >;
  223. };
  224. pinctrl_flexcan2: flexcan2grp {
  225. fsl,pins = <
  226. MX6QDL_PAD_KEY_COL4__FLEXCAN2_TX 0x1b0b0
  227. MX6QDL_PAD_KEY_ROW4__FLEXCAN2_RX 0x1b0b0
  228. >;
  229. };
  230. pinctrl_hdmicec: hdmicecgrp {
  231. fsl,pins = <
  232. MX6QDL_PAD_KEY_ROW2__HDMI_TX_CEC_LINE 0x1f8b0
  233. >;
  234. };
  235. pinctrl_i2c1: i2c1grp {
  236. fsl,pins = <
  237. MX6QDL_PAD_CSI0_DAT8__I2C1_SDA 0x4001b8b1
  238. MX6QDL_PAD_CSI0_DAT9__I2C1_SCL 0x4001b8b1
  239. >;
  240. };
  241. pinctrl_i2c2: i2c2grp {
  242. fsl,pins = <
  243. MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1
  244. MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1
  245. >;
  246. };
  247. pinctrl_i2c3: i2c3grp {
  248. fsl,pins = <
  249. MX6QDL_PAD_GPIO_5__I2C3_SCL 0x4001b8b1
  250. MX6QDL_PAD_GPIO_16__I2C3_SDA 0x4001b8b1
  251. >;
  252. };
  253. pinctrl_pmic: pmicgrp {
  254. fsl,pins = <
  255. /* PMIC INT */
  256. MX6QDL_PAD_GPIO_17__GPIO7_IO12 0x1b0b1
  257. >;
  258. };
  259. pinctrl_pwm2: pwm2grp {
  260. fsl,pins = <
  261. MX6QDL_PAD_DISP0_DAT9__PWM2_OUT 0x1b0b1
  262. >;
  263. };
  264. pinctrl_uart1: uart1grp {
  265. fsl,pins = <
  266. MX6QDL_PAD_CSI0_DAT11__UART1_RX_DATA 0x1b0b1
  267. MX6QDL_PAD_CSI0_DAT10__UART1_TX_DATA 0x1b0b1
  268. >;
  269. };
  270. pinctrl_uart2: uart2grp {
  271. fsl,pins = <
  272. MX6QDL_PAD_SD3_DAT4__UART2_RX_DATA 0x1b0b1
  273. MX6QDL_PAD_SD3_DAT5__UART2_TX_DATA 0x1b0b1
  274. MX6QDL_PAD_SD4_DAT6__UART2_CTS_B 0x1b0b1
  275. MX6QDL_PAD_SD4_DAT5__UART2_RTS_B 0x1b0b1
  276. >;
  277. };
  278. pinctrl_uart3: uart3grp {
  279. fsl,pins = <
  280. MX6QDL_PAD_EIM_D25__UART3_RX_DATA 0x1b0b1
  281. MX6QDL_PAD_EIM_D24__UART3_TX_DATA 0x1b0b1
  282. MX6QDL_PAD_EIM_D23__UART3_CTS_B 0x1b0b1
  283. MX6QDL_PAD_EIM_EB3__UART3_RTS_B 0x1b0b1
  284. >;
  285. };
  286. pinctrl_usbotg: usbotggrp {
  287. fsl,pins = <
  288. MX6QDL_PAD_ENET_RX_ER__USB_OTG_ID 0x17059
  289. >;
  290. };
  291. pinctrl_usdhc1: usdhc1grp {
  292. fsl,pins = <
  293. MX6QDL_PAD_SD1_CMD__SD1_CMD 0x17059
  294. MX6QDL_PAD_SD1_CLK__SD1_CLK 0x10059
  295. MX6QDL_PAD_SD1_DAT0__SD1_DATA0 0x17059
  296. MX6QDL_PAD_SD1_DAT1__SD1_DATA1 0x17059
  297. MX6QDL_PAD_SD1_DAT2__SD1_DATA2 0x17059
  298. MX6QDL_PAD_SD1_DAT3__SD1_DATA3 0x17059
  299. /* WL_EN */
  300. MX6QDL_PAD_SD3_DAT7__GPIO6_IO17 0x17071
  301. /* WL_IRQ */
  302. MX6QDL_PAD_SD3_RST__GPIO7_IO08 0x17071
  303. >;
  304. };
  305. pinctrl_usdhc1_100mhz: usdhc1grp100mhz {
  306. fsl,pins = <
  307. MX6QDL_PAD_SD1_CMD__SD1_CMD 0x170B9
  308. MX6QDL_PAD_SD1_CLK__SD1_CLK 0x100B9
  309. MX6QDL_PAD_SD1_DAT0__SD1_DATA0 0x170B9
  310. MX6QDL_PAD_SD1_DAT1__SD1_DATA1 0x170B9
  311. MX6QDL_PAD_SD1_DAT2__SD1_DATA2 0x170B9
  312. MX6QDL_PAD_SD1_DAT3__SD1_DATA3 0x170B9
  313. >;
  314. };
  315. pinctrl_usdhc1_200mhz: usdhc1grp200mhz {
  316. fsl,pins = <
  317. MX6QDL_PAD_SD1_CMD__SD1_CMD 0x170F9
  318. MX6QDL_PAD_SD1_CLK__SD1_CLK 0x100F9
  319. MX6QDL_PAD_SD1_DAT0__SD1_DATA0 0x170F9
  320. MX6QDL_PAD_SD1_DAT1__SD1_DATA1 0x170F9
  321. MX6QDL_PAD_SD1_DAT2__SD1_DATA2 0x170F9
  322. MX6QDL_PAD_SD1_DAT3__SD1_DATA3 0x170F9
  323. >;
  324. };
  325. pinctrl_usdhc2: usdhc2grp {
  326. fsl,pins = <
  327. MX6QDL_PAD_SD2_CMD__SD2_CMD 0x17059
  328. MX6QDL_PAD_SD2_CLK__SD2_CLK 0x10059
  329. MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x17059
  330. MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x17059
  331. MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x17059
  332. MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x17059
  333. >;
  334. };
  335. pinctrl_usdhc3: usdhc3grp {
  336. fsl,pins = <
  337. MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059
  338. MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10059
  339. MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059
  340. MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059
  341. MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059
  342. MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059
  343. >;
  344. };
  345. };
  346. &pcie {
  347. fsl,tx-swing-full = <103>;
  348. fsl,tx-swing-low = <103>;
  349. reset-gpio = <&gpio4 11 GPIO_ACTIVE_LOW>;
  350. status = "disabled";
  351. };
  352. &pwm2 {
  353. pinctrl-names = "default";
  354. pinctrl-0 = <&pinctrl_pwm2>;
  355. status = "disabled";
  356. };
  357. &reg_arm {
  358. vin-supply = <&sw1a_reg>;
  359. };
  360. &reg_pu {
  361. vin-supply = <&sw1c_reg>;
  362. };
  363. &reg_soc {
  364. vin-supply = <&sw1c_reg>;
  365. };
  366. &snvs_poweroff {
  367. status = "okay";
  368. };
  369. &ssi2 {
  370. status = "okay";
  371. };
  372. &uart1 {
  373. pinctrl-names = "default";
  374. pinctrl-0 = <&pinctrl_uart1>;
  375. status = "disabled";
  376. };
  377. &uart2 {
  378. pinctrl-names = "default";
  379. pinctrl-0 = <&pinctrl_uart2 &pinctrl_bt>;
  380. uart-has-rtscts;
  381. status = "okay";
  382. bluetooth {
  383. compatible = "ti,wl1835-st";
  384. enable-gpios = <&gpio6 18 GPIO_ACTIVE_HIGH>;
  385. };
  386. };
  387. &uart3 {
  388. pinctrl-names = "default";
  389. pinctrl-0 = <&pinctrl_uart3>;
  390. uart-has-rtscts;
  391. status = "disabled";
  392. };
  393. &usbh1 {
  394. status = "disabled";
  395. };
  396. &usbotg {
  397. vbus-supply = <&reg_usb_otg_vbus>;
  398. pinctrl-names = "default";
  399. pinctrl-0 = <&pinctrl_usbotg>;
  400. disable-over-current;
  401. status = "disabled";
  402. };
  403. &usdhc1 {
  404. pinctrl-names = "default", "state_100mhz", "state_200mhz";
  405. pinctrl-0 = <&pinctrl_usdhc1>;
  406. pinctrl-1 = <&pinctrl_usdhc1_100mhz>;
  407. pinctrl-2 = <&pinctrl_usdhc1_200mhz>;
  408. bus-width = <4>;
  409. vmmc-supply = <&reg_wl18xx_vmmc>;
  410. non-removable;
  411. wakeup-source;
  412. keep-power-in-suspend;
  413. cap-power-off-card;
  414. #address-cells = <1>;
  415. #size-cells = <0>;
  416. status = "okay";
  417. wlcore: wlcore@2 {
  418. compatible = "ti,wl1835";
  419. reg = <2>;
  420. interrupt-parent = <&gpio6>;
  421. interrupts = <17 IRQ_TYPE_LEVEL_HIGH>;
  422. ref-clock-frequency = <38400000>;
  423. };
  424. };
  425. &usdhc2 {
  426. pinctrl-names = "default";
  427. pinctrl-0 = <&pinctrl_usdhc2>;
  428. no-1-8-v;
  429. keep-power-in-suspend;
  430. wakeup-source;
  431. status = "disabled";
  432. };
  433. &usdhc3 {
  434. pinctrl-names = "default";
  435. pinctrl-0 = <&pinctrl_usdhc3>;
  436. non-removable;
  437. keep-power-in-suspend;
  438. wakeup-source;
  439. status = "okay";
  440. };