imx6qdl-sabresd.dtsi 18 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. //
  3. // Copyright 2012 Freescale Semiconductor, Inc.
  4. // Copyright 2011 Linaro Ltd.
  5. #include <dt-bindings/clock/imx6qdl-clock.h>
  6. #include <dt-bindings/gpio/gpio.h>
  7. #include <dt-bindings/input/input.h>
  8. / {
  9. chosen {
  10. stdout-path = &uart1;
  11. };
  12. memory@10000000 {
  13. device_type = "memory";
  14. reg = <0x10000000 0x40000000>;
  15. };
  16. reg_usb_otg_vbus: regulator-usb-otg-vbus {
  17. compatible = "regulator-fixed";
  18. regulator-name = "usb_otg_vbus";
  19. regulator-min-microvolt = <5000000>;
  20. regulator-max-microvolt = <5000000>;
  21. gpio = <&gpio3 22 GPIO_ACTIVE_HIGH>;
  22. enable-active-high;
  23. vin-supply = <&swbst_reg>;
  24. };
  25. reg_usb_h1_vbus: regulator-usb-h1-vbus {
  26. compatible = "regulator-fixed";
  27. regulator-name = "usb_h1_vbus";
  28. regulator-min-microvolt = <5000000>;
  29. regulator-max-microvolt = <5000000>;
  30. gpio = <&gpio1 29 GPIO_ACTIVE_HIGH>;
  31. enable-active-high;
  32. vin-supply = <&swbst_reg>;
  33. };
  34. reg_audio: regulator-audio {
  35. compatible = "regulator-fixed";
  36. regulator-name = "wm8962-supply";
  37. gpio = <&gpio4 10 GPIO_ACTIVE_HIGH>;
  38. enable-active-high;
  39. };
  40. reg_pcie: regulator-pcie {
  41. compatible = "regulator-fixed";
  42. pinctrl-names = "default";
  43. pinctrl-0 = <&pinctrl_pcie_reg>;
  44. regulator-name = "MPCIE_3V3";
  45. regulator-min-microvolt = <3300000>;
  46. regulator-max-microvolt = <3300000>;
  47. gpio = <&gpio3 19 GPIO_ACTIVE_HIGH>;
  48. enable-active-high;
  49. };
  50. reg_sensors: regulator-sensors {
  51. compatible = "regulator-fixed";
  52. pinctrl-names = "default";
  53. pinctrl-0 = <&pinctrl_sensors_reg>;
  54. regulator-name = "sensors-supply";
  55. regulator-min-microvolt = <3300000>;
  56. regulator-max-microvolt = <3300000>;
  57. gpio = <&gpio2 31 GPIO_ACTIVE_HIGH>;
  58. enable-active-high;
  59. };
  60. gpio-keys {
  61. compatible = "gpio-keys";
  62. pinctrl-names = "default";
  63. pinctrl-0 = <&pinctrl_gpio_keys>;
  64. power {
  65. label = "Power Button";
  66. gpios = <&gpio3 29 GPIO_ACTIVE_LOW>;
  67. wakeup-source;
  68. linux,code = <KEY_POWER>;
  69. };
  70. volume-up {
  71. label = "Volume Up";
  72. gpios = <&gpio1 4 GPIO_ACTIVE_LOW>;
  73. wakeup-source;
  74. linux,code = <KEY_VOLUMEUP>;
  75. };
  76. volume-down {
  77. label = "Volume Down";
  78. gpios = <&gpio1 5 GPIO_ACTIVE_LOW>;
  79. wakeup-source;
  80. linux,code = <KEY_VOLUMEDOWN>;
  81. };
  82. };
  83. sound {
  84. compatible = "fsl,imx6q-sabresd-wm8962",
  85. "fsl,imx-audio-wm8962";
  86. model = "wm8962-audio";
  87. pinctrl-names = "default";
  88. pinctrl-0 = <&pinctrl_hp>;
  89. ssi-controller = <&ssi2>;
  90. audio-codec = <&codec>;
  91. audio-asrc = <&asrc>;
  92. audio-routing =
  93. "Headphone Jack", "HPOUTL",
  94. "Headphone Jack", "HPOUTR",
  95. "Ext Spk", "SPKOUTL",
  96. "Ext Spk", "SPKOUTR",
  97. "AMIC", "MICBIAS",
  98. "IN3R", "AMIC",
  99. "DMIC", "MICBIAS",
  100. "DMICDAT", "DMIC";
  101. mux-int-port = <2>;
  102. mux-ext-port = <3>;
  103. hp-det-gpio = <&gpio7 8 GPIO_ACTIVE_LOW>;
  104. mic-det-gpio = <&gpio1 9 GPIO_ACTIVE_LOW>;
  105. };
  106. backlight_lvds: backlight-lvds {
  107. compatible = "pwm-backlight";
  108. pwms = <&pwm1 0 5000000>;
  109. brightness-levels = <0 4 8 16 32 64 128 255>;
  110. default-brightness-level = <7>;
  111. status = "okay";
  112. };
  113. leds {
  114. compatible = "gpio-leds";
  115. pinctrl-names = "default";
  116. pinctrl-0 = <&pinctrl_gpio_leds>;
  117. led-red {
  118. gpios = <&gpio1 2 0>;
  119. default-state = "on";
  120. };
  121. };
  122. panel {
  123. compatible = "hannstar,hsd100pxn1";
  124. backlight = <&backlight_lvds>;
  125. port {
  126. panel_in: endpoint {
  127. remote-endpoint = <&lvds0_out>;
  128. };
  129. };
  130. };
  131. };
  132. &ipu1_csi0_from_ipu1_csi0_mux {
  133. bus-width = <8>;
  134. data-shift = <12>; /* Lines 19:12 used */
  135. hsync-active = <1>;
  136. vsync-active = <1>;
  137. };
  138. &ipu1_csi0_mux_from_parallel_sensor {
  139. remote-endpoint = <&ov5642_to_ipu1_csi0_mux>;
  140. };
  141. &ipu1_csi0 {
  142. pinctrl-names = "default";
  143. pinctrl-0 = <&pinctrl_ipu1_csi0>;
  144. };
  145. &mipi_csi {
  146. status = "okay";
  147. port@0 {
  148. reg = <0>;
  149. mipi_csi2_in: endpoint {
  150. remote-endpoint = <&ov5640_to_mipi_csi2>;
  151. clock-lanes = <0>;
  152. data-lanes = <1 2>;
  153. };
  154. };
  155. };
  156. &audmux {
  157. pinctrl-names = "default";
  158. pinctrl-0 = <&pinctrl_audmux>;
  159. status = "okay";
  160. };
  161. &clks {
  162. assigned-clocks = <&clks IMX6QDL_CLK_LDB_DI0_SEL>,
  163. <&clks IMX6QDL_CLK_LDB_DI1_SEL>;
  164. assigned-clock-parents = <&clks IMX6QDL_CLK_PLL3_USB_OTG>,
  165. <&clks IMX6QDL_CLK_PLL3_USB_OTG>;
  166. };
  167. &ecspi1 {
  168. cs-gpios = <&gpio4 9 GPIO_ACTIVE_LOW>;
  169. pinctrl-names = "default";
  170. pinctrl-0 = <&pinctrl_ecspi1>;
  171. status = "okay";
  172. flash: flash@0 {
  173. #address-cells = <1>;
  174. #size-cells = <1>;
  175. compatible = "st,m25p32", "jedec,spi-nor";
  176. spi-max-frequency = <20000000>;
  177. reg = <0>;
  178. };
  179. };
  180. &fec {
  181. pinctrl-names = "default";
  182. pinctrl-0 = <&pinctrl_enet>;
  183. phy-mode = "rgmii-id";
  184. phy-handle = <&phy>;
  185. fsl,magic-packet;
  186. status = "okay";
  187. mdio {
  188. #address-cells = <1>;
  189. #size-cells = <0>;
  190. phy: ethernet-phy@1 {
  191. reg = <1>;
  192. qca,clk-out-frequency = <125000000>;
  193. reset-gpios = <&gpio1 25 GPIO_ACTIVE_LOW>;
  194. reset-assert-us = <10000>;
  195. };
  196. };
  197. };
  198. &hdmi {
  199. pinctrl-names = "default";
  200. pinctrl-0 = <&pinctrl_hdmi_cec>;
  201. ddc-i2c-bus = <&i2c2>;
  202. status = "okay";
  203. };
  204. &i2c1 {
  205. clock-frequency = <100000>;
  206. pinctrl-names = "default";
  207. pinctrl-0 = <&pinctrl_i2c1>;
  208. status = "okay";
  209. codec: wm8962@1a {
  210. compatible = "wlf,wm8962";
  211. reg = <0x1a>;
  212. clocks = <&clks IMX6QDL_CLK_CKO>;
  213. DCVDD-supply = <&reg_audio>;
  214. DBVDD-supply = <&reg_audio>;
  215. AVDD-supply = <&reg_audio>;
  216. CPVDD-supply = <&reg_audio>;
  217. MICVDD-supply = <&reg_audio>;
  218. PLLVDD-supply = <&reg_audio>;
  219. SPKVDD1-supply = <&reg_audio>;
  220. SPKVDD2-supply = <&reg_audio>;
  221. gpio-cfg = <
  222. 0x0000 /* 0:Default */
  223. 0x0000 /* 1:Default */
  224. 0x0013 /* 2:FN_DMICCLK */
  225. 0x0000 /* 3:Default */
  226. 0x8014 /* 4:FN_DMICCDAT */
  227. 0x0000 /* 5:Default */
  228. >;
  229. };
  230. accelerometer@1c {
  231. compatible = "fsl,mma8451";
  232. reg = <0x1c>;
  233. pinctrl-names = "default";
  234. pinctrl-0 = <&pinctrl_i2c1_mma8451_int>;
  235. interrupt-parent = <&gpio1>;
  236. interrupts = <18 IRQ_TYPE_LEVEL_LOW>;
  237. vdd-supply = <&reg_sensors>;
  238. vddio-supply = <&reg_sensors>;
  239. };
  240. ov5642: camera@3c {
  241. compatible = "ovti,ov5642";
  242. pinctrl-names = "default";
  243. pinctrl-0 = <&pinctrl_ov5642>;
  244. clocks = <&clks IMX6QDL_CLK_CKO>;
  245. clock-names = "xclk";
  246. reg = <0x3c>;
  247. DOVDD-supply = <&vgen4_reg>; /* 1.8v */
  248. AVDD-supply = <&vgen3_reg>; /* 2.8v, rev C board is VGEN3
  249. rev B board is VGEN5 */
  250. DVDD-supply = <&vgen2_reg>; /* 1.5v*/
  251. powerdown-gpios = <&gpio1 16 GPIO_ACTIVE_HIGH>;
  252. reset-gpios = <&gpio1 17 GPIO_ACTIVE_LOW>;
  253. status = "disabled";
  254. port {
  255. ov5642_to_ipu1_csi0_mux: endpoint {
  256. remote-endpoint = <&ipu1_csi0_mux_from_parallel_sensor>;
  257. bus-width = <8>;
  258. hsync-active = <1>;
  259. vsync-active = <1>;
  260. };
  261. };
  262. };
  263. };
  264. &i2c2 {
  265. clock-frequency = <100000>;
  266. pinctrl-names = "default";
  267. pinctrl-0 = <&pinctrl_i2c2>;
  268. status = "okay";
  269. touchscreen@4 {
  270. compatible = "eeti,egalax_ts";
  271. reg = <0x04>;
  272. pinctrl-names = "default";
  273. pinctrl-0 = <&pinctrl_i2c2_egalax_int>;
  274. interrupt-parent = <&gpio6>;
  275. interrupts = <8 IRQ_TYPE_EDGE_FALLING>;
  276. wakeup-gpios = <&gpio6 8 GPIO_ACTIVE_HIGH>;
  277. };
  278. ov5640: camera@3c {
  279. compatible = "ovti,ov5640";
  280. pinctrl-names = "default";
  281. pinctrl-0 = <&pinctrl_ov5640>;
  282. reg = <0x3c>;
  283. clocks = <&clks IMX6QDL_CLK_CKO>;
  284. clock-names = "xclk";
  285. DOVDD-supply = <&vgen4_reg>; /* 1.8v */
  286. AVDD-supply = <&vgen3_reg>; /* 2.8v, rev C board is VGEN3
  287. rev B board is VGEN5 */
  288. DVDD-supply = <&vgen2_reg>; /* 1.5v*/
  289. powerdown-gpios = <&gpio1 19 GPIO_ACTIVE_HIGH>;
  290. reset-gpios = <&gpio1 20 GPIO_ACTIVE_LOW>;
  291. port {
  292. ov5640_to_mipi_csi2: endpoint {
  293. remote-endpoint = <&mipi_csi2_in>;
  294. clock-lanes = <0>;
  295. data-lanes = <1 2>;
  296. };
  297. };
  298. };
  299. pmic: pfuze100@8 {
  300. compatible = "fsl,pfuze100";
  301. reg = <0x08>;
  302. regulators {
  303. sw1a_reg: sw1ab {
  304. regulator-min-microvolt = <300000>;
  305. regulator-max-microvolt = <1875000>;
  306. regulator-boot-on;
  307. regulator-always-on;
  308. regulator-ramp-delay = <6250>;
  309. };
  310. sw1c_reg: sw1c {
  311. regulator-min-microvolt = <300000>;
  312. regulator-max-microvolt = <1875000>;
  313. regulator-boot-on;
  314. regulator-always-on;
  315. regulator-ramp-delay = <6250>;
  316. };
  317. sw2_reg: sw2 {
  318. regulator-min-microvolt = <800000>;
  319. regulator-max-microvolt = <3300000>;
  320. regulator-boot-on;
  321. regulator-always-on;
  322. regulator-ramp-delay = <6250>;
  323. };
  324. sw3a_reg: sw3a {
  325. regulator-min-microvolt = <400000>;
  326. regulator-max-microvolt = <1975000>;
  327. regulator-boot-on;
  328. regulator-always-on;
  329. };
  330. sw3b_reg: sw3b {
  331. regulator-min-microvolt = <400000>;
  332. regulator-max-microvolt = <1975000>;
  333. regulator-boot-on;
  334. regulator-always-on;
  335. };
  336. sw4_reg: sw4 {
  337. regulator-min-microvolt = <800000>;
  338. regulator-max-microvolt = <3300000>;
  339. regulator-always-on;
  340. };
  341. swbst_reg: swbst {
  342. regulator-min-microvolt = <5000000>;
  343. regulator-max-microvolt = <5150000>;
  344. };
  345. snvs_reg: vsnvs {
  346. regulator-min-microvolt = <1000000>;
  347. regulator-max-microvolt = <3000000>;
  348. regulator-boot-on;
  349. regulator-always-on;
  350. };
  351. vref_reg: vrefddr {
  352. regulator-boot-on;
  353. regulator-always-on;
  354. };
  355. vgen1_reg: vgen1 {
  356. regulator-min-microvolt = <800000>;
  357. regulator-max-microvolt = <1550000>;
  358. };
  359. vgen2_reg: vgen2 {
  360. regulator-min-microvolt = <800000>;
  361. regulator-max-microvolt = <1550000>;
  362. };
  363. vgen3_reg: vgen3 {
  364. regulator-min-microvolt = <1800000>;
  365. regulator-max-microvolt = <3300000>;
  366. };
  367. vgen4_reg: vgen4 {
  368. regulator-min-microvolt = <1800000>;
  369. regulator-max-microvolt = <3300000>;
  370. regulator-always-on;
  371. };
  372. vgen5_reg: vgen5 {
  373. regulator-min-microvolt = <1800000>;
  374. regulator-max-microvolt = <3300000>;
  375. regulator-always-on;
  376. };
  377. vgen6_reg: vgen6 {
  378. regulator-min-microvolt = <1800000>;
  379. regulator-max-microvolt = <3300000>;
  380. regulator-always-on;
  381. };
  382. };
  383. };
  384. };
  385. &i2c3 {
  386. clock-frequency = <100000>;
  387. pinctrl-names = "default";
  388. pinctrl-0 = <&pinctrl_i2c3>;
  389. status = "okay";
  390. egalax_ts@4 {
  391. compatible = "eeti,egalax_ts";
  392. reg = <0x04>;
  393. interrupt-parent = <&gpio6>;
  394. interrupts = <7 2>;
  395. wakeup-gpios = <&gpio6 7 0>;
  396. };
  397. magnetometer@e {
  398. compatible = "fsl,mag3110";
  399. reg = <0x0e>;
  400. pinctrl-names = "default";
  401. pinctrl-0 = <&pinctrl_i2c3_mag3110_int>;
  402. interrupt-parent = <&gpio3>;
  403. interrupts = <16 IRQ_TYPE_EDGE_RISING>;
  404. vdd-supply = <&reg_sensors>;
  405. vddio-supply = <&reg_sensors>;
  406. };
  407. light-sensor@44 {
  408. compatible = "isil,isl29023";
  409. reg = <0x44>;
  410. pinctrl-names = "default";
  411. pinctrl-0 = <&pinctrl_i2c3_isl29023_int>;
  412. interrupt-parent = <&gpio3>;
  413. interrupts = <9 IRQ_TYPE_EDGE_FALLING>;
  414. vcc-supply = <&reg_sensors>;
  415. };
  416. };
  417. &iomuxc {
  418. pinctrl-names = "default";
  419. pinctrl-0 = <&pinctrl_hog>;
  420. imx6qdl-sabresd {
  421. pinctrl_hog: hoggrp {
  422. fsl,pins = <
  423. MX6QDL_PAD_NANDF_D0__GPIO2_IO00 0x1b0b0
  424. MX6QDL_PAD_NANDF_D1__GPIO2_IO01 0x1b0b0
  425. MX6QDL_PAD_NANDF_D2__GPIO2_IO02 0x1b0b0
  426. MX6QDL_PAD_NANDF_D3__GPIO2_IO03 0x1b0b0
  427. MX6QDL_PAD_GPIO_0__CCM_CLKO1 0x130b0
  428. MX6QDL_PAD_NANDF_CLE__GPIO6_IO07 0x1b0b0
  429. MX6QDL_PAD_ENET_TXD1__GPIO1_IO29 0x1b0b0
  430. MX6QDL_PAD_EIM_D22__GPIO3_IO22 0x1b0b0
  431. MX6QDL_PAD_ENET_CRS_DV__GPIO1_IO25 0x1b0b0
  432. >;
  433. };
  434. pinctrl_audmux: audmuxgrp {
  435. fsl,pins = <
  436. MX6QDL_PAD_CSI0_DAT7__AUD3_RXD 0x130b0
  437. MX6QDL_PAD_CSI0_DAT4__AUD3_TXC 0x130b0
  438. MX6QDL_PAD_CSI0_DAT5__AUD3_TXD 0x110b0
  439. MX6QDL_PAD_CSI0_DAT6__AUD3_TXFS 0x130b0
  440. >;
  441. };
  442. pinctrl_ecspi1: ecspi1grp {
  443. fsl,pins = <
  444. MX6QDL_PAD_KEY_COL1__ECSPI1_MISO 0x100b1
  445. MX6QDL_PAD_KEY_ROW0__ECSPI1_MOSI 0x100b1
  446. MX6QDL_PAD_KEY_COL0__ECSPI1_SCLK 0x100b1
  447. MX6QDL_PAD_KEY_ROW1__GPIO4_IO09 0x1b0b0
  448. >;
  449. };
  450. pinctrl_enet: enetgrp {
  451. fsl,pins = <
  452. MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0
  453. MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0
  454. MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b030
  455. MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b030
  456. MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b030
  457. MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b030
  458. MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b030
  459. MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b030
  460. MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0
  461. MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b030
  462. MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b030
  463. MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b030
  464. MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b030
  465. MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b030
  466. MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b030
  467. MX6QDL_PAD_GPIO_16__ENET_REF_CLK 0x4001b0a8
  468. >;
  469. };
  470. pinctrl_gpio_keys: gpio_keysgrp {
  471. fsl,pins = <
  472. MX6QDL_PAD_EIM_D29__GPIO3_IO29 0x1b0b0
  473. MX6QDL_PAD_GPIO_4__GPIO1_IO04 0x1b0b0
  474. MX6QDL_PAD_GPIO_5__GPIO1_IO05 0x1b0b0
  475. >;
  476. };
  477. pinctrl_hdmi_cec: hdmicecgrp {
  478. fsl,pins = <
  479. MX6QDL_PAD_KEY_ROW2__HDMI_TX_CEC_LINE 0x1f8b0
  480. >;
  481. };
  482. pinctrl_hp: hpgrp {
  483. fsl,pins = <
  484. MX6QDL_PAD_SD3_RST__GPIO7_IO08 0x1b0b0
  485. MX6QDL_PAD_GPIO_9__GPIO1_IO09 0x1b0b0
  486. >;
  487. };
  488. pinctrl_i2c1: i2c1grp {
  489. fsl,pins = <
  490. MX6QDL_PAD_CSI0_DAT8__I2C1_SDA 0x4001b8b1
  491. MX6QDL_PAD_CSI0_DAT9__I2C1_SCL 0x4001b8b1
  492. >;
  493. };
  494. pinctrl_i2c1_mma8451_int: i2c1mma8451intgrp {
  495. fsl,pins = <
  496. MX6QDL_PAD_SD1_CMD__GPIO1_IO18 0xb0b1
  497. >;
  498. };
  499. pinctrl_i2c2: i2c2grp {
  500. fsl,pins = <
  501. MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1
  502. MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1
  503. >;
  504. };
  505. pinctrl_i2c2_egalax_int: i2c2egalaxintgrp {
  506. fsl,pins = <
  507. MX6QDL_PAD_NANDF_ALE__GPIO6_IO08 0x1b0b0
  508. >;
  509. };
  510. pinctrl_i2c3: i2c3grp {
  511. fsl,pins = <
  512. MX6QDL_PAD_GPIO_3__I2C3_SCL 0x4001b8b1
  513. MX6QDL_PAD_GPIO_6__I2C3_SDA 0x4001b8b1
  514. >;
  515. };
  516. pinctrl_i2c3_isl29023_int: i2c3isl29023intgrp {
  517. fsl,pins = <
  518. MX6QDL_PAD_EIM_DA9__GPIO3_IO09 0xb0b1
  519. >;
  520. };
  521. pinctrl_i2c3_mag3110_int: i2c3mag3110intgrp {
  522. fsl,pins = <
  523. MX6QDL_PAD_EIM_D16__GPIO3_IO16 0xb0b1
  524. >;
  525. };
  526. pinctrl_ipu1_csi0: ipu1csi0grp {
  527. fsl,pins = <
  528. MX6QDL_PAD_CSI0_DAT12__IPU1_CSI0_DATA12 0x1b0b0
  529. MX6QDL_PAD_CSI0_DAT13__IPU1_CSI0_DATA13 0x1b0b0
  530. MX6QDL_PAD_CSI0_DAT14__IPU1_CSI0_DATA14 0x1b0b0
  531. MX6QDL_PAD_CSI0_DAT15__IPU1_CSI0_DATA15 0x1b0b0
  532. MX6QDL_PAD_CSI0_DAT16__IPU1_CSI0_DATA16 0x1b0b0
  533. MX6QDL_PAD_CSI0_DAT17__IPU1_CSI0_DATA17 0x1b0b0
  534. MX6QDL_PAD_CSI0_DAT18__IPU1_CSI0_DATA18 0x1b0b0
  535. MX6QDL_PAD_CSI0_DAT19__IPU1_CSI0_DATA19 0x1b0b0
  536. MX6QDL_PAD_CSI0_PIXCLK__IPU1_CSI0_PIXCLK 0x1b0b0
  537. MX6QDL_PAD_CSI0_MCLK__IPU1_CSI0_HSYNC 0x1b0b0
  538. MX6QDL_PAD_CSI0_VSYNC__IPU1_CSI0_VSYNC 0x1b0b0
  539. >;
  540. };
  541. pinctrl_ov5640: ov5640grp {
  542. fsl,pins = <
  543. MX6QDL_PAD_SD1_DAT2__GPIO1_IO19 0x1b0b0
  544. MX6QDL_PAD_SD1_CLK__GPIO1_IO20 0x1b0b0
  545. >;
  546. };
  547. pinctrl_ov5642: ov5642grp {
  548. fsl,pins = <
  549. MX6QDL_PAD_SD1_DAT0__GPIO1_IO16 0x1b0b0
  550. MX6QDL_PAD_SD1_DAT1__GPIO1_IO17 0x1b0b0
  551. >;
  552. };
  553. pinctrl_pcie: pciegrp {
  554. fsl,pins = <
  555. MX6QDL_PAD_GPIO_17__GPIO7_IO12 0x1b0b0
  556. >;
  557. };
  558. pinctrl_pcie_reg: pciereggrp {
  559. fsl,pins = <
  560. MX6QDL_PAD_EIM_D19__GPIO3_IO19 0x1b0b0
  561. >;
  562. };
  563. pinctrl_pwm1: pwm1grp {
  564. fsl,pins = <
  565. MX6QDL_PAD_SD1_DAT3__PWM1_OUT 0x1b0b1
  566. >;
  567. };
  568. pinctrl_sensors_reg: sensorsreggrp {
  569. fsl,pins = <
  570. MX6QDL_PAD_EIM_EB3__GPIO2_IO31 0x1b0b0
  571. >;
  572. };
  573. pinctrl_uart1: uart1grp {
  574. fsl,pins = <
  575. MX6QDL_PAD_CSI0_DAT10__UART1_TX_DATA 0x1b0b1
  576. MX6QDL_PAD_CSI0_DAT11__UART1_RX_DATA 0x1b0b1
  577. >;
  578. };
  579. pinctrl_usbotg: usbotggrp {
  580. fsl,pins = <
  581. MX6QDL_PAD_ENET_RX_ER__USB_OTG_ID 0x17059
  582. >;
  583. };
  584. pinctrl_usdhc2: usdhc2grp {
  585. fsl,pins = <
  586. MX6QDL_PAD_SD2_CMD__SD2_CMD 0x17059
  587. MX6QDL_PAD_SD2_CLK__SD2_CLK 0x10059
  588. MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x17059
  589. MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x17059
  590. MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x17059
  591. MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x17059
  592. MX6QDL_PAD_NANDF_D4__SD2_DATA4 0x17059
  593. MX6QDL_PAD_NANDF_D5__SD2_DATA5 0x17059
  594. MX6QDL_PAD_NANDF_D6__SD2_DATA6 0x17059
  595. MX6QDL_PAD_NANDF_D7__SD2_DATA7 0x17059
  596. >;
  597. };
  598. pinctrl_usdhc3: usdhc3grp {
  599. fsl,pins = <
  600. MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059
  601. MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10059
  602. MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059
  603. MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059
  604. MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059
  605. MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059
  606. MX6QDL_PAD_SD3_DAT4__SD3_DATA4 0x17059
  607. MX6QDL_PAD_SD3_DAT5__SD3_DATA5 0x17059
  608. MX6QDL_PAD_SD3_DAT6__SD3_DATA6 0x17059
  609. MX6QDL_PAD_SD3_DAT7__SD3_DATA7 0x17059
  610. >;
  611. };
  612. pinctrl_usdhc4: usdhc4grp {
  613. fsl,pins = <
  614. MX6QDL_PAD_SD4_CMD__SD4_CMD 0x17059
  615. MX6QDL_PAD_SD4_CLK__SD4_CLK 0x10059
  616. MX6QDL_PAD_SD4_DAT0__SD4_DATA0 0x17059
  617. MX6QDL_PAD_SD4_DAT1__SD4_DATA1 0x17059
  618. MX6QDL_PAD_SD4_DAT2__SD4_DATA2 0x17059
  619. MX6QDL_PAD_SD4_DAT3__SD4_DATA3 0x17059
  620. MX6QDL_PAD_SD4_DAT4__SD4_DATA4 0x17059
  621. MX6QDL_PAD_SD4_DAT5__SD4_DATA5 0x17059
  622. MX6QDL_PAD_SD4_DAT6__SD4_DATA6 0x17059
  623. MX6QDL_PAD_SD4_DAT7__SD4_DATA7 0x17059
  624. >;
  625. };
  626. pinctrl_wdog: wdoggrp {
  627. fsl,pins = <
  628. MX6QDL_PAD_GPIO_1__WDOG2_B 0x1b0b0
  629. >;
  630. };
  631. };
  632. gpio_leds {
  633. pinctrl_gpio_leds: gpioledsgrp {
  634. fsl,pins = <
  635. MX6QDL_PAD_GPIO_2__GPIO1_IO02 0x1b0b0
  636. >;
  637. };
  638. };
  639. };
  640. &ldb {
  641. status = "okay";
  642. lvds-channel@1 {
  643. fsl,data-mapping = "spwg";
  644. fsl,data-width = <18>;
  645. status = "okay";
  646. port@4 {
  647. reg = <4>;
  648. lvds0_out: endpoint {
  649. remote-endpoint = <&panel_in>;
  650. };
  651. };
  652. };
  653. };
  654. &pcie {
  655. pinctrl-names = "default";
  656. pinctrl-0 = <&pinctrl_pcie>;
  657. reset-gpio = <&gpio7 12 GPIO_ACTIVE_LOW>;
  658. vpcie-supply = <&reg_pcie>;
  659. status = "okay";
  660. };
  661. &pwm1 {
  662. #pwm-cells = <2>;
  663. pinctrl-names = "default";
  664. pinctrl-0 = <&pinctrl_pwm1>;
  665. status = "okay";
  666. };
  667. &reg_arm {
  668. vin-supply = <&sw1a_reg>;
  669. };
  670. &reg_pu {
  671. vin-supply = <&sw1c_reg>;
  672. };
  673. &reg_soc {
  674. vin-supply = <&sw1c_reg>;
  675. };
  676. &reg_vdd1p1 {
  677. vin-supply = <&vgen5_reg>;
  678. };
  679. &reg_vdd2p5 {
  680. vin-supply = <&vgen5_reg>;
  681. };
  682. &snvs_poweroff {
  683. status = "okay";
  684. };
  685. &snvs_pwrkey {
  686. status = "okay";
  687. };
  688. &ssi2 {
  689. status = "okay";
  690. };
  691. &uart1 {
  692. pinctrl-names = "default";
  693. pinctrl-0 = <&pinctrl_uart1>;
  694. status = "okay";
  695. };
  696. &usbh1 {
  697. vbus-supply = <&reg_usb_h1_vbus>;
  698. status = "okay";
  699. };
  700. &usbotg {
  701. vbus-supply = <&reg_usb_otg_vbus>;
  702. pinctrl-names = "default";
  703. pinctrl-0 = <&pinctrl_usbotg>;
  704. disable-over-current;
  705. status = "okay";
  706. };
  707. &usdhc2 {
  708. pinctrl-names = "default";
  709. pinctrl-0 = <&pinctrl_usdhc2>;
  710. bus-width = <8>;
  711. cd-gpios = <&gpio2 2 GPIO_ACTIVE_LOW>;
  712. wp-gpios = <&gpio2 3 GPIO_ACTIVE_HIGH>;
  713. status = "okay";
  714. };
  715. &usdhc3 {
  716. pinctrl-names = "default";
  717. pinctrl-0 = <&pinctrl_usdhc3>;
  718. bus-width = <8>;
  719. cd-gpios = <&gpio2 0 GPIO_ACTIVE_LOW>;
  720. wp-gpios = <&gpio2 1 GPIO_ACTIVE_HIGH>;
  721. status = "okay";
  722. };
  723. &usdhc4 {
  724. pinctrl-names = "default";
  725. pinctrl-0 = <&pinctrl_usdhc4>;
  726. bus-width = <8>;
  727. non-removable;
  728. no-1-8-v;
  729. status = "okay";
  730. };
  731. &wdog1 {
  732. status = "disabled";
  733. };
  734. &wdog2 {
  735. pinctrl-names = "default";
  736. pinctrl-0 = <&pinctrl_wdog>;
  737. fsl,ext-reset-output;
  738. status = "okay";
  739. };