imx6qdl-nitrogen6_som2.dtsi 16 KB

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  1. // SPDX-License-Identifier: GPL-2.0 OR X11
  2. /*
  3. * Copyright 2016 Boundary Devices, Inc.
  4. */
  5. #include <dt-bindings/gpio/gpio.h>
  6. #include <dt-bindings/input/input.h>
  7. / {
  8. chosen {
  9. stdout-path = &uart2;
  10. };
  11. memory@10000000 {
  12. device_type = "memory";
  13. reg = <0x10000000 0x40000000>;
  14. };
  15. backlight_lcd: backlight-lcd {
  16. compatible = "pwm-backlight";
  17. pwms = <&pwm1 0 5000000>;
  18. brightness-levels = <0 4 8 16 32 64 128 255>;
  19. default-brightness-level = <7>;
  20. power-supply = <&reg_3p3v>;
  21. status = "okay";
  22. };
  23. backlight_lvds0: backlight-lvds0 {
  24. compatible = "pwm-backlight";
  25. pwms = <&pwm4 0 5000000>;
  26. brightness-levels = <0 4 8 16 32 64 128 255>;
  27. default-brightness-level = <7>;
  28. power-supply = <&reg_3p3v>;
  29. status = "okay";
  30. };
  31. backlight_lvds1: backlight-lvds1 {
  32. compatible = "gpio-backlight";
  33. pinctrl-names = "default";
  34. pinctrl-0 = <&pinctrl_backlight_lvds1>;
  35. gpios = <&gpio2 31 GPIO_ACTIVE_HIGH>;
  36. default-on;
  37. status = "okay";
  38. };
  39. gpio-keys {
  40. compatible = "gpio-keys";
  41. pinctrl-names = "default";
  42. pinctrl-0 = <&pinctrl_gpio_keys>;
  43. power {
  44. label = "Power Button";
  45. gpios = <&gpio2 3 GPIO_ACTIVE_LOW>;
  46. linux,code = <KEY_POWER>;
  47. wakeup-source;
  48. };
  49. menu {
  50. label = "Menu";
  51. gpios = <&gpio2 1 GPIO_ACTIVE_LOW>;
  52. linux,code = <KEY_MENU>;
  53. };
  54. home {
  55. label = "Home";
  56. gpios = <&gpio2 4 GPIO_ACTIVE_LOW>;
  57. linux,code = <KEY_HOME>;
  58. };
  59. back {
  60. label = "Back";
  61. gpios = <&gpio2 2 GPIO_ACTIVE_LOW>;
  62. linux,code = <KEY_BACK>;
  63. };
  64. volume-up {
  65. label = "Volume Up";
  66. gpios = <&gpio7 13 GPIO_ACTIVE_LOW>;
  67. linux,code = <KEY_VOLUMEUP>;
  68. };
  69. volume-down {
  70. label = "Volume Down";
  71. gpios = <&gpio7 1 GPIO_ACTIVE_LOW>;
  72. linux,code = <KEY_VOLUMEDOWN>;
  73. };
  74. };
  75. lcd_display: disp0 {
  76. compatible = "fsl,imx-parallel-display";
  77. #address-cells = <1>;
  78. #size-cells = <0>;
  79. interface-pix-fmt = "bgr666";
  80. pinctrl-names = "default";
  81. pinctrl-0 = <&pinctrl_j15>;
  82. status = "okay";
  83. port@0 {
  84. reg = <0>;
  85. lcd_display_in: endpoint {
  86. remote-endpoint = <&ipu1_di0_disp0>;
  87. };
  88. };
  89. port@1 {
  90. reg = <1>;
  91. lcd_display_out: endpoint {
  92. remote-endpoint = <&lcd_panel_in>;
  93. };
  94. };
  95. };
  96. panel-lcd {
  97. compatible = "okaya,rs800480t-7x0gp";
  98. backlight = <&backlight_lcd>;
  99. port {
  100. lcd_panel_in: endpoint {
  101. remote-endpoint = <&lcd_display_out>;
  102. };
  103. };
  104. };
  105. panel-lvds0 {
  106. compatible = "hannstar,hsd100pxn1";
  107. backlight = <&backlight_lvds0>;
  108. port {
  109. panel_in_lvds0: endpoint {
  110. remote-endpoint = <&lvds0_out>;
  111. };
  112. };
  113. };
  114. panel-lvds1 {
  115. compatible = "hannstar,hsd100pxn1";
  116. backlight = <&backlight_lvds1>;
  117. port {
  118. panel_in_lvds1: endpoint {
  119. remote-endpoint = <&lvds1_out>;
  120. };
  121. };
  122. };
  123. reg_1p8v: regulator-1v8 {
  124. compatible = "regulator-fixed";
  125. regulator-name = "1P8V";
  126. regulator-min-microvolt = <1800000>;
  127. regulator-max-microvolt = <1800000>;
  128. regulator-always-on;
  129. };
  130. reg_2p5v: regulator-2v5 {
  131. compatible = "regulator-fixed";
  132. regulator-name = "2P5V";
  133. regulator-min-microvolt = <2500000>;
  134. regulator-max-microvolt = <2500000>;
  135. regulator-always-on;
  136. };
  137. reg_3p3v: regulator-3v3 {
  138. compatible = "regulator-fixed";
  139. regulator-name = "3P3V";
  140. regulator-min-microvolt = <3300000>;
  141. regulator-max-microvolt = <3300000>;
  142. regulator-always-on;
  143. };
  144. reg_can_xcvr: regulator-can-xcvr {
  145. compatible = "regulator-fixed";
  146. regulator-name = "CAN XCVR";
  147. regulator-min-microvolt = <3300000>;
  148. regulator-max-microvolt = <3300000>;
  149. pinctrl-names = "default";
  150. pinctrl-0 = <&pinctrl_can_xcvr>;
  151. gpio = <&gpio1 2 GPIO_ACTIVE_LOW>;
  152. };
  153. reg_usb_h1_vbus: regulator-usb-h1-vbus {
  154. compatible = "regulator-fixed";
  155. pinctrl-names = "default";
  156. pinctrl-0 = <&pinctrl_usbh1>;
  157. regulator-name = "usb_h1_vbus";
  158. regulator-min-microvolt = <3300000>;
  159. regulator-max-microvolt = <3300000>;
  160. gpio = <&gpio7 12 GPIO_ACTIVE_HIGH>;
  161. enable-active-high;
  162. regulator-always-on;
  163. };
  164. reg_usb_otg_vbus: regulator-usb-otg-vbus {
  165. compatible = "regulator-fixed";
  166. regulator-name = "usb_otg_vbus";
  167. regulator-min-microvolt = <5000000>;
  168. regulator-max-microvolt = <5000000>;
  169. gpio = <&gpio3 22 GPIO_ACTIVE_HIGH>;
  170. enable-active-high;
  171. };
  172. reg_wlan_vmmc: regulator-wlan-vmmc {
  173. compatible = "regulator-fixed";
  174. pinctrl-names = "default";
  175. pinctrl-0 = <&pinctrl_wlan_vmmc>;
  176. regulator-name = "reg_wlan_vmmc";
  177. regulator-min-microvolt = <3300000>;
  178. regulator-max-microvolt = <3300000>;
  179. gpio = <&gpio6 15 GPIO_ACTIVE_HIGH>;
  180. startup-delay-us = <70000>;
  181. enable-active-high;
  182. };
  183. sound {
  184. compatible = "fsl,imx6q-nitrogen6_som2-sgtl5000",
  185. "fsl,imx-audio-sgtl5000";
  186. model = "imx6q-nitrogen6_som2-sgtl5000";
  187. ssi-controller = <&ssi1>;
  188. audio-codec = <&codec>;
  189. audio-routing =
  190. "MIC_IN", "Mic Jack",
  191. "Mic Jack", "Mic Bias",
  192. "Headphone Jack", "HP_OUT";
  193. mux-int-port = <1>;
  194. mux-ext-port = <3>;
  195. };
  196. };
  197. &audmux {
  198. pinctrl-names = "default";
  199. pinctrl-0 = <&pinctrl_audmux>;
  200. status = "okay";
  201. };
  202. &can1 {
  203. pinctrl-names = "default";
  204. pinctrl-0 = <&pinctrl_can1>;
  205. xceiver-supply = <&reg_can_xcvr>;
  206. status = "okay";
  207. };
  208. &clks {
  209. assigned-clocks = <&clks IMX6QDL_CLK_LDB_DI0_SEL>,
  210. <&clks IMX6QDL_CLK_LDB_DI1_SEL>;
  211. assigned-clock-parents = <&clks IMX6QDL_CLK_PLL3_USB_OTG>,
  212. <&clks IMX6QDL_CLK_PLL3_USB_OTG>;
  213. };
  214. &ecspi1 {
  215. cs-gpios = <&gpio3 19 GPIO_ACTIVE_LOW>;
  216. pinctrl-names = "default";
  217. pinctrl-0 = <&pinctrl_ecspi1>;
  218. status = "okay";
  219. flash: flash@0 {
  220. compatible = "microchip,sst25vf016b";
  221. spi-max-frequency = <20000000>;
  222. reg = <0>;
  223. };
  224. };
  225. &fec {
  226. pinctrl-names = "default";
  227. pinctrl-0 = <&pinctrl_enet>;
  228. phy-mode = "rgmii";
  229. /delete-property/ interrupts;
  230. interrupts-extended = <&gpio1 6 IRQ_TYPE_LEVEL_HIGH>,
  231. <&intc 0 119 IRQ_TYPE_LEVEL_HIGH>;
  232. fsl,err006687-workaround-present;
  233. status = "okay";
  234. };
  235. &hdmi {
  236. ddc-i2c-bus = <&i2c2>;
  237. status = "okay";
  238. };
  239. &i2c1 {
  240. clock-frequency = <100000>;
  241. pinctrl-names = "default";
  242. pinctrl-0 = <&pinctrl_i2c1>;
  243. status = "okay";
  244. codec: sgtl5000@a {
  245. compatible = "fsl,sgtl5000";
  246. pinctrl-names = "default";
  247. pinctrl-0 = <&pinctrl_sgtl5000>;
  248. reg = <0x0a>;
  249. clocks = <&clks IMX6QDL_CLK_CKO>;
  250. VDDA-supply = <&reg_2p5v>;
  251. VDDIO-supply = <&reg_3p3v>;
  252. };
  253. rtc@68 {
  254. compatible = "microcrystal,rv4162";
  255. pinctrl-names = "default";
  256. pinctrl-0 = <&pinctrl_rv4162>;
  257. reg = <0x68>;
  258. interrupts-extended = <&gpio6 7 IRQ_TYPE_LEVEL_LOW>;
  259. };
  260. };
  261. &i2c2 {
  262. clock-frequency = <100000>;
  263. pinctrl-names = "default";
  264. pinctrl-0 = <&pinctrl_i2c2>;
  265. status = "okay";
  266. };
  267. &i2c3 {
  268. clock-frequency = <100000>;
  269. pinctrl-names = "default";
  270. pinctrl-0 = <&pinctrl_i2c3>;
  271. status = "okay";
  272. touchscreen@4 {
  273. compatible = "eeti,egalax_ts";
  274. reg = <0x04>;
  275. interrupt-parent = <&gpio1>;
  276. interrupts = <9 IRQ_TYPE_EDGE_FALLING>;
  277. wakeup-gpios = <&gpio1 9 GPIO_ACTIVE_LOW>;
  278. };
  279. touchscreen@38 {
  280. compatible = "edt,edt-ft5x06";
  281. reg = <0x38>;
  282. interrupt-parent = <&gpio1>;
  283. interrupts = <9 IRQ_TYPE_EDGE_FALLING>;
  284. wakeup-source;
  285. };
  286. };
  287. &iomuxc {
  288. pinctrl_audmux: audmuxgrp {
  289. fsl,pins = <
  290. MX6QDL_PAD_CSI0_DAT7__AUD3_RXD 0x130b0
  291. MX6QDL_PAD_CSI0_DAT4__AUD3_TXC 0x130b0
  292. MX6QDL_PAD_CSI0_DAT5__AUD3_TXD 0x110b0
  293. MX6QDL_PAD_CSI0_DAT6__AUD3_TXFS 0x130b0
  294. >;
  295. };
  296. pinctrl_backlight_lvds1: backlight-lvds1grp {
  297. fsl,pins = <
  298. MX6QDL_PAD_EIM_EB3__GPIO2_IO31 0x0b0b0
  299. >;
  300. };
  301. pinctrl_can1: can1grp {
  302. fsl,pins = <
  303. MX6QDL_PAD_KEY_COL2__FLEXCAN1_TX 0x1b0b0
  304. MX6QDL_PAD_KEY_ROW2__FLEXCAN1_RX 0x1b0b0
  305. >;
  306. };
  307. pinctrl_can_xcvr: can-xcvrgrp {
  308. fsl,pins = <
  309. /* Flexcan XCVR enable */
  310. MX6QDL_PAD_GPIO_2__GPIO1_IO02 0x0b0b0
  311. >;
  312. };
  313. pinctrl_ecspi1: ecspi1grp {
  314. fsl,pins = <
  315. MX6QDL_PAD_EIM_D17__ECSPI1_MISO 0x100b1
  316. MX6QDL_PAD_EIM_D18__ECSPI1_MOSI 0x100b1
  317. MX6QDL_PAD_EIM_D16__ECSPI1_SCLK 0x100b1
  318. MX6QDL_PAD_EIM_D19__GPIO3_IO19 0x000b1
  319. >;
  320. };
  321. pinctrl_enet: enetgrp {
  322. fsl,pins = <
  323. MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0
  324. MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0
  325. MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x100b0
  326. MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x100b0
  327. MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x100b0
  328. MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x100b0
  329. MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x100b0
  330. MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x100b0
  331. MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x100b0
  332. MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b0b0
  333. MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x130b0
  334. MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b0b0
  335. MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x130b0
  336. MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b0b0
  337. MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x130b0
  338. MX6QDL_PAD_ENET_RXD0__GPIO1_IO27 0x030b0
  339. MX6QDL_PAD_ENET_TX_EN__GPIO1_IO28 0x1b0b0
  340. MX6QDL_PAD_GPIO_6__ENET_IRQ 0x000b1
  341. >;
  342. };
  343. pinctrl_gpio_keys: gpio-keysgrp {
  344. fsl,pins = <
  345. /* Power Button */
  346. MX6QDL_PAD_NANDF_D3__GPIO2_IO03 0x1b0b0
  347. /* Menu Button */
  348. MX6QDL_PAD_NANDF_D1__GPIO2_IO01 0x1b0b0
  349. /* Home Button */
  350. MX6QDL_PAD_NANDF_D4__GPIO2_IO04 0x1b0b0
  351. /* Back Button */
  352. MX6QDL_PAD_NANDF_D2__GPIO2_IO02 0x1b0b0
  353. /* Volume Up Button */
  354. MX6QDL_PAD_GPIO_18__GPIO7_IO13 0x1b0b0
  355. /* Volume Down Button */
  356. MX6QDL_PAD_SD3_DAT4__GPIO7_IO01 0x1b0b0
  357. >;
  358. };
  359. pinctrl_i2c1: i2c1grp {
  360. fsl,pins = <
  361. MX6QDL_PAD_EIM_D21__I2C1_SCL 0x4001b8b1
  362. MX6QDL_PAD_EIM_D28__I2C1_SDA 0x4001b8b1
  363. >;
  364. };
  365. pinctrl_i2c2: i2c2grp {
  366. fsl,pins = <
  367. MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1
  368. MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1
  369. >;
  370. };
  371. pinctrl_i2c3: i2c3grp {
  372. fsl,pins = <
  373. MX6QDL_PAD_GPIO_5__I2C3_SCL 0x4001b8b1
  374. MX6QDL_PAD_GPIO_16__I2C3_SDA 0x4001b8b1
  375. MX6QDL_PAD_GPIO_9__GPIO1_IO09 0x1b0b0
  376. >;
  377. };
  378. pinctrl_i2c3mux: i2c3muxgrp {
  379. fsl,pins = <
  380. /* PCIe I2C enable */
  381. MX6QDL_PAD_EIM_OE__GPIO2_IO25 0x000b0
  382. >;
  383. };
  384. pinctrl_j15: j15grp {
  385. fsl,pins = <
  386. MX6QDL_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK 0x10
  387. MX6QDL_PAD_DI0_PIN15__IPU1_DI0_PIN15 0x10
  388. MX6QDL_PAD_DI0_PIN2__IPU1_DI0_PIN02 0x10
  389. MX6QDL_PAD_DI0_PIN3__IPU1_DI0_PIN03 0x10
  390. MX6QDL_PAD_DISP0_DAT0__IPU1_DISP0_DATA00 0x10
  391. MX6QDL_PAD_DISP0_DAT1__IPU1_DISP0_DATA01 0x10
  392. MX6QDL_PAD_DISP0_DAT2__IPU1_DISP0_DATA02 0x10
  393. MX6QDL_PAD_DISP0_DAT3__IPU1_DISP0_DATA03 0x10
  394. MX6QDL_PAD_DISP0_DAT4__IPU1_DISP0_DATA04 0x10
  395. MX6QDL_PAD_DISP0_DAT5__IPU1_DISP0_DATA05 0x10
  396. MX6QDL_PAD_DISP0_DAT6__IPU1_DISP0_DATA06 0x10
  397. MX6QDL_PAD_DISP0_DAT7__IPU1_DISP0_DATA07 0x10
  398. MX6QDL_PAD_DISP0_DAT8__IPU1_DISP0_DATA08 0x10
  399. MX6QDL_PAD_DISP0_DAT9__IPU1_DISP0_DATA09 0x10
  400. MX6QDL_PAD_DISP0_DAT10__IPU1_DISP0_DATA10 0x10
  401. MX6QDL_PAD_DISP0_DAT11__IPU1_DISP0_DATA11 0x10
  402. MX6QDL_PAD_DISP0_DAT12__IPU1_DISP0_DATA12 0x10
  403. MX6QDL_PAD_DISP0_DAT13__IPU1_DISP0_DATA13 0x10
  404. MX6QDL_PAD_DISP0_DAT14__IPU1_DISP0_DATA14 0x10
  405. MX6QDL_PAD_DISP0_DAT15__IPU1_DISP0_DATA15 0x10
  406. MX6QDL_PAD_DISP0_DAT16__IPU1_DISP0_DATA16 0x10
  407. MX6QDL_PAD_DISP0_DAT17__IPU1_DISP0_DATA17 0x10
  408. MX6QDL_PAD_DISP0_DAT18__IPU1_DISP0_DATA18 0x10
  409. MX6QDL_PAD_DISP0_DAT19__IPU1_DISP0_DATA19 0x10
  410. MX6QDL_PAD_DISP0_DAT20__IPU1_DISP0_DATA20 0x10
  411. MX6QDL_PAD_DISP0_DAT21__IPU1_DISP0_DATA21 0x10
  412. MX6QDL_PAD_DISP0_DAT22__IPU1_DISP0_DATA22 0x10
  413. MX6QDL_PAD_DISP0_DAT23__IPU1_DISP0_DATA23 0x10
  414. >;
  415. };
  416. pinctrl_pcie: pciegrp {
  417. fsl,pins = <
  418. /* PCIe reset */
  419. MX6QDL_PAD_EIM_DA0__GPIO3_IO00 0x030b0
  420. MX6QDL_PAD_EIM_DA4__GPIO3_IO04 0x030b0
  421. >;
  422. };
  423. pinctrl_pwm1: pwm1grp {
  424. fsl,pins = <
  425. MX6QDL_PAD_SD1_DAT3__PWM1_OUT 0x030b1
  426. >;
  427. };
  428. pinctrl_pwm3: pwm3grp {
  429. fsl,pins = <
  430. MX6QDL_PAD_SD1_DAT1__PWM3_OUT 0x030b1
  431. >;
  432. };
  433. pinctrl_pwm4: pwm4grp {
  434. fsl,pins = <
  435. MX6QDL_PAD_SD1_CMD__PWM4_OUT 0x030b1
  436. >;
  437. };
  438. pinctrl_rv4162: rv4162grp {
  439. fsl,pins = <
  440. MX6QDL_PAD_NANDF_CLE__GPIO6_IO07 0x1b0b0
  441. >;
  442. };
  443. pinctrl_sgtl5000: sgtl5000grp {
  444. fsl,pins = <
  445. MX6QDL_PAD_GPIO_0__CCM_CLKO1 0x000b0
  446. MX6QDL_PAD_EIM_D29__GPIO3_IO29 0x130b0
  447. MX6QDL_PAD_EIM_DA2__GPIO3_IO02 0x130b0
  448. MX6QDL_PAD_ENET_RX_ER__GPIO1_IO24 0x130b0
  449. >;
  450. };
  451. pinctrl_uart1: uart1grp {
  452. fsl,pins = <
  453. MX6QDL_PAD_SD3_DAT7__UART1_TX_DATA 0x1b0b1
  454. MX6QDL_PAD_SD3_DAT6__UART1_RX_DATA 0x1b0b1
  455. >;
  456. };
  457. pinctrl_uart2: uart2grp {
  458. fsl,pins = <
  459. MX6QDL_PAD_EIM_D26__UART2_TX_DATA 0x1b0b1
  460. MX6QDL_PAD_EIM_D27__UART2_RX_DATA 0x1b0b1
  461. >;
  462. };
  463. pinctrl_uart3: uart3grp {
  464. fsl,pins = <
  465. MX6QDL_PAD_EIM_D24__UART3_TX_DATA 0x1b0b1
  466. MX6QDL_PAD_EIM_D25__UART3_RX_DATA 0x1b0b1
  467. MX6QDL_PAD_EIM_D23__UART3_CTS_B 0x1b0b1
  468. MX6QDL_PAD_EIM_D31__UART3_RTS_B 0x1b0b1
  469. >;
  470. };
  471. pinctrl_usbh1: usbh1grp {
  472. fsl,pins = <
  473. MX6QDL_PAD_GPIO_17__GPIO7_IO12 0x030b0
  474. >;
  475. };
  476. pinctrl_usbotg: usbotggrp {
  477. fsl,pins = <
  478. MX6QDL_PAD_GPIO_1__USB_OTG_ID 0x17059
  479. MX6QDL_PAD_KEY_COL4__USB_OTG_OC 0x1b0b0
  480. /* power enable, high active */
  481. MX6QDL_PAD_EIM_D22__GPIO3_IO22 0x030b0
  482. >;
  483. };
  484. pinctrl_usdhc2: usdhc2grp {
  485. fsl,pins = <
  486. MX6QDL_PAD_SD2_CLK__SD2_CLK 0x10071
  487. MX6QDL_PAD_SD2_CMD__SD2_CMD 0x17071
  488. MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x17071
  489. MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x17071
  490. MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x17071
  491. MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x17071
  492. >;
  493. };
  494. pinctrl_usdhc3: usdhc3grp {
  495. fsl,pins = <
  496. MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10071
  497. MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17071
  498. MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17071
  499. MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17071
  500. MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17071
  501. MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17071
  502. MX6QDL_PAD_SD3_DAT5__GPIO7_IO00 0x1b0b0
  503. >;
  504. };
  505. pinctrl_usdhc4: usdhc4grp {
  506. fsl,pins = <
  507. MX6QDL_PAD_SD4_CMD__SD4_CMD 0x17059
  508. MX6QDL_PAD_SD4_CLK__SD4_CLK 0x10059
  509. MX6QDL_PAD_SD4_DAT0__SD4_DATA0 0x17059
  510. MX6QDL_PAD_SD4_DAT1__SD4_DATA1 0x17059
  511. MX6QDL_PAD_SD4_DAT2__SD4_DATA2 0x17059
  512. MX6QDL_PAD_SD4_DAT3__SD4_DATA3 0x17059
  513. MX6QDL_PAD_SD4_DAT4__SD4_DATA4 0x17059
  514. MX6QDL_PAD_SD4_DAT5__SD4_DATA5 0x17059
  515. MX6QDL_PAD_SD4_DAT6__SD4_DATA6 0x17059
  516. MX6QDL_PAD_SD4_DAT7__SD4_DATA7 0x17059
  517. >;
  518. };
  519. pinctrl_wlan_vmmc: wlan-vmmcgrp {
  520. fsl,pins = <
  521. MX6QDL_PAD_NANDF_CS1__GPIO6_IO14 0x100b0
  522. MX6QDL_PAD_NANDF_CS2__GPIO6_IO15 0x030b0
  523. MX6QDL_PAD_NANDF_CS3__GPIO6_IO16 0x030b0
  524. MX6QDL_PAD_SD1_CLK__OSC32K_32K_OUT 0x000b0
  525. >;
  526. };
  527. };
  528. &ipu1_di0_disp0 {
  529. remote-endpoint = <&lcd_display_in>;
  530. };
  531. &ldb {
  532. status = "okay";
  533. lvds-channel@0 {
  534. status = "okay";
  535. port@4 {
  536. reg = <4>;
  537. lvds0_out: endpoint {
  538. remote-endpoint = <&panel_in_lvds0>;
  539. };
  540. };
  541. };
  542. lvds-channel@1 {
  543. fsl,data-mapping = "spwg";
  544. fsl,data-width = <18>;
  545. status = "okay";
  546. port@4 {
  547. reg = <4>;
  548. lvds1_out: endpoint {
  549. remote-endpoint = <&panel_in_lvds1>;
  550. };
  551. };
  552. };
  553. };
  554. &pcie {
  555. pinctrl-names = "default";
  556. pinctrl-0 = <&pinctrl_pcie>;
  557. reset-gpio = <&gpio3 0 GPIO_ACTIVE_LOW>;
  558. status = "okay";
  559. };
  560. &pwm1 {
  561. #pwm-cells = <2>;
  562. pinctrl-names = "default";
  563. pinctrl-0 = <&pinctrl_pwm1>;
  564. status = "okay";
  565. };
  566. &pwm3 {
  567. pinctrl-names = "default";
  568. pinctrl-0 = <&pinctrl_pwm3>;
  569. status = "okay";
  570. };
  571. &pwm4 {
  572. #pwm-cells = <2>;
  573. pinctrl-names = "default";
  574. pinctrl-0 = <&pinctrl_pwm4>;
  575. status = "okay";
  576. };
  577. &ssi1 {
  578. status = "okay";
  579. };
  580. &uart1 {
  581. pinctrl-names = "default";
  582. pinctrl-0 = <&pinctrl_uart1>;
  583. status = "okay";
  584. };
  585. &uart2 {
  586. pinctrl-names = "default";
  587. pinctrl-0 = <&pinctrl_uart2>;
  588. status = "okay";
  589. };
  590. &uart3 {
  591. pinctrl-names = "default";
  592. pinctrl-0 = <&pinctrl_uart3>;
  593. uart-has-rtscts;
  594. status = "okay";
  595. };
  596. &usbh1 {
  597. vbus-supply = <&reg_usb_h1_vbus>;
  598. status = "okay";
  599. };
  600. &usbotg {
  601. vbus-supply = <&reg_usb_otg_vbus>;
  602. pinctrl-names = "default";
  603. pinctrl-0 = <&pinctrl_usbotg>;
  604. disable-over-current;
  605. status = "okay";
  606. };
  607. &usdhc2 {
  608. pinctrl-names = "default";
  609. pinctrl-0 = <&pinctrl_usdhc2>;
  610. bus-width = <4>;
  611. non-removable;
  612. vmmc-supply = <&reg_wlan_vmmc>;
  613. cap-power-off-card;
  614. keep-power-in-suspend;
  615. status = "okay";
  616. #address-cells = <1>;
  617. #size-cells = <0>;
  618. wlcore: wlcore@2 {
  619. compatible = "ti,wl1271";
  620. reg = <2>;
  621. interrupt-parent = <&gpio6>;
  622. interrupts = <14 IRQ_TYPE_LEVEL_HIGH>;
  623. ref-clock-frequency = <38400000>;
  624. };
  625. };
  626. &usdhc3 {
  627. pinctrl-names = "default";
  628. pinctrl-0 = <&pinctrl_usdhc3>;
  629. cd-gpios = <&gpio7 0 GPIO_ACTIVE_LOW>;
  630. bus-width = <4>;
  631. vmmc-supply = <&reg_3p3v>;
  632. status = "okay";
  633. };
  634. &usdhc4 {
  635. pinctrl-names = "default";
  636. pinctrl-0 = <&pinctrl_usdhc4>;
  637. bus-width = <8>;
  638. non-removable;
  639. vmmc-supply = <&reg_1p8v>;
  640. keep-power-in-suspend;
  641. status = "okay";
  642. };