imx6qdl-gw5910.dtsi 14 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. /*
  3. * Copyright 2019 Gateworks Corporation
  4. */
  5. #include <dt-bindings/gpio/gpio.h>
  6. #include <dt-bindings/input/linux-event-codes.h>
  7. #include <dt-bindings/interrupt-controller/irq.h>
  8. / {
  9. /* these are used by bootloader for disabling nodes */
  10. aliases {
  11. led0 = &led0;
  12. led1 = &led1;
  13. led2 = &led2;
  14. };
  15. chosen {
  16. stdout-path = &uart2;
  17. };
  18. memory@10000000 {
  19. device_type = "memory";
  20. reg = <0x10000000 0x20000000>;
  21. };
  22. gpio-keys {
  23. compatible = "gpio-keys";
  24. user-pb {
  25. label = "user_pb";
  26. gpios = <&gsc_gpio 2 GPIO_ACTIVE_LOW>;
  27. linux,code = <BTN_0>;
  28. };
  29. user-pb1x {
  30. label = "user_pb1x";
  31. linux,code = <BTN_1>;
  32. interrupt-parent = <&gsc>;
  33. interrupts = <0>;
  34. };
  35. key-erased {
  36. label = "key-erased";
  37. linux,code = <BTN_2>;
  38. interrupt-parent = <&gsc>;
  39. interrupts = <1>;
  40. };
  41. eeprom-wp {
  42. label = "eeprom_wp";
  43. linux,code = <BTN_3>;
  44. interrupt-parent = <&gsc>;
  45. interrupts = <2>;
  46. };
  47. tamper {
  48. label = "tamper";
  49. linux,code = <BTN_4>;
  50. interrupt-parent = <&gsc>;
  51. interrupts = <5>;
  52. };
  53. switch-hold {
  54. label = "switch_hold";
  55. linux,code = <BTN_5>;
  56. interrupt-parent = <&gsc>;
  57. interrupts = <7>;
  58. };
  59. };
  60. leds {
  61. compatible = "gpio-leds";
  62. pinctrl-names = "default";
  63. pinctrl-0 = <&pinctrl_gpio_leds>;
  64. led0: led-user1 {
  65. label = "user1";
  66. gpios = <&gpio4 6 GPIO_ACTIVE_HIGH>; /* MX6_PANLEDG */
  67. default-state = "on";
  68. linux,default-trigger = "heartbeat";
  69. };
  70. led1: led-user2 {
  71. label = "user2";
  72. gpios = <&gpio4 7 GPIO_ACTIVE_HIGH>; /* MX6_PANLEDR */
  73. default-state = "off";
  74. };
  75. led2: led-user3 {
  76. label = "user3";
  77. gpios = <&gpio4 15 GPIO_ACTIVE_LOW>; /* MX6_LOCLED# */
  78. default-state = "off";
  79. };
  80. };
  81. pps {
  82. compatible = "pps-gpio";
  83. pinctrl-names = "default";
  84. pinctrl-0 = <&pinctrl_pps>;
  85. gpios = <&gpio4 16 GPIO_ACTIVE_HIGH>;
  86. status = "okay";
  87. };
  88. reg_3p3v: regulator-3p3v {
  89. compatible = "regulator-fixed";
  90. regulator-name = "3P3V";
  91. regulator-min-microvolt = <3300000>;
  92. regulator-max-microvolt = <3300000>;
  93. regulator-always-on;
  94. };
  95. reg_5p0v: regulator-5p0v {
  96. compatible = "regulator-fixed";
  97. regulator-name = "5P0V";
  98. regulator-min-microvolt = <5000000>;
  99. regulator-max-microvolt = <5000000>;
  100. regulator-always-on;
  101. };
  102. reg_wl: regulator-wl {
  103. pinctrl-names = "default";
  104. pinctrl-0 = <&pinctrl_reg_wl>;
  105. compatible = "regulator-fixed";
  106. regulator-name = "wl";
  107. gpio = <&gpio1 5 GPIO_ACTIVE_HIGH>;
  108. startup-delay-us = <100>;
  109. enable-active-high;
  110. regulator-min-microvolt = <3300000>;
  111. regulator-max-microvolt = <3300000>;
  112. };
  113. };
  114. &ecspi3 {
  115. cs-gpios = <&gpio4 24 GPIO_ACTIVE_LOW>;
  116. pinctrl-names = "default";
  117. pinctrl-0 = <&pinctrl_ecspi3>;
  118. status = "okay";
  119. };
  120. &fec {
  121. pinctrl-names = "default";
  122. pinctrl-0 = <&pinctrl_enet>;
  123. phy-mode = "rgmii-id";
  124. status = "okay";
  125. };
  126. &gpmi {
  127. pinctrl-names = "default";
  128. pinctrl-0 = <&pinctrl_gpmi_nand>;
  129. status = "okay";
  130. };
  131. &i2c1 {
  132. clock-frequency = <100000>;
  133. pinctrl-names = "default";
  134. pinctrl-0 = <&pinctrl_i2c1>;
  135. status = "okay";
  136. gsc: gsc@20 {
  137. compatible = "gw,gsc";
  138. reg = <0x20>;
  139. interrupt-parent = <&gpio1>;
  140. interrupts = <4 IRQ_TYPE_LEVEL_LOW>;
  141. interrupt-controller;
  142. #interrupt-cells = <1>;
  143. #size-cells = <0>;
  144. adc {
  145. compatible = "gw,gsc-adc";
  146. #address-cells = <1>;
  147. #size-cells = <0>;
  148. channel@6 {
  149. gw,mode = <0>;
  150. reg = <0x06>;
  151. label = "temp";
  152. };
  153. channel@8 {
  154. gw,mode = <3>;
  155. reg = <0x08>;
  156. label = "vdd_bat";
  157. };
  158. channel@82 {
  159. gw,mode = <2>;
  160. reg = <0x82>;
  161. label = "vdd_vin";
  162. gw,voltage-divider-ohms = <22100 1000>;
  163. gw,voltage-offset-microvolt = <800000>;
  164. };
  165. channel@84 {
  166. gw,mode = <2>;
  167. reg = <0x84>;
  168. label = "vdd_5p0";
  169. gw,voltage-divider-ohms = <22100 10000>;
  170. };
  171. channel@86 {
  172. gw,mode = <2>;
  173. reg = <0x86>;
  174. label = "vdd_3p3";
  175. gw,voltage-divider-ohms = <10000 10000>;
  176. };
  177. channel@88 {
  178. gw,mode = <2>;
  179. reg = <0x88>;
  180. label = "vdd_2p5";
  181. gw,voltage-divider-ohms = <10000 10000>;
  182. };
  183. channel@8c {
  184. gw,mode = <2>;
  185. reg = <0x8c>;
  186. label = "vdd_3p0";
  187. };
  188. channel@8e {
  189. gw,mode = <2>;
  190. reg = <0x8e>;
  191. label = "vdd_arm";
  192. };
  193. channel@90 {
  194. gw,mode = <2>;
  195. reg = <0x90>;
  196. label = "vdd_soc";
  197. };
  198. channel@92 {
  199. gw,mode = <2>;
  200. reg = <0x92>;
  201. label = "vdd_1p5";
  202. };
  203. channel@98 {
  204. gw,mode = <2>;
  205. reg = <0x98>;
  206. label = "vdd_1p8";
  207. };
  208. channel@9a {
  209. gw,mode = <2>;
  210. reg = <0x9a>;
  211. label = "vdd_1p0";
  212. gw,voltage-divider-ohms = <10000 10000>;
  213. };
  214. channel@9c {
  215. gw,mode = <2>;
  216. reg = <0x9c>;
  217. label = "vdd_an1";
  218. gw,voltage-divider-ohms = <10000 10000>;
  219. };
  220. channel@a2 {
  221. gw,mode = <2>;
  222. reg = <0xa2>;
  223. label = "vdd_gsc";
  224. gw,voltage-divider-ohms = <10000 10000>;
  225. };
  226. };
  227. };
  228. gsc_gpio: gpio@23 {
  229. compatible = "nxp,pca9555";
  230. reg = <0x23>;
  231. gpio-controller;
  232. #gpio-cells = <2>;
  233. interrupt-parent = <&gsc>;
  234. interrupts = <4>;
  235. };
  236. eeprom@50 {
  237. compatible = "atmel,24c02";
  238. reg = <0x50>;
  239. pagesize = <16>;
  240. };
  241. eeprom@51 {
  242. compatible = "atmel,24c02";
  243. reg = <0x51>;
  244. pagesize = <16>;
  245. };
  246. eeprom@52 {
  247. compatible = "atmel,24c02";
  248. reg = <0x52>;
  249. pagesize = <16>;
  250. };
  251. eeprom@53 {
  252. compatible = "atmel,24c02";
  253. reg = <0x53>;
  254. pagesize = <16>;
  255. };
  256. rtc@68 {
  257. compatible = "dallas,ds1672";
  258. reg = <0x68>;
  259. };
  260. };
  261. &i2c2 {
  262. clock-frequency = <100000>;
  263. pinctrl-names = "default";
  264. pinctrl-0 = <&pinctrl_i2c2>;
  265. status = "okay";
  266. };
  267. &i2c3 {
  268. clock-frequency = <100000>;
  269. pinctrl-names = "default";
  270. pinctrl-0 = <&pinctrl_i2c3>;
  271. status = "okay";
  272. accel@19 {
  273. pinctrl-names = "default";
  274. pinctrl-0 = <&pinctrl_accel>;
  275. compatible = "st,lis2de12";
  276. reg = <0x19>;
  277. st,drdy-int-pin = <1>;
  278. interrupt-parent = <&gpio7>;
  279. interrupts = <13 0>;
  280. interrupt-names = "INT1";
  281. };
  282. };
  283. &pcie {
  284. pinctrl-names = "default";
  285. pinctrl-0 = <&pinctrl_pcie>;
  286. reset-gpio = <&gpio3 20 GPIO_ACTIVE_LOW>;
  287. status = "okay";
  288. };
  289. &pwm2 {
  290. pinctrl-names = "default";
  291. pinctrl-0 = <&pinctrl_pwm2>; /* MX6_DIO1 */
  292. status = "disabled";
  293. };
  294. &pwm3 {
  295. pinctrl-names = "default";
  296. pinctrl-0 = <&pinctrl_pwm3>; /* MX6_DIO2 */
  297. status = "disabled";
  298. };
  299. /* off-board RS232 */
  300. &uart1 {
  301. pinctrl-names = "default";
  302. pinctrl-0 = <&pinctrl_uart1>;
  303. status = "okay";
  304. };
  305. /* serial console */
  306. &uart2 {
  307. pinctrl-names = "default";
  308. pinctrl-0 = <&pinctrl_uart2>;
  309. status = "okay";
  310. };
  311. /* cc1352 */
  312. &uart3 {
  313. pinctrl-names = "default";
  314. pinctrl-0 = <&pinctrl_uart3>;
  315. uart-has-rtscts;
  316. status = "okay";
  317. };
  318. /* Sterling-LWB Bluetooth */
  319. &uart4 {
  320. pinctrl-names = "default";
  321. pinctrl-0 = <&pinctrl_uart4>,<&pinctrl_bten>;
  322. uart-has-rtscts;
  323. status = "okay";
  324. bluetooth {
  325. compatible = "brcm,bcm4330-bt";
  326. shutdown-gpios = <&gpio1 2 GPIO_ACTIVE_HIGH>;
  327. };
  328. };
  329. /* GPS */
  330. &uart5 {
  331. pinctrl-names = "default";
  332. pinctrl-0 = <&pinctrl_uart5>;
  333. status = "okay";
  334. };
  335. &usbotg {
  336. vbus-supply = <&reg_5p0v>;
  337. pinctrl-names = "default";
  338. pinctrl-0 = <&pinctrl_usbotg>;
  339. disable-over-current;
  340. status = "okay";
  341. };
  342. &usbh1 {
  343. status = "okay";
  344. };
  345. /* Sterling-LWB SDIO WiFi */
  346. &usdhc2 {
  347. pinctrl-names = "default";
  348. pinctrl-0 = <&pinctrl_usdhc2>;
  349. vmmc-supply = <&reg_wl>;
  350. non-removable;
  351. bus-width = <4>;
  352. status = "okay";
  353. };
  354. &usdhc3 {
  355. pinctrl-names = "default", "state_100mhz", "state_200mhz";
  356. pinctrl-0 = <&pinctrl_usdhc3>;
  357. pinctrl-1 = <&pinctrl_usdhc3_100mhz>;
  358. pinctrl-2 = <&pinctrl_usdhc3_200mhz>;
  359. cd-gpios = <&gpio7 0 GPIO_ACTIVE_LOW>;
  360. vmmc-supply = <&reg_3p3v>;
  361. status = "okay";
  362. };
  363. &wdog1 {
  364. pinctrl-names = "default";
  365. pinctrl-0 = <&pinctrl_wdog>;
  366. fsl,ext-reset-output;
  367. };
  368. &iomuxc {
  369. pinctrl_accel: accelmuxgrp {
  370. fsl,pins = <
  371. MX6QDL_PAD_GPIO_18__GPIO7_IO13 0x1b0b1
  372. >;
  373. };
  374. pinctrl_bten: btengrp {
  375. fsl,pins = <
  376. MX6QDL_PAD_GPIO_2__GPIO1_IO02 0x1b0b1
  377. >;
  378. };
  379. pinctrl_ecspi3: escpi3grp {
  380. fsl,pins = <
  381. MX6QDL_PAD_DISP0_DAT0__ECSPI3_SCLK 0x100b1
  382. MX6QDL_PAD_DISP0_DAT1__ECSPI3_MOSI 0x100b1
  383. MX6QDL_PAD_DISP0_DAT2__ECSPI3_MISO 0x100b1
  384. MX6QDL_PAD_DISP0_DAT3__GPIO4_IO24 0x100b1
  385. >;
  386. };
  387. pinctrl_enet: enetgrp {
  388. fsl,pins = <
  389. MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b030
  390. MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b030
  391. MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b030
  392. MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b030
  393. MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b030
  394. MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b030
  395. MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b030
  396. MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b030
  397. MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b030
  398. MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b030
  399. MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b030
  400. MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b030
  401. MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0
  402. MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0
  403. MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0
  404. MX6QDL_PAD_GPIO_16__ENET_REF_CLK 0x4001b0a8
  405. MX6QDL_PAD_ENET_TXD0__GPIO1_IO30 0x1b0b0
  406. >;
  407. };
  408. pinctrl_gpio_leds: gpioledsgrp {
  409. fsl,pins = <
  410. MX6QDL_PAD_KEY_COL0__GPIO4_IO06 0x1b0b0
  411. MX6QDL_PAD_KEY_ROW0__GPIO4_IO07 0x1b0b0
  412. MX6QDL_PAD_KEY_ROW4__GPIO4_IO15 0x1b0b0
  413. >;
  414. };
  415. pinctrl_gpmi_nand: gpminandgrp {
  416. fsl,pins = <
  417. MX6QDL_PAD_NANDF_CLE__NAND_CLE 0xb0b1
  418. MX6QDL_PAD_NANDF_ALE__NAND_ALE 0xb0b1
  419. MX6QDL_PAD_NANDF_WP_B__NAND_WP_B 0xb0b1
  420. MX6QDL_PAD_NANDF_RB0__NAND_READY_B 0xb000
  421. MX6QDL_PAD_NANDF_CS0__NAND_CE0_B 0xb0b1
  422. MX6QDL_PAD_SD4_CMD__NAND_RE_B 0xb0b1
  423. MX6QDL_PAD_SD4_CLK__NAND_WE_B 0xb0b1
  424. MX6QDL_PAD_NANDF_D0__NAND_DATA00 0xb0b1
  425. MX6QDL_PAD_NANDF_D1__NAND_DATA01 0xb0b1
  426. MX6QDL_PAD_NANDF_D2__NAND_DATA02 0xb0b1
  427. MX6QDL_PAD_NANDF_D3__NAND_DATA03 0xb0b1
  428. MX6QDL_PAD_NANDF_D4__NAND_DATA04 0xb0b1
  429. MX6QDL_PAD_NANDF_D5__NAND_DATA05 0xb0b1
  430. MX6QDL_PAD_NANDF_D6__NAND_DATA06 0xb0b1
  431. MX6QDL_PAD_NANDF_D7__NAND_DATA07 0xb0b1
  432. >;
  433. };
  434. pinctrl_i2c1: i2c1grp {
  435. fsl,pins = <
  436. MX6QDL_PAD_EIM_D21__I2C1_SCL 0x4001b8b1
  437. MX6QDL_PAD_EIM_D28__I2C1_SDA 0x4001b8b1
  438. MX6QDL_PAD_GPIO_4__GPIO1_IO04 0x0001b0b0
  439. >;
  440. };
  441. pinctrl_i2c2: i2c2grp {
  442. fsl,pins = <
  443. MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1
  444. MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1
  445. >;
  446. };
  447. pinctrl_i2c3: i2c3grp {
  448. fsl,pins = <
  449. MX6QDL_PAD_GPIO_3__I2C3_SCL 0x4001b8b1
  450. MX6QDL_PAD_GPIO_6__I2C3_SDA 0x4001b8b1
  451. >;
  452. };
  453. pinctrl_pcie: pciegrp {
  454. fsl,pins = <
  455. MX6QDL_PAD_EIM_D20__GPIO3_IO20 0x1b0b0
  456. >;
  457. };
  458. pinctrl_pps: ppsgrp {
  459. fsl,pins = <
  460. MX6QDL_PAD_DI0_DISP_CLK__GPIO4_IO16 0x1b0b1
  461. >;
  462. };
  463. pinctrl_pwm2: pwm2grp {
  464. fsl,pins = <
  465. MX6QDL_PAD_SD1_DAT2__PWM2_OUT 0x1b0b1
  466. >;
  467. };
  468. pinctrl_pwm3: pwm3grp {
  469. fsl,pins = <
  470. MX6QDL_PAD_SD1_DAT1__PWM3_OUT 0x1b0b1
  471. >;
  472. };
  473. pinctrl_reg_wl: regwlgrp {
  474. fsl,pins = <
  475. MX6QDL_PAD_GPIO_5__GPIO1_IO05 0x1b0b1
  476. >;
  477. };
  478. pinctrl_uart1: uart1grp {
  479. fsl,pins = <
  480. MX6QDL_PAD_CSI0_DAT10__UART1_TX_DATA 0x1b0b1
  481. MX6QDL_PAD_CSI0_DAT11__UART1_RX_DATA 0x1b0b1
  482. >;
  483. };
  484. pinctrl_uart2: uart2grp {
  485. fsl,pins = <
  486. MX6QDL_PAD_SD4_DAT7__UART2_TX_DATA 0x1b0b1
  487. MX6QDL_PAD_SD4_DAT4__UART2_RX_DATA 0x1b0b1
  488. >;
  489. };
  490. pinctrl_uart3: uart3grp {
  491. fsl,pins = <
  492. MX6QDL_PAD_EIM_D24__UART3_TX_DATA 0x1b0b1
  493. MX6QDL_PAD_EIM_D25__UART3_RX_DATA 0x1b0b1
  494. MX6QDL_PAD_EIM_D23__UART3_RTS_B 0x1b0b1
  495. MX6QDL_PAD_EIM_D31__UART3_CTS_B 0x1b0b1
  496. MX6QDL_PAD_EIM_A25__GPIO5_IO02 0x4001b0b1 /* DIO20 */
  497. MX6QDL_PAD_DISP0_DAT11__GPIO5_IO05 0x4001b0b1 /* DIO14 */
  498. MX6QDL_PAD_DISP0_DAT12__GPIO5_IO06 0x4001b0b1 /* DIO15 */
  499. MX6QDL_PAD_DISP0_DAT14__GPIO5_IO08 0x1b0b1 /* TMS */
  500. MX6QDL_PAD_DISP0_DAT15__GPIO5_IO09 0x1b0b1 /* TCK */
  501. MX6QDL_PAD_DISP0_DAT16__GPIO5_IO10 0x1b0b1 /* TDO */
  502. MX6QDL_PAD_DISP0_DAT17__GPIO5_IO11 0x1b0b1 /* TDI */
  503. MX6QDL_PAD_DISP0_DAT23__GPIO5_IO17 0x4001b0b1 /* RST# */
  504. >;
  505. };
  506. pinctrl_uart4: uart4grp {
  507. fsl,pins = <
  508. MX6QDL_PAD_CSI0_DAT12__UART4_TX_DATA 0x1b0b1
  509. MX6QDL_PAD_CSI0_DAT13__UART4_RX_DATA 0x1b0b1
  510. MX6QDL_PAD_CSI0_DAT16__UART4_RTS_B 0x1b0b1
  511. MX6QDL_PAD_CSI0_DAT17__UART4_CTS_B 0x1b0b1
  512. >;
  513. };
  514. pinctrl_uart5: uart5grp {
  515. fsl,pins = <
  516. MX6QDL_PAD_KEY_COL1__UART5_TX_DATA 0x1b0b1
  517. MX6QDL_PAD_KEY_ROW1__UART5_RX_DATA 0x1b0b1
  518. >;
  519. };
  520. pinctrl_usbotg: usbotggrp {
  521. fsl,pins = <
  522. MX6QDL_PAD_GPIO_1__USB_OTG_ID 0x13059
  523. >;
  524. };
  525. pinctrl_usdhc2: usdhc2grp {
  526. fsl,pins = <
  527. MX6QDL_PAD_SD2_CMD__SD2_CMD 0x17059
  528. MX6QDL_PAD_SD2_CLK__SD2_CLK 0x10059
  529. MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x17059
  530. MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x17059
  531. MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x17059
  532. MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x17059
  533. >;
  534. };
  535. pinctrl_usdhc3: usdhc3grp {
  536. fsl,pins = <
  537. MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059
  538. MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10059
  539. MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059
  540. MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059
  541. MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059
  542. MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059
  543. MX6QDL_PAD_SD3_DAT5__GPIO7_IO00 0x17059 /* CD */
  544. MX6QDL_PAD_NANDF_CS1__SD3_VSELECT 0x17059
  545. >;
  546. };
  547. pinctrl_usdhc3_100mhz: usdhc3grp100mhz {
  548. fsl,pins = <
  549. MX6QDL_PAD_SD3_CMD__SD3_CMD 0x170b9
  550. MX6QDL_PAD_SD3_CLK__SD3_CLK 0x170b9
  551. MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x170b9
  552. MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x170b9
  553. MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x170b9
  554. MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x170b9
  555. MX6QDL_PAD_SD3_DAT5__GPIO7_IO00 0x170b9 /* CD */
  556. MX6QDL_PAD_NANDF_CS1__SD3_VSELECT 0x170b9
  557. >;
  558. };
  559. pinctrl_usdhc3_200mhz: usdhc3grp200mhz {
  560. fsl,pins = <
  561. MX6QDL_PAD_SD3_CMD__SD3_CMD 0x170f9
  562. MX6QDL_PAD_SD3_CLK__SD3_CLK 0x100f9
  563. MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x170f9
  564. MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x170f9
  565. MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x170f9
  566. MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x170f9
  567. MX6QDL_PAD_SD3_DAT5__GPIO7_IO00 0x170f9 /* CD */
  568. MX6QDL_PAD_NANDF_CS1__SD3_VSELECT 0x170f9
  569. >;
  570. };
  571. pinctrl_wdog: wdoggrp {
  572. fsl,pins = <
  573. MX6QDL_PAD_DISP0_DAT8__WDOG1_B 0x1b0b0
  574. >;
  575. };
  576. };