imx6qdl-emcon.dtsi 18 KB

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  1. // SPDX-License-Identifier: (GPL-2.0 or MIT)
  2. //
  3. // Copyright (C) 2018 emtrion GmbH
  4. //
  5. #include <dt-bindings/gpio/gpio.h>
  6. #include <dt-bindings/pwm/pwm.h>
  7. #include <dt-bindings/input/input.h>
  8. / {
  9. model = "emtrion SoM emCON-MX6";
  10. compatible = "emtrion,emcon-mx6";
  11. aliases {
  12. mmc0 = &usdhc3;
  13. mmc1 = &usdhc2;
  14. mmc2 = &usdhc1;
  15. rtc0 = &ds1307;
  16. };
  17. chosen {
  18. stdout-path = &uart1;
  19. };
  20. memory@10000000 {
  21. device_type = "memory";
  22. reg = <0x10000000 0x40000000>;
  23. };
  24. gpio-keys {
  25. compatible = "gpio-keys";
  26. pinctrl-names = "default";
  27. pinctrl-0 = <&pinctrl_emcon_wake>;
  28. wake {
  29. label = "Wake";
  30. linux,code = <KEY_WAKEUP>;
  31. gpios = <&gpio3 2 GPIO_ACTIVE_LOW>;
  32. wakeup-source;
  33. };
  34. };
  35. som_leds: leds {
  36. compatible = "gpio-leds";
  37. pinctrl-names = "default";
  38. pinctrl-0 = <&pinctrl_som_leds>;
  39. led-green {
  40. label = "som:green";
  41. gpios = <&gpio3 0 GPIO_ACTIVE_HIGH>;
  42. linux,default-trigger = "heartbeat";
  43. default-state = "on";
  44. };
  45. led-red {
  46. label = "som:red";
  47. gpios = <&gpio3 1 GPIO_ACTIVE_LOW>;
  48. default-state = "keep";
  49. };
  50. };
  51. lvds_backlight: lvds-backlight {
  52. compatible = "pwm-backlight";
  53. pinctrl-names = "default";
  54. pinctrl-0 = <&pinctrl_lvds_bl>;
  55. enable-gpios = <&gpio6 9 GPIO_ACTIVE_HIGH>;
  56. pwms = <&pwm1 0 50000>;
  57. brightness-levels = <
  58. 0 4 8 16 32 64 80 96 112
  59. 128 144 160 176 250
  60. >;
  61. default-brightness-level = <13>;
  62. status = "okay";
  63. };
  64. pwm_fan: pwm-fan {
  65. compatible = "pwm-fan";
  66. #cooling-cells = <2>;
  67. pwms = <&pwm4 0 50000>;
  68. cooling-levels = <0 64 127 191 255>;
  69. status = "disabled";
  70. };
  71. rgb_encoder: display {
  72. compatible = "fsl,imx-parallel-display";
  73. #address-cells = <1>;
  74. #size-cells = <0>;
  75. pinctrl-names = "default";
  76. pinctrl-0 = <&pinctrl_rgb24_display>;
  77. status = "disabled";
  78. port@0 {
  79. reg = <0>;
  80. rgb_encoder_in: endpoint {
  81. remote-endpoint = <&ipu1_di0_disp0>;
  82. };
  83. };
  84. port@1 {
  85. reg = <1>;
  86. rgb_encoder_out: endpoint {
  87. remote-endpoint = <&rgb_panel_in>;
  88. };
  89. };
  90. };
  91. rgb_panel: lcd {
  92. backlight = <&rgb_backlight>;
  93. power-supply = <&reg_parallel_disp>;
  94. port {
  95. rgb_panel_in: endpoint {
  96. remote-endpoint = <&rgb_encoder_out>;
  97. };
  98. };
  99. };
  100. reg_parallel_disp: reg-parallel-display {
  101. compatible = "regulator-fixed";
  102. pinctrl-names = "default";
  103. pinctrl-0 = <&pinctrl_rgb_bl_en>;
  104. regulator-name = "LCD-Supply";
  105. regulator-min-microvolt = <5000000>;
  106. regulator-max-microvolt = <5000000>;
  107. gpio = <&gpio7 9 GPIO_ACTIVE_HIGH>;
  108. enable-active-high;
  109. };
  110. reg_lvds_disp: reg-lvds-display {
  111. compatible = "regulator-fixed";
  112. regulator-name = "LVDS-Supply";
  113. regulator-min-microvolt = <5000000>;
  114. regulator-max-microvolt = <5000000>;
  115. gpio = <&gpio7 10 GPIO_ACTIVE_HIGH>;
  116. enable-active-high;
  117. };
  118. rgb_backlight: rgb-backlight {
  119. compatible = "pwm-backlight";
  120. pinctrl-names = "default";
  121. pinctrl-0 = <&pinctrl_rgb_bl>;
  122. enable-gpios = <&gpio6 8 GPIO_ACTIVE_HIGH>;
  123. pwms = <&pwm3 0 5000000>;
  124. brightness-levels = <
  125. 250 176 160 144 128 112
  126. 96 80 64 48 32 16 8 1
  127. >;
  128. default-brightness-level = <13>;
  129. status = "okay";
  130. };
  131. };
  132. &can1 {
  133. pinctrl-names = "default";
  134. pinctrl-0 = <&pinctrl_can1>;
  135. };
  136. &can2 {
  137. pinctrl-names = "default";
  138. pinctrl-0 = <&pinctrl_can2>;
  139. };
  140. &ecspi2 {
  141. pinctrl-names = "default";
  142. pinctrl-0 = <&pinctrl_ecspi2>;
  143. cs-gpios = <&gpio2 26 GPIO_ACTIVE_LOW>,
  144. <&gpio2 27 GPIO_ACTIVE_LOW>;
  145. };
  146. &ecspi4 {
  147. pinctrl-names = "default";
  148. pinctrl-0 = <&pinctrl_nor_flash>;
  149. };
  150. &fec {
  151. pinctrl-names = "default";
  152. pinctrl-0 = <&pinctrl_enet>;
  153. phy-mode = "rgmii";
  154. phy-reset-gpios = <&gpio5 20 GPIO_ACTIVE_LOW>;
  155. phy-reset-duration = <50>;
  156. phy-supply = <&vdd_1V8_reg>;
  157. phy-handle = <&ksz9031>;
  158. status = "okay";
  159. mdio {
  160. #address-cells = <1>;
  161. #size-cells = <0>;
  162. ksz9031: phy@0 {
  163. compatible = "ethernet-phy-ieee802.3-c22";
  164. reg = <0>;
  165. interrupt-parent = <&gpio1>;
  166. interrupts = <30 IRQ_TYPE_EDGE_FALLING>;
  167. rxdv-skew-ps = <480>;
  168. txen-skew-ps = <480>;
  169. rxd0-skew-ps = <480>;
  170. rxd1-skew-ps = <480>;
  171. rxd2-skew-ps = <480>;
  172. rxd3-skew-ps = <480>;
  173. txd0-skew-ps = <420>;
  174. txd1-skew-ps = <420>;
  175. txd2-skew-ps = <360>;
  176. txd3-skew-ps = <360>;
  177. txc-skew-ps = <1020>;
  178. rxc-skew-ps = <960>;
  179. };
  180. };
  181. };
  182. &i2c1 {
  183. clock-frequency = <100000>;
  184. pinctrl-names = "default";
  185. pinctrl-0 = <&pinctrl_i2c1>;
  186. status = "okay";
  187. da9063: pmic@58 {
  188. compatible = "dlg,da9063";
  189. reg = <0x58>;
  190. pinctrl-names = "default";
  191. pinctrl-0 = <&pinctrl_pmic>;
  192. interrupt-parent = <&gpio2>;
  193. interrupts = <8 IRQ_TYPE_LEVEL_LOW>;
  194. interrupt-controller;
  195. onkey {
  196. compatible = "dlg,da9063-onkey";
  197. wakeup-source;
  198. };
  199. watchdog {
  200. compatible = "dlg,da9063-watchdog";
  201. timeout-sec = <0>;
  202. };
  203. regulators {
  204. vddcore_reg: bcore1 {
  205. regulator-min-microvolt = <1100000>;
  206. regulator-max-microvolt = <1450000>;
  207. regulator-ramp-delay = <2>;
  208. regulator-name = "DA9063_CORE";
  209. regulator-always-on;
  210. };
  211. vddsoc_reg: bcore2 {
  212. regulator-min-microvolt = <1100000>;
  213. regulator-max-microvolt = <1450000>;
  214. regulator-ramp-delay = <2>;
  215. regulator-name = "DA9063_SOC";
  216. regulator-always-on;
  217. };
  218. vdd_ddr3_reg: bpro {
  219. regulator-min-microvolt = <1500000>;
  220. regulator-max-microvolt = <1500000>;
  221. regulator-ramp-delay = <2>;
  222. regulator-always-on;
  223. };
  224. vdd_3v3_reg: bperi {
  225. regulator-min-microvolt = <3300000>;
  226. regulator-max-microvolt = <3300000>;
  227. regulator-ramp-delay = <2>;
  228. regulator-always-on;
  229. };
  230. vdd_sata_reg: ldo3 {
  231. regulator-min-microvolt = <2500000>;
  232. regulator-max-microvolt = <2500000>;
  233. regulator-always-on;
  234. };
  235. vdd_mipi_reg: ldo4 {
  236. regulator-min-microvolt = <2500000>;
  237. regulator-max-microvolt = <2500000>;
  238. regulator-always-on;
  239. };
  240. vdd_mx6_snvs_reg: ldo5 {
  241. regulator-min-microvolt = <3300000>;
  242. regulator-max-microvolt = <3300000>;
  243. regulator-always-on;
  244. };
  245. vdd_hdmi_reg: ldo6 {
  246. regulator-min-microvolt = <2500000>;
  247. regulator-max-microvolt = <2500000>;
  248. regulator-always-on;
  249. regulator-boot-on;
  250. };
  251. vdd_pcie_reg: ldo7 {
  252. regulator-min-microvolt = <2500000>;
  253. regulator-max-microvolt = <2500000>;
  254. regulator-always-on;
  255. };
  256. vdd_1V8_reg: ldo8 {
  257. regulator-min-microvolt = <1800000>;
  258. regulator-max-microvolt = <1800000>;
  259. regulator-always-on;
  260. };
  261. vdd_3V3_sdc_reg: ldo9 {
  262. regulator-min-microvolt = <1800000>;
  263. regulator-max-microvolt = <3300000>;
  264. regulator-always-on;
  265. };
  266. vdd_1V2_reg: ldo10 {
  267. regulator-min-microvolt = <1200000>;
  268. regulator-max-microvolt = <1200000>;
  269. regulator-always-on;
  270. };
  271. };
  272. };
  273. ds1307: rtc@68 {
  274. compatible = "dallas,ds1307";
  275. reg = <0x68>;
  276. };
  277. };
  278. &i2c2 {
  279. clock-frequency = <100000>;
  280. pinctrl-names = "default";
  281. pinctrl-0 = <&pinctrl_i2c2>;
  282. };
  283. &iomuxc {
  284. pinctrl_audmux: audmuxgrp {
  285. fsl,pins = <
  286. MX6QDL_PAD_CSI0_DAT7__AUD3_RXD 0x130b0
  287. MX6QDL_PAD_CSI0_DAT4__AUD3_TXC 0x1b060
  288. MX6QDL_PAD_CSI0_DAT5__AUD3_TXD 0x130B0
  289. MX6QDL_PAD_CSI0_DAT6__AUD3_TXFS 0x1b060
  290. >;
  291. };
  292. pinctrl_can1: can1grp {
  293. fsl,pins = <
  294. MX6QDL_PAD_KEY_COL2__FLEXCAN1_TX 0x1b0b1
  295. MX6QDL_PAD_KEY_ROW2__FLEXCAN1_RX 0x1b0b1
  296. >;
  297. };
  298. pinctrl_can2: can2grp {
  299. fsl,pins = <
  300. MX6QDL_PAD_KEY_COL4__FLEXCAN2_TX 0x1b0b1
  301. MX6QDL_PAD_KEY_ROW4__FLEXCAN2_RX 0x1b0b1
  302. >;
  303. };
  304. pinctrl_cpi1: csi0grp {
  305. fsl,pins = <
  306. MX6QDL_PAD_CSI0_PIXCLK__IPU1_CSI0_PIXCLK 0xb0b1
  307. MX6QDL_PAD_CSI0_MCLK__IPU1_CSI0_HSYNC 0x1b0b1
  308. MX6QDL_PAD_CSI0_VSYNC__IPU1_CSI0_VSYNC 0x1b0b1
  309. MX6QDL_PAD_CSI0_DAT12__IPU1_CSI0_DATA12 0x1b0b1
  310. MX6QDL_PAD_CSI0_DAT13__IPU1_CSI0_DATA13 0x1b0b1
  311. MX6QDL_PAD_CSI0_DAT14__IPU1_CSI0_DATA14 0x1b0b1
  312. MX6QDL_PAD_CSI0_DAT15__IPU1_CSI0_DATA15 0x1b0b1
  313. MX6QDL_PAD_CSI0_DAT16__IPU1_CSI0_DATA16 0x1b0b1
  314. MX6QDL_PAD_CSI0_DAT17__IPU1_CSI0_DATA17 0x1b0b1
  315. MX6QDL_PAD_CSI0_DAT18__IPU1_CSI0_DATA18 0x1b0b1
  316. MX6QDL_PAD_CSI0_DAT19__IPU1_CSI0_DATA19 0x1b0b1
  317. >;
  318. };
  319. /*camera2-pinctrl is in imx6q-emcon.dtsi or imx6dl-emcon.dtsi*/
  320. pinctrl_ecspi2: ecspi2grp {
  321. fsl,pins = <
  322. MX6QDL_PAD_EIM_CS0__ECSPI2_SCLK 0x100b1
  323. MX6QDL_PAD_EIM_CS1__ECSPI2_MOSI 0x100b1
  324. MX6QDL_PAD_EIM_OE__ECSPI2_MISO 0x100b1
  325. MX6QDL_PAD_EIM_LBA__GPIO2_IO27 0x100b1
  326. MX6QDL_PAD_EIM_RW__GPIO2_IO26 0x100b1
  327. >;
  328. };
  329. pinctrl_emcon_gpio1: emcongpio1 {
  330. fsl,pins = <
  331. MX6QDL_PAD_NANDF_D0__GPIO2_IO00 0x0b0b1
  332. >;
  333. };
  334. pinctrl_emcon_gpio2: emcongpio2 {
  335. fsl,pins = <
  336. MX6QDL_PAD_NANDF_D1__GPIO2_IO01 0x0b0b1
  337. >;
  338. };
  339. pinctrl_emcon_gpio3: emcongpio3 {
  340. fsl,pins = <
  341. MX6QDL_PAD_NANDF_D2__GPIO2_IO02 0x0b0b1
  342. >;
  343. };
  344. pinctrl_emcon_gpio4: emcongpio4 {
  345. fsl,pins = <
  346. MX6QDL_PAD_NANDF_D3__GPIO2_IO03 0x0b0b1
  347. >;
  348. };
  349. pinctrl_emcon_gpio5: emcongpio5 {
  350. fsl,pins = <
  351. MX6QDL_PAD_NANDF_D4__GPIO2_IO04 0x0b0b1
  352. >;
  353. };
  354. pinctrl_emcon_gpio6: emcongpio6 {
  355. fsl,pins = <
  356. MX6QDL_PAD_NANDF_D5__GPIO2_IO05 0x0b0b1
  357. >;
  358. };
  359. pinctrl_emcon_gpio7: emcongpio7 {
  360. fsl,pins = <
  361. MX6QDL_PAD_NANDF_D6__GPIO2_IO06 0x0b0b1
  362. >;
  363. };
  364. pinctrl_emcon_gpio8: emcongpio8 {
  365. fsl,pins = <
  366. MX6QDL_PAD_NANDF_D7__GPIO2_IO07 0x0b0b1
  367. >;
  368. };
  369. pinctrl_emcon_irq_a: emconirqa {
  370. fsl,pins = <
  371. MX6QDL_PAD_NANDF_CLE__GPIO6_IO07 0x0b0b1
  372. >;
  373. };
  374. pinctrl_emcon_irq_b: emconirqb {
  375. fsl,pins = <
  376. MX6QDL_PAD_NANDF_CS2__GPIO6_IO15 0x0b0b1
  377. >;
  378. };
  379. pinctrl_emcon_irq_c: emconirqc {
  380. fsl,pins = <
  381. MX6QDL_PAD_NANDF_CS3__GPIO6_IO16 0x0b0b1
  382. >;
  383. };
  384. pinctrl_emcon_irq_pwr: emconirqpwr {
  385. fsl,pins = <
  386. MX6QDL_PAD_EIM_D23__GPIO3_IO23 0x0b0b1
  387. >;
  388. };
  389. pinctrl_emcon_wake: emconwake {
  390. fsl,pins = <
  391. MX6QDL_PAD_EIM_DA2__GPIO3_IO02 0x1b0b1
  392. >;
  393. };
  394. pinctrl_enet: enetgrp {
  395. fsl,pins = <
  396. MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b030
  397. MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b030
  398. MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b030
  399. MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b030
  400. MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b030
  401. MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b030
  402. MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b030
  403. MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b030
  404. MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x4001a0b1
  405. MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b030
  406. MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b030
  407. MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b030
  408. MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b030
  409. MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b030
  410. MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b0b0
  411. MX6QDL_PAD_CSI0_DATA_EN__GPIO5_IO20 0x1b058
  412. MX6QDL_PAD_ENET_TXD0__GPIO1_IO30 0x1b0b0
  413. >;
  414. };
  415. pinctrl_i2c1: i2c1grp {
  416. fsl,pins = <
  417. MX6QDL_PAD_CSI0_DAT8__I2C1_SDA 0x4001b8b1
  418. MX6QDL_PAD_CSI0_DAT9__I2C1_SCL 0x4001b8b1
  419. >;
  420. };
  421. pinctrl_i2c2: i2c2grp {
  422. fsl,pins = <
  423. MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1
  424. MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1
  425. >;
  426. };
  427. pinctrl_i2c3: i2c3grp {
  428. fsl,pins = <
  429. MX6QDL_PAD_GPIO_3__I2C3_SCL 0x4000b070
  430. MX6QDL_PAD_GPIO_6__I2C3_SDA 0x4001b870
  431. >;
  432. };
  433. pinctrl_irq_touch1: irqtouch1 {
  434. fsl,pins = <
  435. MX6QDL_PAD_GPIO_5__GPIO1_IO05 0x0b0b1
  436. >;
  437. };
  438. pinctrl_irq_touch2: irqtouch2 {
  439. fsl,pins = <
  440. MX6QDL_PAD_EIM_BCLK__GPIO6_IO31 0x0b0b1
  441. >;
  442. };
  443. pinctrl_lvds_bl: lvdsbacklightgrp {
  444. fsl,pins = <
  445. MX6QDL_PAD_GPIO_9__PWM1_OUT 0x0b0b1
  446. MX6QDL_PAD_NANDF_WP_B__GPIO6_IO09 0x0b0b1
  447. >;
  448. };
  449. pinctrl_lvds_reg: lvdsreggrp {
  450. fsl,pins = <
  451. MX6QDL_PAD_SD4_CLK__GPIO7_IO10 0x0b0b1
  452. >;
  453. };
  454. pinctrl_nor_flash: norflashgrp {
  455. fsl,pins = <
  456. MX6QDL_PAD_NANDF_CS0__GPIO6_IO11 0x1b0b1
  457. MX6QDL_PAD_EIM_D21__ECSPI4_SCLK 0x100b1
  458. MX6QDL_PAD_EIM_D28__ECSPI4_MOSI 0x100b1
  459. MX6QDL_PAD_EIM_D22__ECSPI4_MISO 0x100b1
  460. MX6QDL_PAD_EIM_A25__GPIO5_IO02 0x100b1
  461. >;
  462. };
  463. pinctrl_pcie_ctrl: pciegrp {
  464. fsl,pins = <
  465. MX6QDL_PAD_EIM_A16__GPIO2_IO22 0x1b0b1
  466. MX6QDL_PAD_GPIO_17__GPIO7_IO12 0x1b0b1
  467. >;
  468. };
  469. pinctrl_pmic: pmicgrp {
  470. fsl,pins = <
  471. MX6QDL_PAD_SD4_DAT0__GPIO2_IO08 0x0b0b1
  472. >;
  473. };
  474. pinctrl_pwm_fan: pwmfan {
  475. fsl,pins = <
  476. MX6QDL_PAD_SD4_DAT2__PWM4_OUT 0x0b0b1
  477. >;
  478. };
  479. pinctrl_rgb_bl: rgbbacklightgrp {
  480. fsl,pins = <
  481. MX6QDL_PAD_SD4_DAT1__PWM3_OUT 0x0b0b1
  482. MX6QDL_PAD_NANDF_ALE__GPIO6_IO08 0x0b0b1
  483. >;
  484. };
  485. pinctrl_rgb_bl_en: rgbenable {
  486. fsl,pins = <
  487. MX6QDL_PAD_SD4_CMD__GPIO7_IO09 0x0b0b1
  488. >;
  489. };
  490. pinctrl_rgb24_display: rgbgrp {
  491. fsl,pins = <
  492. MX6QDL_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK 0x10
  493. MX6QDL_PAD_DI0_PIN15__IPU1_DI0_PIN15 0x10
  494. MX6QDL_PAD_DI0_PIN2__IPU1_DI0_PIN02 0x10
  495. MX6QDL_PAD_DI0_PIN3__IPU1_DI0_PIN03 0x10
  496. MX6QDL_PAD_DISP0_DAT0__IPU1_DISP0_DATA00 0x10
  497. MX6QDL_PAD_DISP0_DAT1__IPU1_DISP0_DATA01 0x10
  498. MX6QDL_PAD_DISP0_DAT2__IPU1_DISP0_DATA02 0x10
  499. MX6QDL_PAD_DISP0_DAT3__IPU1_DISP0_DATA03 0x10
  500. MX6QDL_PAD_DISP0_DAT4__IPU1_DISP0_DATA04 0x10
  501. MX6QDL_PAD_DISP0_DAT5__IPU1_DISP0_DATA05 0x10
  502. MX6QDL_PAD_DISP0_DAT6__IPU1_DISP0_DATA06 0x10
  503. MX6QDL_PAD_DISP0_DAT7__IPU1_DISP0_DATA07 0x10
  504. MX6QDL_PAD_DISP0_DAT8__IPU1_DISP0_DATA08 0x10
  505. MX6QDL_PAD_DISP0_DAT9__IPU1_DISP0_DATA09 0x10
  506. MX6QDL_PAD_DISP0_DAT10__IPU1_DISP0_DATA10 0x10
  507. MX6QDL_PAD_DISP0_DAT11__IPU1_DISP0_DATA11 0x10
  508. MX6QDL_PAD_DISP0_DAT12__IPU1_DISP0_DATA12 0x10
  509. MX6QDL_PAD_DISP0_DAT13__IPU1_DISP0_DATA13 0x10
  510. MX6QDL_PAD_DISP0_DAT14__IPU1_DISP0_DATA14 0x10
  511. MX6QDL_PAD_DISP0_DAT15__IPU1_DISP0_DATA15 0x10
  512. MX6QDL_PAD_DISP0_DAT16__IPU1_DISP0_DATA16 0x10
  513. MX6QDL_PAD_DISP0_DAT17__IPU1_DISP0_DATA17 0x10
  514. MX6QDL_PAD_DISP0_DAT18__IPU1_DISP0_DATA18 0x10
  515. MX6QDL_PAD_DISP0_DAT19__IPU1_DISP0_DATA19 0x10
  516. MX6QDL_PAD_DISP0_DAT20__IPU1_DISP0_DATA20 0x10
  517. MX6QDL_PAD_DISP0_DAT21__IPU1_DISP0_DATA21 0x10
  518. MX6QDL_PAD_DISP0_DAT22__IPU1_DISP0_DATA22 0x10
  519. MX6QDL_PAD_DISP0_DAT23__IPU1_DISP0_DATA23 0x10
  520. >;
  521. };
  522. pinctrl_secure: securegrp {
  523. fsl,pins = <
  524. MX6QDL_PAD_GPIO_18__GPIO7_IO13 0x1b0b1
  525. >;
  526. };
  527. pinctrl_som_leds: somledgrp {
  528. fsl,pins = <
  529. MX6QDL_PAD_EIM_DA0__GPIO3_IO00 0x0b0b1
  530. MX6QDL_PAD_EIM_DA1__GPIO3_IO01 0x0b0b1
  531. >;
  532. };
  533. pinctrl_spdif_in: spdifin {
  534. fsl,pins = <
  535. MX6QDL_PAD_GPIO_16__SPDIF_IN 0x1b0b0
  536. >;
  537. };
  538. pinctrl_spdif_out: spdifout {
  539. fsl,pins = <
  540. MX6QDL_PAD_GPIO_19__SPDIF_OUT 0x13091
  541. >;
  542. };
  543. pinctrl_uart1: uart1grp {
  544. fsl,pins = <
  545. MX6QDL_PAD_CSI0_DAT10__UART1_TX_DATA 0x1b0b1
  546. MX6QDL_PAD_CSI0_DAT11__UART1_RX_DATA 0x1b0b1
  547. >;
  548. };
  549. pinctrl_uart2: uart2grp {
  550. fsl,pins = <
  551. MX6QDL_PAD_SD4_DAT5__UART2_RTS_B 0x1b0b1
  552. MX6QDL_PAD_SD4_DAT6__UART2_CTS_B 0x1b0b1
  553. MX6QDL_PAD_SD4_DAT7__UART2_TX_DATA 0x1b0b1
  554. MX6QDL_PAD_SD4_DAT4__UART2_RX_DATA 0x1b0b1
  555. >;
  556. };
  557. pinctrl_uart3: uart3grp {
  558. fsl,pins = <
  559. MX6QDL_PAD_EIM_D24__UART3_TX_DATA 0x1b0b1
  560. MX6QDL_PAD_EIM_D25__UART3_RX_DATA 0x1b0b1
  561. >;
  562. };
  563. pinctrl_uart4: uart4grp {
  564. fsl,pins = <
  565. MX6QDL_PAD_KEY_COL0__UART4_TX_DATA 0x1b0b1
  566. MX6QDL_PAD_KEY_ROW0__UART4_RX_DATA 0x1b0b1
  567. >;
  568. };
  569. pinctrl_uart5: uart5grp {
  570. fsl,pins = <
  571. MX6QDL_PAD_KEY_COL1__UART5_TX_DATA 0x1b0b1
  572. MX6QDL_PAD_KEY_ROW1__UART5_RX_DATA 0x1b0b1
  573. >;
  574. };
  575. pinctrl_usb_host1: usbhgrp {
  576. fsl,pins = <
  577. MX6QDL_PAD_EIM_D31__USB_H1_PWR 0x1B058
  578. MX6QDL_PAD_EIM_D30__USB_H1_OC 0x1B058
  579. >;
  580. };
  581. pinctrl_usb_otg: usbotggrp {
  582. fsl,pins = <
  583. MX6QDL_PAD_ENET_RX_ER__USB_OTG_ID 0x17059
  584. MX6QDL_PAD_GPIO_7__GPIO1_IO07 0x17059
  585. MX6QDL_PAD_GPIO_8__GPIO1_IO08 0x17059
  586. >;
  587. };
  588. pinctrl_usdhc1: usdhc1grp {
  589. fsl,pins = <
  590. MX6QDL_PAD_SD1_CMD__SD1_CMD 0x17059
  591. MX6QDL_PAD_SD1_CLK__SD1_CLK 0x10059
  592. MX6QDL_PAD_SD1_DAT0__SD1_DATA0 0x17059
  593. MX6QDL_PAD_SD1_DAT1__SD1_DATA1 0x17059
  594. MX6QDL_PAD_SD1_DAT2__SD1_DATA2 0x17059
  595. MX6QDL_PAD_SD1_DAT3__SD1_DATA3 0x17059
  596. MX6QDL_PAD_GPIO_1__SD1_CD_B 0x1b0b1
  597. MX6QDL_PAD_DI0_PIN4__SD1_WP 0x1b0b1
  598. >;
  599. };
  600. pinctrl_usdhc2: usdhc2grp {
  601. fsl,pins = <
  602. MX6QDL_PAD_SD2_CMD__SD2_CMD 0x17059
  603. MX6QDL_PAD_SD2_CLK__SD2_CLK 0x10059
  604. MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x17059
  605. MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x17059
  606. MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x17059
  607. MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x17059
  608. MX6QDL_PAD_GPIO_4__SD2_CD_B 0x1b0b1
  609. MX6QDL_PAD_GPIO_2__SD2_WP 0x1b0b1
  610. >;
  611. };
  612. pinctrl_usdhc3: usdhc3grp {
  613. fsl,pins = <
  614. MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059
  615. MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10059
  616. MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059
  617. MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059
  618. MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059
  619. MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059
  620. MX6QDL_PAD_SD3_DAT4__SD3_DATA4 0x17059
  621. MX6QDL_PAD_SD3_DAT5__SD3_DATA5 0x17059
  622. MX6QDL_PAD_SD3_DAT6__SD3_DATA6 0x17059
  623. MX6QDL_PAD_SD3_DAT7__SD3_DATA7 0x17059
  624. MX6QDL_PAD_SD3_RST__SD3_RESET 0x1b0b1
  625. >;
  626. };
  627. };
  628. &ipu1_di0_disp0 {
  629. remote-endpoint = <&rgb_encoder_in>;
  630. };
  631. &pcie {
  632. pinctrl-names = "default";
  633. pinctrl-0 = <&pinctrl_pcie_ctrl>;
  634. reset-gpio = <&gpio7 12 GPIO_ACTIVE_LOW>;
  635. disable-gpio = <&gpio2 22 GPIO_ACTIVE_LOW>;
  636. };
  637. &pwm1 {
  638. #pwm-cells = <2>;
  639. status = "okay";
  640. };
  641. &pwm3 {
  642. #pwm-cells = <2>;
  643. status = "okay";
  644. };
  645. &pwm4 {
  646. #pwm-cells = <2>;
  647. status = "okay";
  648. };
  649. &uart1 {
  650. pinctrl-names = "default";
  651. pinctrl-0 = <&pinctrl_uart1>;
  652. status = "okay";
  653. };
  654. &uart2 {
  655. pinctrl-names = "default";
  656. pinctrl-0 = <&pinctrl_uart2>;
  657. };
  658. &uart3 {
  659. pinctrl-names = "default";
  660. pinctrl-0 = <&pinctrl_uart3>;
  661. };
  662. &uart4 {
  663. pinctrl-names = "default";
  664. pinctrl-0 = <&pinctrl_uart4>;
  665. };
  666. &uart5 {
  667. pinctrl-names = "default";
  668. pinctrl-0 = <&pinctrl_uart5>;
  669. };
  670. &usbh1 {
  671. pinctrl-names = "default";
  672. pinctrl-0 = <&pinctrl_usb_host1>;
  673. };
  674. &usbotg {
  675. pinctrl-names = "default";
  676. pinctrl-0 = <&pinctrl_usb_otg>;
  677. vbus-supply = <&reg_usb_otg>;
  678. dr_mode = "peripheral";
  679. };
  680. &usdhc1 {
  681. pinctrl-names = "default";
  682. pinctrl-0 = <&pinctrl_usdhc1>;
  683. fsl,wp-controller;
  684. };
  685. &usdhc2 {
  686. pinctrl-names = "default";
  687. pinctrl-0 = <&pinctrl_usdhc2>;
  688. fsl,wp-controller;
  689. };
  690. &usdhc3 {
  691. pinctrl-names = "default";
  692. pinctrl-0 = <&pinctrl_usdhc3>;
  693. non-removable;
  694. bus-width = <8>;
  695. status = "okay";
  696. };
  697. /******device power Management*********/
  698. &cpu0 {
  699. voltage-tolerance = <2>;
  700. };
  701. &reg_arm {
  702. vin-supply = <&vddcore_reg>;
  703. };
  704. &reg_soc {
  705. vin-supply = <&vddsoc_reg>;
  706. };
  707. &reg_pu {
  708. vin-supply = <&vddsoc_reg>;
  709. };
  710. /*******Disabled HW following***********/
  711. &snvs_rtc {
  712. status = "disabled";
  713. };