imx6q-prtwd2.dts 3.7 KB

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  1. // SPDX-License-Identifier: GPL-2.0-or-later
  2. /*
  3. * Copyright (c) 2018 Protonic Holland
  4. */
  5. /dts-v1/;
  6. #include "imx6q.dtsi"
  7. #include "imx6qdl-prti6q.dtsi"
  8. #include <dt-bindings/leds/common.h>
  9. / {
  10. model = "Protonic WD2 board";
  11. compatible = "prt,prtwd2", "fsl,imx6q";
  12. memory@10000000 {
  13. device_type = "memory";
  14. reg = <0x10000000 0x20000000>;
  15. };
  16. memory@80000000 {
  17. device_type = "memory";
  18. reg = <0x80000000 0x20000000>;
  19. };
  20. usdhc2_wifi_pwrseq: usdhc2_wifi_pwrseq {
  21. compatible = "mmc-pwrseq-simple";
  22. pinctrl-names = "default";
  23. pinctrl-0 = <&pinctrl_wifi_npd>;
  24. reset-gpios = <&gpio6 10 GPIO_ACTIVE_LOW>;
  25. };
  26. /* PRTWD2 rev 1 bitbang I2C for Ethernet Switch */
  27. i2c {
  28. compatible = "i2c-gpio";
  29. pinctrl-names = "default";
  30. pinctrl-0 = <&pinctrl_i2c4>;
  31. sda-gpios = <&gpio1 22 (GPIO_ACTIVE_HIGH|GPIO_OPEN_DRAIN)>;
  32. scl-gpios = <&gpio1 31 GPIO_ACTIVE_HIGH>;
  33. i2c-gpio,delay-us = <20>; /* ~10 kHz */
  34. i2c-gpio,scl-output-only;
  35. #address-cells = <1>;
  36. #size-cells = <0>;
  37. };
  38. };
  39. &can1 {
  40. pinctrl-names = "default";
  41. pinctrl-0 = <&pinctrl_can1 &pinctrl_can1phy>;
  42. status = "okay";
  43. };
  44. &fec {
  45. pinctrl-names = "default";
  46. pinctrl-0 = <&pinctrl_enet>;
  47. phy-mode = "rmii";
  48. clocks = <&clks IMX6QDL_CLK_ENET>,
  49. <&clks IMX6QDL_CLK_ENET>;
  50. clock-names = "ipg", "ahb";
  51. status = "okay";
  52. fixed-link {
  53. speed = <100>;
  54. pause;
  55. full-duplex;
  56. };
  57. };
  58. &i2c3 {
  59. adc@49 {
  60. compatible = "ti,ads1015";
  61. reg = <0x49>;
  62. #address-cells = <1>;
  63. #size-cells = <0>;
  64. /* V in */
  65. channel@4 {
  66. reg = <4>;
  67. ti,gain = <1>;
  68. ti,datarate = <3>;
  69. };
  70. /* I charge */
  71. channel@5 {
  72. reg = <5>;
  73. ti,gain = <1>;
  74. ti,datarate = <3>;
  75. };
  76. /* V bus */
  77. channel@6 {
  78. reg = <6>;
  79. ti,gain = <1>;
  80. ti,datarate = <3>;
  81. };
  82. /* nc */
  83. channel@7 {
  84. reg = <7>;
  85. ti,gain = <1>;
  86. ti,datarate = <3>;
  87. };
  88. };
  89. };
  90. &usdhc2 {
  91. pinctrl-names = "default";
  92. pinctrl-0 = <&pinctrl_usdhc2>;
  93. no-1-8-v;
  94. non-removable;
  95. mmc-pwrseq = <&usdhc2_wifi_pwrseq>;
  96. #address-cells = <1>;
  97. #size-cells = <0>;
  98. status = "okay";
  99. wifi@1 {
  100. compatible = "brcm,bcm4329-fmac";
  101. reg = <1>;
  102. };
  103. };
  104. &iomuxc {
  105. pinctrl-names = "default";
  106. pinctrl-0 = <&pinctrl_usb_eth_chg>;
  107. pinctrl_can1phy: can1phy {
  108. fsl,pins = <
  109. /* CAN1_SR */
  110. MX6QDL_PAD_KEY_COL3__GPIO4_IO12 0x13070
  111. >;
  112. };
  113. pinctrl_enet: enetgrp {
  114. fsl,pins = <
  115. /* MX6QDL_ENET_PINGRP4 */
  116. MX6QDL_PAD_ENET_RXD0__ENET_RX_DATA0 0x1b0b0
  117. MX6QDL_PAD_ENET_RXD1__ENET_RX_DATA1 0x1b0b0
  118. MX6QDL_PAD_ENET_RX_ER__ENET_RX_ER 0x130b0
  119. MX6QDL_PAD_ENET_TX_EN__ENET_TX_EN 0x1b0b0
  120. MX6QDL_PAD_ENET_TXD0__ENET_TX_DATA0 0x1b0b0
  121. MX6QDL_PAD_ENET_TXD1__ENET_TX_DATA1 0x1b0b0
  122. MX6QDL_PAD_ENET_CRS_DV__ENET_RX_EN 0x1b0b0
  123. MX6QDL_PAD_GPIO_16__ENET_REF_CLK 0x1b0b0
  124. /* Phy reset */
  125. MX6QDL_PAD_CSI0_DAT4__GPIO5_IO22 0x1b0b0
  126. /* nINTRP */
  127. MX6QDL_PAD_CSI0_DAT5__GPIO5_IO23 0x1b0b0
  128. MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x10030
  129. MX6QDL_PAD_ENET_MDC__ENET_MDC 0x10030
  130. >;
  131. };
  132. pinctrl_i2c4: i2c4grp {
  133. fsl,pins = <
  134. MX6QDL_PAD_ENET_MDIO__GPIO1_IO22 0x1f8b0
  135. MX6QDL_PAD_ENET_MDC__GPIO1_IO31 0x1f8b0
  136. >;
  137. };
  138. pinctrl_usb_eth_chg: usbethchggrp {
  139. fsl,pins = <
  140. /* USB charging control */
  141. MX6QDL_PAD_NANDF_CS0__GPIO6_IO11 0x130b0
  142. MX6QDL_PAD_NANDF_CS1__GPIO6_IO14 0x130b0
  143. MX6QDL_PAD_NANDF_CS2__GPIO6_IO15 0x130b0
  144. MX6QDL_PAD_NANDF_CS3__GPIO6_IO16 0x130b0
  145. >;
  146. };
  147. pinctrl_usdhc2: usdhc2grp {
  148. fsl,pins = <
  149. MX6QDL_PAD_SD2_CMD__SD2_CMD 0x170b9
  150. MX6QDL_PAD_SD2_CLK__SD2_CLK 0x100b9
  151. MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x170b9
  152. MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x170b9
  153. MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x170b9
  154. MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x170b9
  155. >;
  156. };
  157. pinctrl_wifi_npd: wifinpd {
  158. fsl,pins = <
  159. /* WL_REG_ON */
  160. MX6QDL_PAD_NANDF_RB0__GPIO6_IO10 0x13069
  161. >;
  162. };
  163. };