imx6q-prti6q.dts 11 KB

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  1. // SPDX-License-Identifier: GPL-2.0-or-later OR MIT
  2. /*
  3. * Copyright (c) 2014 Protonic Holland
  4. */
  5. /dts-v1/;
  6. #include "imx6q.dtsi"
  7. #include "imx6qdl-prti6q.dtsi"
  8. #include <dt-bindings/leds/common.h>
  9. #include <dt-bindings/sound/fsl-imx-audmux.h>
  10. / {
  11. model = "Protonic PRTI6Q board";
  12. compatible = "prt,prti6q", "fsl,imx6q";
  13. memory@10000000 {
  14. device_type = "memory";
  15. reg = <0x10000000 0xf0000000>;
  16. };
  17. backlight_lcd: backlight-lcd {
  18. compatible = "pwm-backlight";
  19. pinctrl-names = "default";
  20. pinctrl-0 = <&pinctrl_backlight>;
  21. pwms = <&pwm1 0 5000000>;
  22. brightness-levels = <0 16 64 255>;
  23. num-interpolated-steps = <16>;
  24. default-brightness-level = <1>;
  25. power-supply = <&reg_3v3>;
  26. enable-gpios = <&gpio4 28 GPIO_ACTIVE_HIGH>;
  27. };
  28. can_osc: can-osc {
  29. compatible = "fixed-clock";
  30. #clock-cells = <0>;
  31. clock-frequency = <25000000>;
  32. };
  33. leds {
  34. compatible = "gpio-leds";
  35. pinctrl-names = "default";
  36. pinctrl-0 = <&pinctrl_leds>;
  37. led-debug0 {
  38. function = LED_FUNCTION_STATUS;
  39. gpios = <&gpio1 8 GPIO_ACTIVE_HIGH>;
  40. linux,default-trigger = "heartbeat";
  41. };
  42. led-debug1 {
  43. function = LED_FUNCTION_SD;
  44. gpios = <&gpio1 9 GPIO_ACTIVE_HIGH>;
  45. linux,default-trigger = "disk-activity";
  46. };
  47. };
  48. panel {
  49. compatible = "kyo,tcg121xglp";
  50. backlight = <&backlight_lcd>;
  51. port {
  52. panel_in: endpoint {
  53. remote-endpoint = <&lvds0_out>;
  54. };
  55. };
  56. };
  57. reg_1v8: regulator-1v8 {
  58. compatible = "regulator-fixed";
  59. regulator-name = "1v8";
  60. regulator-min-microvolt = <1800000>;
  61. regulator-max-microvolt = <1800000>;
  62. };
  63. reg_wifi: regulator-wifi {
  64. compatible = "regulator-fixed";
  65. pinctrl-names = "default";
  66. pinctrl-0 = <&pinctrl_wifi_npd>;
  67. enable-active-high;
  68. gpio = <&gpio1 26 GPIO_ACTIVE_HIGH>;
  69. regulator-max-microvolt = <1800000>;
  70. regulator-min-microvolt = <1800000>;
  71. regulator-name = "regulator-WL12xx";
  72. startup-delay-us = <70000>;
  73. };
  74. sound {
  75. compatible = "simple-audio-card";
  76. simple-audio-card,name = "prti6q-sgtl5000";
  77. simple-audio-card,format = "i2s";
  78. simple-audio-card,widgets =
  79. "Microphone", "Microphone Jack",
  80. "Line", "Line In Jack",
  81. "Headphone", "Headphone Jack",
  82. "Speaker", "External Speaker";
  83. simple-audio-card,routing =
  84. "MIC_IN", "Microphone Jack",
  85. "LINE_IN", "Line In Jack",
  86. "Headphone Jack", "HP_OUT",
  87. "External Speaker", "LINE_OUT";
  88. simple-audio-card,cpu {
  89. sound-dai = <&ssi1>;
  90. system-clock-frequency = <0>;
  91. };
  92. simple-audio-card,codec {
  93. sound-dai = <&sgtl5000>;
  94. bitclock-master;
  95. frame-master;
  96. };
  97. };
  98. sound-spdif {
  99. compatible = "fsl,imx-audio-spdif";
  100. model = "imx-spdif";
  101. spdif-controller = <&spdif>;
  102. spdif-in;
  103. spdif-out;
  104. };
  105. };
  106. &audmux {
  107. pinctrl-names = "default";
  108. pinctrl-0 = <&pinctrl_audmux>;
  109. status = "okay";
  110. mux-ssi1 {
  111. fsl,audmux-port = <0>;
  112. fsl,port-config = <
  113. IMX_AUDMUX_V2_PTCR_SYN 0
  114. IMX_AUDMUX_V2_PTCR_TFSEL(2) 0
  115. IMX_AUDMUX_V2_PTCR_TCSEL(2) 0
  116. IMX_AUDMUX_V2_PTCR_TFSDIR 0
  117. IMX_AUDMUX_V2_PTCR_TCLKDIR IMX_AUDMUX_V2_PDCR_RXDSEL(2)
  118. >;
  119. };
  120. mux-pins3 {
  121. fsl,audmux-port = <2>;
  122. fsl,port-config = <
  123. IMX_AUDMUX_V2_PTCR_SYN IMX_AUDMUX_V2_PDCR_RXDSEL(0)
  124. 0 IMX_AUDMUX_V2_PDCR_TXRXEN
  125. >;
  126. };
  127. };
  128. &can1 {
  129. pinctrl-names = "default";
  130. pinctrl-0 = <&pinctrl_can1>;
  131. status = "okay";
  132. };
  133. &can2 {
  134. pinctrl-names = "default";
  135. pinctrl-0 = <&pinctrl_can2>;
  136. status = "okay";
  137. };
  138. &ecspi1 {
  139. cs-gpios = <&gpio3 19 GPIO_ACTIVE_LOW>;
  140. pinctrl-names = "default";
  141. pinctrl-0 = <&pinctrl_ecspi1>;
  142. status = "okay";
  143. flash@0 {
  144. compatible = "jedec,spi-nor";
  145. reg = <0>;
  146. spi-max-frequency = <20000000>;
  147. };
  148. };
  149. &ecspi2 {
  150. cs-gpios = <&gpio2 26 GPIO_ACTIVE_LOW>, <&gpio4 25 GPIO_ACTIVE_LOW>;
  151. pinctrl-names = "default";
  152. pinctrl-0 = <&pinctrl_ecspi2 &pinctrl_ecspi2_cs>;
  153. status = "okay";
  154. can@0 {
  155. compatible = "microchip,mcp2515";
  156. reg = <0>;
  157. pinctrl-names = "default";
  158. pinctrl-0 = <&pinctrl_can3>;
  159. clocks = <&can_osc>;
  160. interrupts-extended = <&gpio3 20 IRQ_TYPE_LEVEL_LOW>;
  161. spi-max-frequency = <5000000>;
  162. };
  163. adc@1 {
  164. compatible = "ti,adc128s052";
  165. reg = <1>;
  166. spi-max-frequency = <2000000>;
  167. vref-supply = <&reg_3v3>;
  168. };
  169. };
  170. &ecspi3 {
  171. cs-gpios = <&gpio4 24 GPIO_ACTIVE_LOW>;
  172. pinctrl-names = "default";
  173. pinctrl-0 = <&pinctrl_ecspi3>;
  174. status = "okay";
  175. };
  176. &fec {
  177. pinctrl-names = "default";
  178. pinctrl-0 = <&pinctrl_enet>;
  179. phy-mode = "rgmii-id";
  180. phy-handle = <&rgmii_phy>;
  181. status = "okay";
  182. mdio {
  183. #address-cells = <1>;
  184. #size-cells = <0>;
  185. /* Microchip KSZ9031RNX PHY */
  186. rgmii_phy: ethernet-phy@0 {
  187. reg = <0>;
  188. interrupts-extended = <&gpio1 28 IRQ_TYPE_LEVEL_LOW>;
  189. reset-gpios = <&gpio1 25 GPIO_ACTIVE_LOW>;
  190. reset-assert-us = <10000>;
  191. reset-deassert-us = <300>;
  192. };
  193. };
  194. };
  195. &hdmi {
  196. pinctrl-names = "default";
  197. pinctrl-0 = <&pinctrl_hdmi>;
  198. ddc-i2c-bus = <&i2c2>;
  199. status = "okay";
  200. };
  201. &i2c1 {
  202. sgtl5000: audio-codec@a {
  203. compatible = "fsl,sgtl5000";
  204. reg = <0xa>;
  205. #sound-dai-cells = <0>;
  206. clocks = <&clks 201>;
  207. VDDA-supply = <&reg_3v3>;
  208. VDDIO-supply = <&reg_3v3>;
  209. VDDD-supply = <&reg_1v8>;
  210. };
  211. };
  212. /* DDC */
  213. &i2c2 {
  214. clock-frequency = <100000>;
  215. pinctrl-names = "default";
  216. pinctrl-0 = <&pinctrl_i2c2>;
  217. status = "okay";
  218. };
  219. &i2c3 {
  220. adc@49 {
  221. compatible = "ti,ads1015";
  222. reg = <0x49>;
  223. #address-cells = <1>;
  224. #size-cells = <0>;
  225. /* can2_l */
  226. channel@4 {
  227. reg = <4>;
  228. ti,gain = <3>;
  229. ti,datarate = <3>;
  230. };
  231. /* can2_h */
  232. channel@5 {
  233. reg = <5>;
  234. ti,gain = <3>;
  235. ti,datarate = <3>;
  236. };
  237. /* can1_l */
  238. channel@6 {
  239. reg = <6>;
  240. ti,gain = <3>;
  241. ti,datarate = <3>;
  242. };
  243. /* can1_h */
  244. channel@7 {
  245. reg = <7>;
  246. ti,gain = <3>;
  247. ti,datarate = <3>;
  248. };
  249. };
  250. };
  251. &pcie {
  252. status = "okay";
  253. };
  254. &pwm1 {
  255. #pwm-cells = <2>;
  256. pinctrl-names = "default";
  257. pinctrl-0 = <&pinctrl_pwm1>;
  258. status = "okay";
  259. };
  260. &ldb {
  261. status = "okay";
  262. lvds-channel@0 {
  263. status = "okay";
  264. port@4 {
  265. reg = <4>;
  266. lvds0_out: endpoint {
  267. remote-endpoint = <&panel_in>;
  268. };
  269. };
  270. };
  271. };
  272. &sata {
  273. status = "okay";
  274. };
  275. &snvs_poweroff {
  276. status = "okay";
  277. };
  278. &spdif {
  279. pinctrl-names = "default";
  280. pinctrl-0 = <&pinctrl_spdif>;
  281. status = "okay";
  282. };
  283. &ssi1 {
  284. #sound-dai-cells = <0>;
  285. fsl,mode = "ac97-slave";
  286. status = "okay";
  287. };
  288. &uart2 {
  289. pinctrl-names = "default";
  290. pinctrl-0 = <&pinctrl_uart2>;
  291. status = "okay";
  292. };
  293. &uart5 {
  294. pinctrl-names = "default";
  295. pinctrl-0 = <&pinctrl_uart5>;
  296. status = "okay";
  297. };
  298. &usbotg {
  299. pinctrl-0 = <&pinctrl_usbotg &pinctrl_usbotg_id>;
  300. };
  301. &usdhc2 {
  302. pinctrl-names = "default";
  303. pinctrl-0 = <&pinctrl_usdhc2>;
  304. non-removable;
  305. vmmc-supply = <&reg_wifi>;
  306. cap-power-off-card;
  307. keep-power-in-suspend;
  308. status = "okay";
  309. wifi {
  310. compatible = "ti,wl1271";
  311. pinctrl-names = "default";
  312. pinctrl-0 = <&pinctrl_wifi>;
  313. interrupts-extended = <&gpio1 30 IRQ_TYPE_LEVEL_HIGH>;
  314. ref-clock-frequency = <38400000>;
  315. tcxo-clock-frequency = <19200000>;
  316. };
  317. };
  318. &iomuxc {
  319. pinctrl_audmux: audmuxgrp {
  320. fsl,pins = <
  321. MX6QDL_PAD_CSI0_MCLK__CCM_CLKO1 0x030b0
  322. MX6QDL_PAD_CSI0_DAT7__AUD3_RXD 0x130b0
  323. MX6QDL_PAD_CSI0_DAT4__AUD3_TXC 0x130b0
  324. MX6QDL_PAD_CSI0_DAT5__AUD3_TXD 0x110b0
  325. MX6QDL_PAD_CSI0_DAT6__AUD3_TXFS 0x130b0
  326. >;
  327. };
  328. pinctrl_backlight: backlightgrp {
  329. fsl,pins = <
  330. MX6QDL_PAD_DISP0_DAT7__GPIO4_IO28 0x1b0b0
  331. >;
  332. };
  333. pinctrl_can2: can2grp {
  334. fsl,pins = <
  335. MX6QDL_PAD_KEY_COL4__FLEXCAN2_TX 0x1b008
  336. MX6QDL_PAD_KEY_ROW4__FLEXCAN2_RX 0x1b008
  337. >;
  338. };
  339. pinctrl_can3: can3grp {
  340. fsl,pins = <
  341. MX6QDL_PAD_EIM_D20__GPIO3_IO20 0x1b0b1
  342. >;
  343. };
  344. pinctrl_ecspi1: ecspi1grp {
  345. fsl,pins = <
  346. MX6QDL_PAD_EIM_D17__ECSPI1_MISO 0x100b1
  347. MX6QDL_PAD_EIM_D18__ECSPI1_MOSI 0x100b1
  348. MX6QDL_PAD_EIM_D16__ECSPI1_SCLK 0x100b1
  349. /* CS */
  350. MX6QDL_PAD_EIM_D19__GPIO3_IO19 0x000b1
  351. >;
  352. };
  353. pinctrl_ecspi2: ecspi2grp {
  354. fsl,pins = <
  355. MX6QDL_PAD_EIM_OE__ECSPI2_MISO 0x100b1
  356. MX6QDL_PAD_EIM_CS0__ECSPI2_SCLK 0x100b1
  357. MX6QDL_PAD_EIM_CS1__ECSPI2_MOSI 0x100b1
  358. MX6QDL_PAD_EIM_RW__GPIO2_IO26 0x000b1
  359. >;
  360. };
  361. pinctrl_ecspi2_cs: ecspi2csgrp {
  362. fsl,pins = <
  363. /* ADC128S022 CS */
  364. MX6QDL_PAD_DISP0_DAT4__GPIO4_IO25 0x1b0b1
  365. >;
  366. };
  367. pinctrl_ecspi3: ecspi3grp {
  368. fsl,pins = <
  369. MX6QDL_PAD_DISP0_DAT0__ECSPI3_SCLK 0x100b1
  370. MX6QDL_PAD_DISP0_DAT1__ECSPI3_MOSI 0x100b1
  371. MX6QDL_PAD_DISP0_DAT2__ECSPI3_MISO 0x100b1
  372. MX6QDL_PAD_DISP0_DAT3__GPIO4_IO24 0x000b1
  373. >;
  374. };
  375. pinctrl_enet: enetgrp {
  376. fsl,pins = <
  377. MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b030
  378. MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b030
  379. MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b030
  380. MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b030
  381. MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b030
  382. MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b030
  383. MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x10030
  384. MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x10030
  385. MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x10030
  386. MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x10030
  387. MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x10030
  388. MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x10030
  389. MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x10030
  390. MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x10030
  391. MX6QDL_PAD_ENET_MDC__ENET_MDC 0x10030
  392. /* Phy reset */
  393. MX6QDL_PAD_ENET_CRS_DV__GPIO1_IO25 0x1b0b0
  394. MX6QDL_PAD_ENET_TX_EN__GPIO1_IO28 0x1b0b1
  395. >;
  396. };
  397. pinctrl_hdmi: hdmigrp {
  398. fsl,pins = <
  399. /* NOTE: DDC is done via I2C2, so DON'T
  400. * configure DDC pins for HDMI!
  401. */
  402. MX6QDL_PAD_EIM_A25__HDMI_TX_CEC_LINE 0x1f8b0
  403. >;
  404. };
  405. /* DDC */
  406. pinctrl_i2c2: i2c2grp {
  407. fsl,pins = <
  408. MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1
  409. MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1
  410. >;
  411. };
  412. pinctrl_leds: ledsgrp {
  413. fsl,pins = <
  414. MX6QDL_PAD_GPIO_8__GPIO1_IO08 0x1b0b0
  415. MX6QDL_PAD_GPIO_9__GPIO1_IO09 0x1b0b0
  416. >;
  417. };
  418. pinctrl_pwm1: pwm1grp {
  419. fsl,pins = <
  420. MX6QDL_PAD_DISP0_DAT8__PWM1_OUT 0x1b0b0
  421. >;
  422. };
  423. pinctrl_spdif: spdifgrp {
  424. fsl,pins = <
  425. MX6QDL_PAD_GPIO_16__SPDIF_IN 0x1b0b0
  426. MX6QDL_PAD_GPIO_19__SPDIF_OUT 0x1b0b0
  427. >;
  428. };
  429. pinctrl_uart2: uart2grp {
  430. fsl,pins = <
  431. MX6QDL_PAD_EIM_D26__UART2_RX_DATA 0x1b0b1
  432. MX6QDL_PAD_EIM_D27__UART2_TX_DATA 0x1b0b1
  433. MX6QDL_PAD_EIM_D28__UART2_DTE_CTS_B 0x1b0b1
  434. MX6QDL_PAD_EIM_D29__UART2_DTE_RTS_B 0x1b0b1
  435. >;
  436. };
  437. pinctrl_uart5: uart5grp {
  438. fsl,pins = <
  439. MX6QDL_PAD_KEY_COL1__UART5_TX_DATA 0x1b0b1
  440. MX6QDL_PAD_KEY_ROW1__UART5_RX_DATA 0x1b0b1
  441. >;
  442. };
  443. pinctrl_usbotg_id: usbotgidgrp {
  444. fsl,pins = <
  445. MX6QDL_PAD_ENET_RX_ER__USB_OTG_ID 0x1f058
  446. >;
  447. };
  448. pinctrl_usdhc2: usdhc2grp {
  449. fsl,pins = <
  450. MX6QDL_PAD_SD2_CMD__SD2_CMD 0x170b9
  451. MX6QDL_PAD_SD2_CLK__SD2_CLK 0x100b9
  452. MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x170b9
  453. MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x170b9
  454. MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x170b9
  455. MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x170b9
  456. >;
  457. };
  458. pinctrl_wifi: wifigrp {
  459. fsl,pins = <
  460. /* WL12xx IRQ */
  461. MX6QDL_PAD_ENET_TXD0__GPIO1_IO30 0x10880
  462. >;
  463. };
  464. pinctrl_wifi_npd: wifinpd {
  465. fsl,pins = <
  466. MX6QDL_PAD_ENET_RXD1__GPIO1_IO26 0x1b8b0
  467. >;
  468. };
  469. };