imx6q-pistachio.dts 16 KB

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  1. /*
  2. * Copyright (C) 2017 NutsBoard.Org
  3. *
  4. * Author: Wig Cheng <[email protected]>
  5. *
  6. * This file is dual-licensed: you can use it either under the terms
  7. * of the GPL or the X11 license, at your option. Note that this dual
  8. * licensing only applies to this file, and not this project as a
  9. * whole.
  10. *
  11. * a) This file is free software; you can redistribute it and/or
  12. * modify it under the terms of the GNU General Public License as
  13. * published by the Free Software Foundation; either version 2 of the
  14. * License, or (at your option) any later version.
  15. *
  16. * This file is distributed in the hope that it will be useful,
  17. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  18. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  19. * GNU General Public License for more details.
  20. *
  21. * Or, alternatively,
  22. *
  23. * b) Permission is hereby granted, free of charge, to any person
  24. * obtaining a copy of this software and associated documentation
  25. * files (the "Software"), to deal in the Software without
  26. * restriction, including without limitation the rights to use,
  27. * copy, modify, merge, publish, distribute, sublicense, and/or
  28. * sell copies of the Software, and to permit persons to whom the
  29. * Software is furnished to do so, subject to the following
  30. * conditions:
  31. *
  32. * The above copyright notice and this permission notice shall be
  33. * included in all copies or substantial portions of the Software.
  34. *
  35. * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  36. * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
  37. * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  38. * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
  39. * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
  40. * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  41. * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  42. * OTHER DEALINGS IN THE SOFTWARE.
  43. */
  44. /dts-v1/;
  45. #include <dt-bindings/gpio/gpio.h>
  46. #include <dt-bindings/input/input.h>
  47. #include "imx6q.dtsi"
  48. / {
  49. model = "NutsBoard i.MX6 Quad Pistachio board";
  50. compatible = "nutsboard,imx6q-pistachio", "fsl,imx6q";
  51. chosen {
  52. stdout-path = &uart4;
  53. };
  54. memory@10000000 {
  55. device_type = "memory";
  56. reg = <0x10000000 0x80000000>;
  57. };
  58. reg_3p3v: regulator-3p3v {
  59. compatible = "regulator-fixed";
  60. regulator-name = "3P3V";
  61. regulator-min-microvolt = <3300000>;
  62. regulator-max-microvolt = <3300000>;
  63. };
  64. reg_1p8v: regulator-1p8v {
  65. compatible = "regulator-fixed";
  66. regulator-name = "1P8V";
  67. regulator-min-microvolt = <1800000>;
  68. regulator-max-microvolt = <1800000>;
  69. };
  70. wlan_en_reg: regulator-wlan_en {
  71. compatible = "regulator-fixed";
  72. regulator-name = "wlan-en-regulator";
  73. regulator-min-microvolt = <1800000>;
  74. regulator-max-microvolt = <1800000>;
  75. gpio = <&gpio2 24 GPIO_ACTIVE_HIGH>;
  76. startup-delay-us = <70000>;
  77. enable-active-high;
  78. };
  79. reg_usb_otg_vbus: regulator-usb_vbus {
  80. compatible = "regulator-fixed";
  81. regulator-name = "usb_otg_vbus";
  82. regulator-min-microvolt = <5000000>;
  83. regulator-max-microvolt = <5000000>;
  84. gpio = <&gpio3 22 GPIO_ACTIVE_HIGH>;
  85. enable-active-high;
  86. vin-supply = <&swbst_reg>;
  87. };
  88. gpio-keys {
  89. compatible = "gpio-keys";
  90. pinctrl-names = "default";
  91. pinctrl-0 = <&pinctrl_gpio_keys>;
  92. key-power {
  93. label = "Power Button";
  94. gpios = <&gpio2 12 GPIO_ACTIVE_LOW>;
  95. wakeup-source;
  96. linux,code = <KEY_POWER>;
  97. };
  98. };
  99. sound {
  100. compatible = "fsl,imx-sgtl5000",
  101. "fsl,imx-audio-sgtl5000";
  102. model = "audio-sgtl5000";
  103. ssi-controller = <&ssi1>;
  104. audio-codec = <&codec>;
  105. audio-routing =
  106. "MIC_IN", "Mic Jack",
  107. "Mic Jack", "Mic Bias",
  108. "Headphone Jack", "HP_OUT";
  109. mux-int-port = <1>;
  110. mux-ext-port = <3>;
  111. };
  112. backlight_lvds: backlight-lvds {
  113. compatible = "pwm-backlight";
  114. pwms = <&pwm1 0 50000>;
  115. brightness-levels = <
  116. 0 /*1 2 3 4 5 6*/ 7 8 9
  117. 10 11 12 13 14 15 16 17 18 19
  118. 20 21 22 23 24 25 26 27 28 29
  119. 30 31 32 33 34 35 36 37 38 39
  120. 40 41 42 43 44 45 46 47 48 49
  121. 50 51 52 53 54 55 56 57 58 59
  122. 60 61 62 63 64 65 66 67 68 69
  123. 70 71 72 73 74 75 76 77 78 79
  124. 80 81 82 83 84 85 86 87 88 89
  125. 90 91 92 93 94 95 96 97 98 99
  126. 100
  127. >;
  128. default-brightness-level = <94>;
  129. status = "okay";
  130. };
  131. panel {
  132. compatible = "hannstar,hsd100pxn1";
  133. backlight = <&backlight_lvds>;
  134. port {
  135. panel_in: endpoint {
  136. remote-endpoint = <&lvds0_out>;
  137. };
  138. };
  139. };
  140. };
  141. &audmux {
  142. pinctrl-names = "default";
  143. pinctrl-0 = <&pinctrl_audmux>;
  144. status = "okay";
  145. };
  146. &can2 {
  147. pinctrl-names = "default";
  148. pinctrl-0 = <&pinctrl_flexcan2>;
  149. status = "okay";
  150. };
  151. &clks {
  152. assigned-clocks = <&clks IMX6QDL_CLK_LDB_DI0_SEL>,
  153. <&clks IMX6QDL_CLK_LDB_DI1_SEL>;
  154. assigned-clock-parents = <&clks IMX6QDL_CLK_PLL3_USB_OTG>,
  155. <&clks IMX6QDL_CLK_PLL3_USB_OTG>;
  156. };
  157. &fec {
  158. pinctrl-names = "default";
  159. pinctrl-0 = <&pinctrl_enet>;
  160. phy-mode = "rgmii";
  161. status = "okay";
  162. };
  163. &hdmi {
  164. ddc-i2c-bus = <&i2c2>;
  165. status = "okay";
  166. };
  167. &i2c1 {
  168. clock-frequency = <100000>;
  169. pinctrl-names = "default";
  170. pinctrl-0 = <&pinctrl_i2c1>;
  171. status = "okay";
  172. codec: sgtl5000@a {
  173. compatible = "fsl,sgtl5000";
  174. pinctrl-names = "default";
  175. pinctrl-0 = <&pinctrl_i2c1_sgtl5000>;
  176. reg = <0x0a>;
  177. clocks = <&clks IMX6QDL_CLK_CKO>;
  178. VDDA-supply = <&reg_1p8v>;
  179. VDDIO-supply = <&reg_1p8v>;
  180. };
  181. };
  182. &i2c2 {
  183. clock-frequency = <100000>;
  184. pinctrl-names = "default";
  185. pinctrl-0 = <&pinctrl_i2c2>;
  186. status = "okay";
  187. pmic: pfuze100@8 {
  188. compatible = "fsl,pfuze100";
  189. reg = <0x08>;
  190. regulators {
  191. sw1a_reg: sw1ab {
  192. regulator-min-microvolt = <300000>;
  193. regulator-max-microvolt = <1875000>;
  194. regulator-boot-on;
  195. regulator-always-on;
  196. regulator-ramp-delay = <6250>;
  197. };
  198. sw1c_reg: sw1c {
  199. regulator-min-microvolt = <300000>;
  200. regulator-max-microvolt = <1875000>;
  201. regulator-boot-on;
  202. regulator-always-on;
  203. regulator-ramp-delay = <6250>;
  204. };
  205. sw2_reg: sw2 {
  206. regulator-min-microvolt = <800000>;
  207. regulator-max-microvolt = <3300000>;
  208. regulator-boot-on;
  209. regulator-always-on;
  210. regulator-ramp-delay = <6250>;
  211. };
  212. sw3a_reg: sw3a {
  213. regulator-min-microvolt = <400000>;
  214. regulator-max-microvolt = <1975000>;
  215. regulator-boot-on;
  216. regulator-always-on;
  217. };
  218. sw3b_reg: sw3b {
  219. regulator-min-microvolt = <400000>;
  220. regulator-max-microvolt = <1975000>;
  221. regulator-boot-on;
  222. regulator-always-on;
  223. };
  224. sw4_reg: sw4 {
  225. regulator-min-microvolt = <800000>;
  226. regulator-max-microvolt = <3300000>;
  227. };
  228. swbst_reg: swbst {
  229. regulator-min-microvolt = <5000000>;
  230. regulator-max-microvolt = <5150000>;
  231. };
  232. snvs_reg: vsnvs {
  233. regulator-min-microvolt = <1000000>;
  234. regulator-max-microvolt = <3000000>;
  235. regulator-boot-on;
  236. regulator-always-on;
  237. };
  238. vref_reg: vrefddr {
  239. regulator-boot-on;
  240. regulator-always-on;
  241. };
  242. vgen1_reg: vgen1 {
  243. regulator-min-microvolt = <800000>;
  244. regulator-max-microvolt = <1550000>;
  245. };
  246. vgen2_reg: vgen2 {
  247. regulator-min-microvolt = <800000>;
  248. regulator-max-microvolt = <1550000>;
  249. };
  250. vgen3_reg: vgen3 {
  251. regulator-min-microvolt = <1800000>;
  252. regulator-max-microvolt = <3300000>;
  253. };
  254. vgen4_reg: vgen4 {
  255. regulator-min-microvolt = <1800000>;
  256. regulator-max-microvolt = <3300000>;
  257. regulator-always-on;
  258. };
  259. vgen5_reg: vgen5 {
  260. regulator-min-microvolt = <1800000>;
  261. regulator-max-microvolt = <3300000>;
  262. regulator-always-on;
  263. };
  264. vgen6_reg: vgen6 {
  265. regulator-min-microvolt = <1800000>;
  266. regulator-max-microvolt = <3300000>;
  267. regulator-always-on;
  268. };
  269. };
  270. };
  271. ar1021@4d {
  272. compatible = "microchip,ar1021-i2c";
  273. reg = <0x4d>;
  274. interrupt-parent = <&gpio6>;
  275. interrupts = <8 IRQ_TYPE_EDGE_FALLING>;
  276. };
  277. };
  278. &i2c3 {
  279. clock-frequency = <100000>;
  280. pinctrl-names = "default";
  281. pinctrl-0 = <&pinctrl_i2c3>;
  282. status = "okay";
  283. };
  284. &iomuxc {
  285. pinctrl-names = "default";
  286. pinctrl_hog: hoggrp {
  287. fsl,pins = <
  288. MX6QDL_PAD_EIM_D22__GPIO3_IO22 0x1b0b0 /*pcie power*/
  289. MX6QDL_PAD_EIM_A25__GPIO5_IO02 0x1b0b0 /*LCD power*/
  290. MX6QDL_PAD_EIM_D16__GPIO3_IO16 0x1b0b0 /*backlight power*/
  291. MX6QDL_PAD_GPIO_2__GPIO1_IO02 0x1b0b1 /*SD3 CD pin*/
  292. MX6QDL_PAD_KEY_COL2__GPIO4_IO10 0x1b0b0 /*codec power*/
  293. MX6QDL_PAD_EIM_A16__GPIO2_IO22 0x1b0b0 /*touch reset*/
  294. MX6QDL_PAD_NANDF_ALE__GPIO6_IO08 0x1b0b01 /*touch irq*/
  295. MX6QDL_PAD_GPIO_7__GPIO1_IO07 0x1b0b0/*backlight pwr*/
  296. MX6QDL_PAD_GPIO_16__GPIO7_IO11 0x1b0b0 /*gpio 5V_1*/
  297. MX6QDL_PAD_EIM_A19__GPIO2_IO19 0x1b0b0 /*gpio 5V_2*/
  298. MX6QDL_PAD_EIM_A24__GPIO5_IO04 0x1b0b0 /*gpio 5V_3*/
  299. MX6QDL_PAD_GPIO_17__GPIO7_IO12 0x1b0b0 /*gpio 5V_4*/
  300. MX6QDL_PAD_NANDF_CLE__GPIO6_IO07 0x1b0b0 /*AUX_5V_EN*/
  301. MX6QDL_PAD_NANDF_WP_B__GPIO6_IO09 0x1b0b0 /*AUX_5VB_EN*/
  302. MX6QDL_PAD_NANDF_RB0__GPIO6_IO10 0x1b0b0 /*AUX_3V3_EN*/
  303. MX6QDL_PAD_EIM_D21__GPIO3_IO21 0x1b0b0 /*I2C expander pwr*/
  304. >;
  305. };
  306. pinctrl_audmux: audmuxgrp {
  307. fsl,pins = <
  308. MX6QDL_PAD_CSI0_DAT7__AUD3_RXD 0x130b0
  309. MX6QDL_PAD_CSI0_DAT4__AUD3_TXC 0x130b0
  310. MX6QDL_PAD_CSI0_DAT5__AUD3_TXD 0x110b0
  311. MX6QDL_PAD_CSI0_DAT6__AUD3_TXFS 0x130b0
  312. >;
  313. };
  314. pinctrl_ecspi1: ecspi1grp {
  315. fsl,pins = <
  316. MX6QDL_PAD_KEY_COL1__ECSPI1_MISO 0x100b1
  317. MX6QDL_PAD_KEY_ROW0__ECSPI1_MOSI 0x100b1
  318. MX6QDL_PAD_KEY_COL0__ECSPI1_SCLK 0x100b1
  319. MX6QDL_PAD_KEY_ROW1__GPIO4_IO09 0x1b0b0
  320. >;
  321. };
  322. pinctrl_enet: enetgrp {
  323. fsl,pins = <
  324. MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b8b0
  325. MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0
  326. /* AR8035 reset */
  327. MX6QDL_PAD_EIM_A20__GPIO2_IO18 0x130b0
  328. /* AR8035 interrupt */
  329. MX6QDL_PAD_EIM_CS0__GPIO2_IO23 0x1b0b1
  330. MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b030
  331. MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b030
  332. MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b030
  333. MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b030
  334. MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b030
  335. MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b030
  336. /* AR8035 CLK_25M --> ENET_REF_CLK (V22) */
  337. MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x0a0b1
  338. /* AR8035 pin strapping: IO voltage: pull up */
  339. MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b030
  340. /* AR8035 pin strapping: PHYADDR#0: pull down */
  341. MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x13030
  342. /* AR8035 pin strapping: PHYADDR#1: pull down */
  343. MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x13030
  344. /* AR8035 pin strapping: MODE#1: pull up */
  345. MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b030
  346. /* AR8035 pin strapping: MODE#3: pull up */
  347. MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b030
  348. /* AR8035 pin strapping: MODE#0: pull down */
  349. MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x13030
  350. >;
  351. };
  352. pinctrl_flexcan2: flexcan2grp {
  353. fsl,pins = <
  354. MX6QDL_PAD_KEY_COL4__FLEXCAN2_TX 0x1b0b0
  355. MX6QDL_PAD_KEY_ROW4__FLEXCAN2_RX 0x1b0b0
  356. >;
  357. };
  358. pinctrl_gpio_keys: gpio_keysgrp {
  359. fsl,pins = <
  360. MX6QDL_PAD_SD4_DAT4__GPIO2_IO12 0x1b0b0
  361. >;
  362. };
  363. pinctrl_hdmi_cec: hdmicecgrp {
  364. fsl,pins = <
  365. MX6QDL_PAD_KEY_ROW2__HDMI_TX_CEC_LINE 0x108b0
  366. >;
  367. };
  368. pinctrl_i2c1: i2c1grp {
  369. fsl,pins = <
  370. MX6QDL_PAD_CSI0_DAT8__I2C1_SDA 0x4001b8b1
  371. MX6QDL_PAD_CSI0_DAT9__I2C1_SCL 0x4001b8b1
  372. >;
  373. };
  374. pinctrl_i2c2: i2c2grp {
  375. fsl,pins = <
  376. MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1
  377. MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1
  378. >;
  379. };
  380. pinctrl_i2c3: i2c3grp {
  381. fsl,pins = <
  382. MX6QDL_PAD_GPIO_3__I2C3_SCL 0x4001b8b1
  383. MX6QDL_PAD_GPIO_6__I2C3_SDA 0x4001b8b1
  384. >;
  385. };
  386. pinctrl_i2c1_sgtl5000: i2c1-sgtl5000grp {
  387. fsl,pins = <
  388. MX6QDL_PAD_GPIO_0__CCM_CLKO1 0x000b0 /* sys_mclk */
  389. MX6QDL_PAD_SD3_RST__GPIO7_IO08 0x130b0 /*headphone det*/
  390. MX6QDL_PAD_GPIO_8__GPIO1_IO08 0x130b0 /*microphone det*/
  391. >;
  392. };
  393. pinctrl_pwm1: pwm1grp {
  394. fsl,pins = <
  395. MX6QDL_PAD_GPIO_9__PWM1_OUT 0x1b0b1
  396. >;
  397. };
  398. pinctrl_uart1: uart1grp {
  399. fsl,pins = <
  400. MX6QDL_PAD_CSI0_DAT10__UART1_RX_DATA 0x1b0b1
  401. MX6QDL_PAD_CSI0_DAT11__UART1_TX_DATA 0x1b0b1
  402. MX6QDL_PAD_EIM_D20__UART1_CTS_B 0x1b0b1
  403. MX6QDL_PAD_EIM_D19__UART1_RTS_B 0x1b0b1
  404. MX6QDL_PAD_EIM_D23__UART1_DCD_B 0x1b0b0
  405. MX6QDL_PAD_EIM_D24__UART1_DTR_B 0x1b0b0
  406. MX6QDL_PAD_EIM_D25__UART1_DSR_B 0x1b0b0
  407. >;
  408. };
  409. pinctrl_uart2: uart2grp {
  410. fsl,pins = <
  411. MX6QDL_PAD_EIM_D26__UART2_TX_DATA 0x1b0b1
  412. MX6QDL_PAD_EIM_D27__UART2_RX_DATA 0x1b0b1
  413. MX6QDL_PAD_EIM_D28__UART2_CTS_B 0x1b0b1
  414. MX6QDL_PAD_EIM_D29__UART2_RTS_B 0x1b0b1
  415. >;
  416. };
  417. pinctrl_uart3: uart3grp {
  418. fsl,pins = <
  419. MX6QDL_PAD_SD4_CLK__UART3_RX_DATA 0x1b0b1
  420. MX6QDL_PAD_SD4_CMD__UART3_TX_DATA 0x1b0b1
  421. MX6QDL_PAD_EIM_D30__UART3_CTS_B 0x1b0b1
  422. MX6QDL_PAD_EIM_D31__UART3_RTS_B 0x1b0b1
  423. >;
  424. };
  425. pinctrl_uart4: uart4grp {
  426. fsl,pins = <
  427. MX6QDL_PAD_CSI0_DAT12__UART4_TX_DATA 0x1b0b1
  428. MX6QDL_PAD_CSI0_DAT13__UART4_RX_DATA 0x1b0b1
  429. MX6QDL_PAD_CSI0_DAT16__UART4_RTS_B 0x1b0b1
  430. MX6QDL_PAD_CSI0_DAT17__UART4_CTS_B 0x1b0b1
  431. >;
  432. };
  433. pinctrl_uart5: uart5grp {
  434. fsl,pins = <
  435. MX6QDL_PAD_CSI0_DAT14__UART5_TX_DATA 0x1b0b1
  436. MX6QDL_PAD_CSI0_DAT15__UART5_RX_DATA 0x1b0b1
  437. MX6QDL_PAD_CSI0_DAT18__UART5_RTS_B 0x1b0b1
  438. MX6QDL_PAD_CSI0_DAT19__UART5_CTS_B 0x1b0b1
  439. MX6QDL_PAD_EIM_A21__GPIO2_IO17 0x15059 /*BT_EN*/
  440. >;
  441. };
  442. pinctrl_usbotg: usbotggrp {
  443. fsl,pins = <
  444. MX6QDL_PAD_ENET_RX_ER__USB_OTG_ID 0x17059
  445. >;
  446. };
  447. pinctrl_usdhc1: usdhc1grp {
  448. fsl,pins = <
  449. MX6QDL_PAD_SD1_CMD__SD1_CMD 0x17059
  450. MX6QDL_PAD_SD1_CLK__SD1_CLK 0x10059
  451. MX6QDL_PAD_SD1_DAT0__SD1_DATA0 0x17059
  452. MX6QDL_PAD_SD1_DAT1__SD1_DATA1 0x17059
  453. MX6QDL_PAD_SD1_DAT2__SD1_DATA2 0x17059
  454. MX6QDL_PAD_SD1_DAT3__SD1_DATA3 0x17059
  455. MX6QDL_PAD_NANDF_D0__SD1_DATA4 0x17059
  456. MX6QDL_PAD_NANDF_D1__SD1_DATA5 0x17059
  457. MX6QDL_PAD_NANDF_D2__SD1_DATA6 0x17059
  458. MX6QDL_PAD_NANDF_D3__SD1_DATA7 0x17059
  459. >;
  460. };
  461. pinctrl_usdhc2: usdhc2grp {
  462. fsl,pins = <
  463. MX6QDL_PAD_SD2_CMD__SD2_CMD 0x17059
  464. MX6QDL_PAD_SD2_CLK__SD2_CLK 0x10059
  465. MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x17059
  466. MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x17059
  467. MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x17059
  468. MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x17059
  469. MX6QDL_PAD_EIM_RW__GPIO2_IO26 0x15059 /*WL_EN_LDO*/
  470. MX6QDL_PAD_EIM_CS1__GPIO2_IO24 0x15059 /*WL_EN*/
  471. MX6QDL_PAD_CSI0_PIXCLK__GPIO5_IO18 0x15059 /*WL_IRQ*/
  472. >;
  473. };
  474. pinctrl_usdhc3: usdhc3grp {
  475. fsl,pins = <
  476. MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17071
  477. MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10071
  478. MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17071
  479. MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17071
  480. MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17071
  481. MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17071
  482. >;
  483. };
  484. pinctrl_wdog: wdoggrp {
  485. fsl,pins = <
  486. MX6QDL_PAD_GPIO_1__WDOG2_B 0x1b0b00
  487. >;
  488. };
  489. };
  490. &ldb {
  491. status = "okay";
  492. lvds-channel@1 {
  493. fsl,data-mapping = "spwg";
  494. fsl,data-width = <18>;
  495. status = "okay";
  496. port@4 {
  497. reg = <4>;
  498. lvds0_out: endpoint {
  499. remote-endpoint = <&panel_in>;
  500. };
  501. };
  502. };
  503. };
  504. &pwm1 {
  505. #pwm-cells = <2>;
  506. pinctrl-names = "default";
  507. pinctrl-0 = <&pinctrl_pwm1>;
  508. status = "okay";
  509. };
  510. &snvs_poweroff {
  511. status = "okay";
  512. };
  513. &ssi1 {
  514. status = "okay";
  515. };
  516. &uart1 {
  517. pinctrl-names = "default";
  518. pinctrl-0 = <&pinctrl_uart1>;
  519. uart-has-rtscts;
  520. fsl,dte-mode;
  521. status = "okay";
  522. };
  523. &uart2 {
  524. pinctrl-names = "default";
  525. pinctrl-0 = <&pinctrl_uart2>;
  526. uart-has-rtscts;
  527. status = "okay";
  528. };
  529. &uart3 {
  530. pinctrl-names = "default";
  531. pinctrl-0 = <&pinctrl_uart3>;
  532. uart-has-rtscts;
  533. status = "okay";
  534. };
  535. &uart4 {
  536. pinctrl-names = "default";
  537. pinctrl-0 = <&pinctrl_uart4>;
  538. uart-has-rtscts;
  539. status = "okay";
  540. };
  541. &uart5 {
  542. pinctrl-names = "default";
  543. pinctrl-0 = <&pinctrl_uart5>;
  544. uart-has-rtscts;
  545. status = "okay";
  546. };
  547. &usbotg {
  548. vbus-supply = <&reg_usb_otg_vbus>;
  549. pinctrl-names = "default";
  550. pinctrl-0 = <&pinctrl_usbotg>;
  551. disable-over-current;
  552. srp-disable;
  553. hnp-disable;
  554. adp-disable;
  555. status = "okay";
  556. };
  557. &usbh1 {
  558. status = "okay";
  559. };
  560. &usbphy1 {
  561. fsl,tx-d-cal = <0x5>;
  562. };
  563. &usbphy2 {
  564. fsl,tx-d-cal = <0x5>;
  565. };
  566. &usdhc1 {
  567. pinctrl-names = "default";
  568. pinctrl-0 = <&pinctrl_usdhc1>;
  569. bus-width = <8>;
  570. keep-power-in-suspend;
  571. vmmc-supply = <&reg_3p3v>;
  572. status = "okay";
  573. };
  574. &usdhc2 {
  575. pinctrl-names = "default";
  576. pinctrl-0 = <&pinctrl_usdhc2>;
  577. bus-width = <4>;
  578. vmmc-supply = <&wlan_en_reg>;
  579. no-1-8-v;
  580. keep-power-in-suspend;
  581. non-removable;
  582. cap-power-off-card;
  583. status = "okay";
  584. #address-cells = <1>;
  585. #size-cells = <0>;
  586. wlcore: wlcore@2 {
  587. compatible = "ti,wl1835";
  588. reg = <2>;
  589. interrupt-parent = <&gpio5>;
  590. interrupts = <18 IRQ_TYPE_LEVEL_HIGH>;
  591. ref-clock-frequency = <38400000>;
  592. tcxo-clock-frequency = <26000000>;
  593. };
  594. };
  595. &usdhc3 {
  596. pinctrl-names = "default";
  597. pinctrl-0 = <&pinctrl_usdhc3>;
  598. bus-width = <4>;
  599. cd-gpios = <&gpio1 2 GPIO_ACTIVE_LOW>;
  600. no-1-8-v;
  601. keep-power-in-suspend;
  602. wakeup-source;
  603. status = "okay";
  604. };
  605. &sata {
  606. status = "okay";
  607. };
  608. &wdog1 {
  609. status = "okay";
  610. };