imx6q-dmo-edmqmx6.dts 9.8 KB

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  1. // SPDX-License-Identifier: GPL-2.0-or-later
  2. /*
  3. * Copyright 2013 Data Modul AG
  4. */
  5. /dts-v1/;
  6. #include <dt-bindings/gpio/gpio.h>
  7. #include "imx6q.dtsi"
  8. / {
  9. model = "Data Modul eDM-QMX6 Board";
  10. compatible = "dmo,imx6q-edmqmx6", "fsl,imx6q";
  11. chosen {
  12. stdout-path = &uart2;
  13. };
  14. aliases {
  15. gpio7 = &stmpe_gpio1;
  16. gpio8 = &stmpe_gpio2;
  17. stmpe-i2c0 = &stmpe1;
  18. stmpe-i2c1 = &stmpe2;
  19. };
  20. memory@10000000 {
  21. device_type = "memory";
  22. reg = <0x10000000 0x80000000>;
  23. };
  24. regulators {
  25. compatible = "simple-bus";
  26. #address-cells = <1>;
  27. #size-cells = <0>;
  28. reg_3p3v: regulator@0 {
  29. compatible = "regulator-fixed";
  30. reg = <0>;
  31. regulator-name = "3P3V";
  32. regulator-min-microvolt = <3300000>;
  33. regulator-max-microvolt = <3300000>;
  34. regulator-always-on;
  35. };
  36. reg_usb_otg_switch: regulator@1 {
  37. compatible = "regulator-fixed";
  38. reg = <1>;
  39. regulator-name = "usb_otg_switch";
  40. regulator-min-microvolt = <5000000>;
  41. regulator-max-microvolt = <5000000>;
  42. gpio = <&gpio7 12 0>;
  43. regulator-boot-on;
  44. regulator-always-on;
  45. };
  46. reg_usb_host1: regulator@2 {
  47. compatible = "regulator-fixed";
  48. reg = <2>;
  49. regulator-name = "usb_host1_en";
  50. regulator-min-microvolt = <3300000>;
  51. regulator-max-microvolt = <3300000>;
  52. gpio = <&gpio3 31 0>;
  53. enable-active-high;
  54. };
  55. };
  56. gpio-leds {
  57. compatible = "gpio-leds";
  58. led-blue {
  59. label = "blue";
  60. gpios = <&stmpe_gpio1 8 GPIO_ACTIVE_HIGH>;
  61. linux,default-trigger = "heartbeat";
  62. };
  63. led-green {
  64. label = "green";
  65. gpios = <&stmpe_gpio1 9 GPIO_ACTIVE_HIGH>;
  66. };
  67. led-pink {
  68. label = "pink";
  69. gpios = <&stmpe_gpio1 10 GPIO_ACTIVE_HIGH>;
  70. };
  71. led-red {
  72. label = "red";
  73. gpios = <&stmpe_gpio1 11 GPIO_ACTIVE_HIGH>;
  74. };
  75. };
  76. };
  77. &can1 {
  78. pinctrl-names = "default";
  79. pinctrl-0 = <&pinctrl_can1>;
  80. status = "okay";
  81. };
  82. &ecspi5 {
  83. pinctrl-names = "default";
  84. pinctrl-0 = <&pinctrl_ecspi5>;
  85. cs-gpios = <&gpio1 12 GPIO_ACTIVE_LOW>;
  86. status = "okay";
  87. flash: flash@0 {
  88. compatible = "m25p80", "jedec,spi-nor";
  89. spi-max-frequency = <40000000>;
  90. reg = <0>;
  91. };
  92. };
  93. &fec {
  94. pinctrl-names = "default";
  95. pinctrl-0 = <&pinctrl_enet>;
  96. phy-mode = "rgmii-id";
  97. phy-reset-gpios = <&gpio1 25 GPIO_ACTIVE_LOW>;
  98. phy-supply = <&vgen2_1v2_eth>;
  99. status = "okay";
  100. };
  101. &i2c1 {
  102. clock-frequency = <100000>;
  103. pinctrl-names = "default";
  104. pinctrl-0 = <&pinctrl_i2c1>;
  105. status = "okay";
  106. };
  107. &i2c2 {
  108. clock-frequency = <100000>;
  109. pinctrl-names = "default";
  110. pinctrl-0 = <&pinctrl_i2c2
  111. &pinctrl_stmpe1
  112. &pinctrl_stmpe2
  113. &pinctrl_pfuze>;
  114. status = "okay";
  115. pmic: pfuze100@8 {
  116. compatible = "fsl,pfuze100";
  117. reg = <0x08>;
  118. interrupt-parent = <&gpio3>;
  119. interrupts = <20 8>;
  120. regulators {
  121. sw1a_reg: sw1ab {
  122. regulator-min-microvolt = <300000>;
  123. regulator-max-microvolt = <1875000>;
  124. regulator-boot-on;
  125. regulator-always-on;
  126. };
  127. sw1c_reg: sw1c {
  128. regulator-min-microvolt = <300000>;
  129. regulator-max-microvolt = <1875000>;
  130. regulator-boot-on;
  131. regulator-always-on;
  132. };
  133. sw2_reg: sw2 {
  134. regulator-min-microvolt = <800000>;
  135. regulator-max-microvolt = <3300000>;
  136. regulator-boot-on;
  137. regulator-always-on;
  138. };
  139. sw3a_reg: sw3a {
  140. regulator-min-microvolt = <400000>;
  141. regulator-max-microvolt = <1975000>;
  142. regulator-boot-on;
  143. regulator-always-on;
  144. };
  145. sw3b_reg: sw3b {
  146. regulator-min-microvolt = <400000>;
  147. regulator-max-microvolt = <1975000>;
  148. regulator-boot-on;
  149. regulator-always-on;
  150. };
  151. sw4_reg: sw4 {
  152. regulator-min-microvolt = <400000>;
  153. regulator-max-microvolt = <1975000>;
  154. regulator-always-on;
  155. };
  156. swbst_reg: swbst {
  157. regulator-min-microvolt = <5000000>;
  158. regulator-max-microvolt = <5150000>;
  159. regulator-always-on;
  160. };
  161. snvs_reg: vsnvs {
  162. regulator-min-microvolt = <1000000>;
  163. regulator-max-microvolt = <3000000>;
  164. regulator-boot-on;
  165. regulator-always-on;
  166. };
  167. vref_reg: vrefddr {
  168. regulator-boot-on;
  169. regulator-always-on;
  170. };
  171. vgen1_reg: vgen1 {
  172. regulator-min-microvolt = <800000>;
  173. regulator-max-microvolt = <1550000>;
  174. };
  175. vgen2_1v2_eth: vgen2 {
  176. regulator-min-microvolt = <800000>;
  177. regulator-max-microvolt = <1550000>;
  178. };
  179. vdd_high_in: vgen3 {
  180. regulator-min-microvolt = <1800000>;
  181. regulator-max-microvolt = <3300000>;
  182. regulator-boot-on;
  183. regulator-always-on;
  184. };
  185. vgen4_reg: vgen4 {
  186. regulator-min-microvolt = <1800000>;
  187. regulator-max-microvolt = <3300000>;
  188. regulator-always-on;
  189. };
  190. vgen5_reg: vgen5 {
  191. regulator-min-microvolt = <1800000>;
  192. regulator-max-microvolt = <3300000>;
  193. regulator-always-on;
  194. };
  195. vgen6_reg: vgen6 {
  196. regulator-min-microvolt = <1800000>;
  197. regulator-max-microvolt = <3300000>;
  198. regulator-always-on;
  199. };
  200. };
  201. };
  202. stmpe1: stmpe1601@40 {
  203. compatible = "st,stmpe1601";
  204. reg = <0x40>;
  205. interrupts = <30 0>;
  206. interrupt-parent = <&gpio3>;
  207. vcc-supply = <&sw2_reg>;
  208. vio-supply = <&sw2_reg>;
  209. stmpe_gpio1: stmpe_gpio {
  210. #gpio-cells = <2>;
  211. compatible = "st,stmpe-gpio";
  212. };
  213. };
  214. stmpe2: stmpe1601@44 {
  215. compatible = "st,stmpe1601";
  216. reg = <0x44>;
  217. interrupts = <2 0>;
  218. interrupt-parent = <&gpio5>;
  219. vcc-supply = <&sw2_reg>;
  220. vio-supply = <&sw2_reg>;
  221. stmpe_gpio2: stmpe_gpio {
  222. #gpio-cells = <2>;
  223. compatible = "st,stmpe-gpio";
  224. };
  225. };
  226. temp1: ad7414@4c {
  227. compatible = "ad,ad7414";
  228. reg = <0x4c>;
  229. };
  230. temp2: ad7414@4d {
  231. compatible = "ad,ad7414";
  232. reg = <0x4d>;
  233. };
  234. rtc: m41t62@68 {
  235. compatible = "st,m41t62";
  236. reg = <0x68>;
  237. };
  238. };
  239. &i2c3 {
  240. clock-frequency = <100000>;
  241. pinctrl-names = "default";
  242. pinctrl-0 = <&pinctrl_i2c3>;
  243. status = "okay";
  244. };
  245. &iomuxc {
  246. pinctrl-names = "default";
  247. pinctrl-0 = <&pinctrl_hog>;
  248. imx6q-dmo-edmqmx6 {
  249. pinctrl_hog: hoggrp {
  250. fsl,pins = <
  251. MX6QDL_PAD_EIM_A16__GPIO2_IO22 0x80000000
  252. MX6QDL_PAD_EIM_A17__GPIO2_IO21 0x80000000
  253. >;
  254. };
  255. pinctrl_can1: can1grp {
  256. fsl,pins = <
  257. MX6QDL_PAD_KEY_ROW2__FLEXCAN1_RX 0x1b0b0
  258. MX6QDL_PAD_GPIO_7__FLEXCAN1_TX 0x1b0b0
  259. >;
  260. };
  261. pinctrl_ecspi5: ecspi5rp-1 {
  262. fsl,pins = <
  263. MX6QDL_PAD_SD1_DAT0__ECSPI5_MISO 0x80000000
  264. MX6QDL_PAD_SD1_CMD__ECSPI5_MOSI 0x80000000
  265. MX6QDL_PAD_SD1_CLK__ECSPI5_SCLK 0x80000000
  266. MX6QDL_PAD_SD2_DAT3__GPIO1_IO12 0x80000000
  267. >;
  268. };
  269. pinctrl_enet: enetgrp {
  270. fsl,pins = <
  271. MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b030
  272. MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b030
  273. MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b030
  274. MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b030
  275. MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b030
  276. MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b030
  277. MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b030
  278. MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b030
  279. MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b030
  280. MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b030
  281. MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b030
  282. MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b030
  283. MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0
  284. MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0
  285. MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0
  286. MX6QDL_PAD_ENET_CRS_DV__GPIO1_IO25 0x1b0b0
  287. MX6QDL_PAD_GPIO_16__ENET_REF_CLK 0x4001b0a8
  288. >;
  289. };
  290. pinctrl_i2c1: i2c1grp {
  291. fsl,pins = <
  292. MX6QDL_PAD_EIM_D21__I2C1_SCL 0x4001b8b1
  293. MX6QDL_PAD_EIM_D28__I2C1_SDA 0x4001b8b1
  294. >;
  295. };
  296. pinctrl_i2c2: i2c2grp {
  297. fsl,pins = <
  298. MX6QDL_PAD_EIM_EB2__I2C2_SCL 0x4001b8b1
  299. MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1
  300. >;
  301. };
  302. pinctrl_i2c3: i2c3grp {
  303. fsl,pins = <
  304. MX6QDL_PAD_EIM_D17__I2C3_SCL 0x4001b8b1
  305. MX6QDL_PAD_GPIO_6__I2C3_SDA 0x4001b8b1
  306. >;
  307. };
  308. pinctrl_pcie: pciegrp {
  309. fsl,pins = <
  310. MX6QDL_PAD_KEY_COL1__GPIO4_IO08 0x100b1
  311. >;
  312. };
  313. pinctrl_pfuze: pfuze100grp1 {
  314. fsl,pins = <
  315. MX6QDL_PAD_EIM_D20__GPIO3_IO20 0x80000000
  316. >;
  317. };
  318. pinctrl_stmpe1: stmpe1grp {
  319. fsl,pins = <MX6QDL_PAD_EIM_D30__GPIO3_IO30 0x80000000>;
  320. };
  321. pinctrl_stmpe2: stmpe2grp {
  322. fsl,pins = <MX6QDL_PAD_EIM_A25__GPIO5_IO02 0x80000000>;
  323. };
  324. pinctrl_uart1: uart1grp {
  325. fsl,pins = <
  326. MX6QDL_PAD_SD3_DAT7__UART1_TX_DATA 0x1b0b1
  327. MX6QDL_PAD_SD3_DAT6__UART1_RX_DATA 0x1b0b1
  328. >;
  329. };
  330. pinctrl_uart2: uart2grp {
  331. fsl,pins = <
  332. MX6QDL_PAD_EIM_D26__UART2_TX_DATA 0x1b0b1
  333. MX6QDL_PAD_EIM_D27__UART2_RX_DATA 0x1b0b1
  334. >;
  335. };
  336. pinctrl_usbotg: usbotggrp {
  337. fsl,pins = <
  338. MX6QDL_PAD_ENET_RX_ER__USB_OTG_ID 0x17059
  339. >;
  340. };
  341. pinctrl_usdhc3: usdhc3grp {
  342. fsl,pins = <
  343. MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059
  344. MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10059
  345. MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059
  346. MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059
  347. MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059
  348. MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059
  349. >;
  350. };
  351. pinctrl_usdhc4: usdhc4grp {
  352. fsl,pins = <
  353. MX6QDL_PAD_SD4_CMD__SD4_CMD 0x17059
  354. MX6QDL_PAD_SD4_CLK__SD4_CLK 0x10059
  355. MX6QDL_PAD_SD4_DAT0__SD4_DATA0 0x17059
  356. MX6QDL_PAD_SD4_DAT1__SD4_DATA1 0x17059
  357. MX6QDL_PAD_SD4_DAT2__SD4_DATA2 0x17059
  358. MX6QDL_PAD_SD4_DAT3__SD4_DATA3 0x17059
  359. MX6QDL_PAD_SD4_DAT4__SD4_DATA4 0x17059
  360. MX6QDL_PAD_SD4_DAT5__SD4_DATA5 0x17059
  361. MX6QDL_PAD_SD4_DAT6__SD4_DATA6 0x17059
  362. MX6QDL_PAD_SD4_DAT7__SD4_DATA7 0x17059
  363. >;
  364. };
  365. };
  366. };
  367. &pcie {
  368. pinctrl-names = "default";
  369. pinctrl-0 = <&pinctrl_pcie>;
  370. reset-gpio = <&gpio4 8 GPIO_ACTIVE_LOW>;
  371. status = "okay";
  372. };
  373. &sata {
  374. status = "okay";
  375. };
  376. &uart1 {
  377. pinctrl-names = "default";
  378. pinctrl-0 = <&pinctrl_uart1>;
  379. status = "okay";
  380. };
  381. &uart2 {
  382. pinctrl-names = "default";
  383. pinctrl-0 = <&pinctrl_uart2>;
  384. status = "okay";
  385. };
  386. &usbh1 {
  387. vbus-supply = <&reg_usb_host1>;
  388. disable-over-current;
  389. dr_mode = "host";
  390. status = "okay";
  391. };
  392. &usbotg {
  393. pinctrl-names = "default";
  394. pinctrl-0 = <&pinctrl_usbotg>;
  395. disable-over-current;
  396. status = "okay";
  397. };
  398. &usdhc3 {
  399. pinctrl-names = "default";
  400. pinctrl-0 = <&pinctrl_usdhc3>;
  401. vmmc-supply = <&reg_3p3v>;
  402. status = "okay";
  403. };
  404. &usdhc4 {
  405. pinctrl-names = "default";
  406. pinctrl-0 = <&pinctrl_usdhc4>;
  407. vmmc-supply = <&reg_3p3v>;
  408. non-removable;
  409. bus-width = <8>;
  410. status = "okay";
  411. };