imx6-logicpd-baseboard.dtsi 12 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. //
  3. // Copyright (C) 2019 Logic PD, Inc.
  4. / {
  5. keyboard {
  6. compatible = "gpio-keys";
  7. button-0 {
  8. gpios = <&pcf8575 0 GPIO_ACTIVE_LOW>;
  9. label = "btn0";
  10. linux,code = <KEY_WAKEUP>;
  11. debounce-interval = <10>;
  12. wakeup-source;
  13. };
  14. button-1 {
  15. gpios = <&pcf8575 1 GPIO_ACTIVE_LOW>;
  16. label = "btn1";
  17. linux,code = <KEY_WAKEUP>;
  18. debounce-interval = <10>;
  19. wakeup-source;
  20. };
  21. button-2 {
  22. gpios = <&pcf8575 2 GPIO_ACTIVE_LOW>;
  23. label = "btn2";
  24. linux,code = <KEY_WAKEUP>;
  25. debounce-interval = <10>;
  26. wakeup-source;
  27. };
  28. button-3 {
  29. gpios = <&pcf8575 3 GPIO_ACTIVE_LOW>;
  30. label = "btn3";
  31. linux,code = <KEY_WAKEUP>;
  32. debounce-interval = <10>;
  33. wakeup-source;
  34. };
  35. };
  36. leds {
  37. compatible = "gpio-leds";
  38. gen-led0 {
  39. label = "led0";
  40. pinctrl-names = "default";
  41. pinctrl-0 = <&pinctrl_led0>;
  42. gpios = <&gpio1 30 GPIO_ACTIVE_HIGH>;
  43. linux,default-trigger = "cpu0";
  44. };
  45. gen-led1 {
  46. label = "led1";
  47. gpios = <&pcf8575 8 GPIO_ACTIVE_HIGH>;
  48. };
  49. gen-led2 {
  50. label = "led2";
  51. gpios = <&pcf8575 9 GPIO_ACTIVE_HIGH>;
  52. linux,default-trigger = "heartbeat";
  53. };
  54. gen-led3 {
  55. label = "led3";
  56. gpios = <&pcf8575 10 GPIO_ACTIVE_HIGH>;
  57. linux,default-trigger = "default-on";
  58. };
  59. };
  60. reg_usb_otg_vbus: regulator-otg-vbus {
  61. pinctrl-names = "default";
  62. pinctrl-0 = <&pinctrl_reg_usb_otg>;
  63. compatible = "regulator-fixed";
  64. regulator-name = "usb_otg_vbus";
  65. regulator-min-microvolt = <5000000>;
  66. regulator-max-microvolt = <5000000>;
  67. gpio = <&gpio4 15 GPIO_ACTIVE_HIGH>;
  68. enable-active-high;
  69. };
  70. reg_usb_h1_vbus: regulator-usb-h1-vbus {
  71. pinctrl-names = "default";
  72. pinctrl-0 = <&pinctrl_reg_usb_h1_vbus>;
  73. compatible = "regulator-fixed";
  74. regulator-name = "usb_h1_vbus";
  75. regulator-min-microvolt = <5000000>;
  76. regulator-max-microvolt = <5000000>;
  77. gpio = <&gpio7 12 GPIO_ACTIVE_HIGH>;
  78. startup-delay-us = <70000>;
  79. enable-active-high;
  80. };
  81. reg_3v3: regulator-3v3 {
  82. pinctrl-names = "default";
  83. pinctrl-0 = <&pinctrl_reg_3v3>;
  84. compatible = "regulator-fixed";
  85. regulator-name = "reg_3v3";
  86. regulator-min-microvolt = <3300000>;
  87. regulator-max-microvolt = <3300000>;
  88. gpio = <&gpio1 26 GPIO_ACTIVE_HIGH>;
  89. startup-delay-us = <70000>;
  90. enable-active-high;
  91. regulator-always-on;
  92. };
  93. reg_enet: regulator-ethernet {
  94. pinctrl-names = "default";
  95. pinctrl-0 = <&pinctrl_reg_enet>;
  96. compatible = "regulator-fixed";
  97. regulator-name = "ethernet-supply";
  98. regulator-min-microvolt = <3300000>;
  99. regulator-max-microvolt = <3300000>;
  100. gpio = <&gpio3 31 GPIO_ACTIVE_HIGH>;
  101. startup-delay-us = <70000>;
  102. enable-active-high;
  103. vin-supply = <&sw4_reg>;
  104. };
  105. reg_audio: regulator-audio {
  106. pinctrl-names = "default";
  107. pinctrl-0 = <&pinctrl_reg_audio>;
  108. compatible = "regulator-fixed";
  109. regulator-name = "3v3_aud";
  110. regulator-min-microvolt = <3300000>;
  111. regulator-max-microvolt = <3300000>;
  112. gpio = <&gpio1 29 GPIO_ACTIVE_HIGH>;
  113. enable-active-high;
  114. vin-supply = <&reg_3v3>;
  115. };
  116. reg_hdmi: regulator-hdmi {
  117. pinctrl-names = "default";
  118. pinctrl-0 = <&pinctrl_reg_hdmi>;
  119. compatible = "regulator-fixed";
  120. regulator-name = "hdmi-supply";
  121. regulator-min-microvolt = <3300000>;
  122. regulator-max-microvolt = <3300000>;
  123. gpio = <&gpio3 20 GPIO_ACTIVE_HIGH>;
  124. enable-active-high;
  125. vin-supply = <&reg_3v3>;
  126. };
  127. reg_uart3: regulator-uart3 {
  128. pinctrl-names = "default";
  129. pinctrl-0 = <&pinctrl_reg_uart3>;
  130. compatible = "regulator-fixed";
  131. regulator-name = "uart3-supply";
  132. gpio = <&gpio1 28 GPIO_ACTIVE_HIGH>;
  133. enable-active-high;
  134. regulator-always-on;
  135. vin-supply = <&reg_3v3>;
  136. };
  137. reg_1v8: regulator-1v8 {
  138. pinctrl-names = "default";
  139. pinctrl-0 = <&pinctrl_reg_1v8>;
  140. compatible = "regulator-fixed";
  141. regulator-name = "1v8-supply";
  142. gpio = <&gpio3 30 GPIO_ACTIVE_HIGH>;
  143. enable-active-high;
  144. regulator-always-on;
  145. vin-supply = <&reg_3v3>;
  146. };
  147. reg_pcie: regulator-pcie {
  148. compatible = "regulator-fixed";
  149. pinctrl-names = "default";
  150. pinctrl-0 = <&pinctrl_reg_pcie>;
  151. regulator-name = "mpcie_3v3";
  152. regulator-min-microvolt = <3300000>;
  153. regulator-max-microvolt = <3300000>;
  154. gpio = <&gpio1 2 GPIO_ACTIVE_HIGH>;
  155. enable-active-high;
  156. };
  157. reg_mipi: regulator-mipi {
  158. compatible = "regulator-fixed";
  159. pinctrl-names = "default";
  160. pinctrl-0 = <&pinctrl_reg_mipi>;
  161. regulator-name = "mipi_pwr_en";
  162. regulator-min-microvolt = <2800000>;
  163. regulator-max-microvolt = <2800000>;
  164. gpio = <&gpio3 19 GPIO_ACTIVE_HIGH>;
  165. enable-active-high;
  166. };
  167. sound {
  168. compatible = "fsl,imx-audio-wm8962";
  169. model = "wm8962-audio";
  170. ssi-controller = <&ssi2>;
  171. audio-codec = <&wm8962>;
  172. audio-routing =
  173. "Headphone Jack", "HPOUTL",
  174. "Headphone Jack", "HPOUTR",
  175. "Ext Spk", "SPKOUTL",
  176. "Ext Spk", "SPKOUTR",
  177. "AMIC", "MICBIAS",
  178. "IN3R", "AMIC";
  179. mux-int-port = <2>;
  180. mux-ext-port = <4>;
  181. };
  182. };
  183. &audmux {
  184. pinctrl-names = "default";
  185. pinctrl-0 = <&pinctrl_audmux>;
  186. status = "okay";
  187. };
  188. &ecspi1 {
  189. pinctrl-names = "default";
  190. pinctrl-0 = <&pinctrl_ecspi1>;
  191. cs-gpios = <&gpio4 9 GPIO_ACTIVE_LOW>;
  192. status = "disabled";
  193. };
  194. &fec {
  195. pinctrl-names = "default";
  196. pinctrl-0 = <&pinctrl_enet>;
  197. phy-mode = "rgmii-id";
  198. phy-reset-duration = <10>;
  199. phy-reset-gpios = <&gpio1 24 GPIO_ACTIVE_LOW>;
  200. phy-supply = <&reg_enet>;
  201. interrupt-parent = <&gpio1>;
  202. interrupts = <25 IRQ_TYPE_EDGE_FALLING>;
  203. status = "okay";
  204. };
  205. &i2c1 {
  206. pinctrl-names = "default";
  207. pinctrl-0 = <&pinctrl_i2c1>;
  208. clock-frequency = <400000>;
  209. status = "okay";
  210. wm8962: audio-codec@1a {
  211. compatible = "wlf,wm8962";
  212. reg = <0x1a>;
  213. clocks = <&clks IMX6QDL_CLK_CKO>;
  214. DCVDD-supply = <&reg_audio>;
  215. DBVDD-supply = <&reg_audio>;
  216. AVDD-supply = <&reg_audio>;
  217. CPVDD-supply = <&reg_audio>;
  218. MICVDD-supply = <&reg_audio>;
  219. PLLVDD-supply = <&reg_audio>;
  220. SPKVDD1-supply = <&reg_audio>;
  221. SPKVDD2-supply = <&reg_audio>;
  222. gpio-cfg = <
  223. 0x0000 /* 0:Default */
  224. 0x0000 /* 1:Default */
  225. 0x0000 /* 2:FN_DMICCLK */
  226. 0x0000 /* 3:Default */
  227. 0x0000 /* 4:FN_DMICCDAT */
  228. 0x0000 /* 5:Default */
  229. >;
  230. };
  231. };
  232. &i2c3 {
  233. ov5640: camera@10 {
  234. compatible = "ovti,ov5640";
  235. pinctrl-names = "default";
  236. pinctrl-0 = <&pinctrl_ov5640>;
  237. reg = <0x10>;
  238. clocks = <&clks IMX6QDL_CLK_CKO>;
  239. clock-names = "xclk";
  240. DOVDD-supply = <&reg_mipi>;
  241. AVDD-supply = <&reg_mipi>;
  242. DVDD-supply = <&reg_mipi>;
  243. reset-gpios = <&gpio3 26 GPIO_ACTIVE_LOW>;
  244. powerdown-gpios = <&gpio3 27 GPIO_ACTIVE_HIGH>;
  245. port {
  246. ov5640_to_mipi_csi2: endpoint {
  247. remote-endpoint = <&mipi_csi2_in>;
  248. clock-lanes = <0>;
  249. data-lanes = <1 2>;
  250. };
  251. };
  252. };
  253. pcf8575: gpio@20 {
  254. pinctrl-names = "default";
  255. pinctrl-0 = <&pinctrl_pcf8574>;
  256. compatible = "nxp,pcf8575";
  257. reg = <0x20>;
  258. interrupt-parent = <&gpio6>;
  259. interrupts = <31 IRQ_TYPE_EDGE_FALLING>;
  260. gpio-controller;
  261. #gpio-cells = <2>;
  262. interrupt-controller;
  263. #interrupt-cells = <2>;
  264. lines-initial-states = <0x0710>;
  265. wakeup-source;
  266. };
  267. };
  268. &ipu1_csi1_from_mipi_vc1 {
  269. clock-lanes = <0>;
  270. data-lanes = <1 2>;
  271. };
  272. &mipi_csi {
  273. status = "okay";
  274. port@0 {
  275. reg = <0>;
  276. mipi_csi2_in: endpoint {
  277. remote-endpoint = <&ov5640_to_mipi_csi2>;
  278. clock-lanes = <0>;
  279. data-lanes = <1 2>;
  280. };
  281. };
  282. };
  283. &pcie {
  284. pinctrl-names = "default";
  285. pinctrl-0 = <&pinctrl_pcie>;
  286. reset-gpio = <&gpio1 9 GPIO_ACTIVE_LOW>;
  287. vpcie-supply = <&reg_pcie>;
  288. status = "okay";
  289. };
  290. &pwm3 {
  291. pinctrl-names = "default";
  292. pinctrl-0 = <&pinctrl_pwm3>;
  293. };
  294. &snvs_pwrkey {
  295. status = "okay";
  296. };
  297. &ssi2 {
  298. status = "okay";
  299. };
  300. &uart3 {
  301. pinctrl-names = "default";
  302. pinctrl-0 = <&pinctrl_uart3>;
  303. status = "okay";
  304. };
  305. &usbh1 {
  306. vbus-supply = <&reg_usb_h1_vbus>;
  307. status = "okay";
  308. };
  309. &usbotg {
  310. vbus-supply = <&reg_usb_otg_vbus>;
  311. pinctrl-names = "default";
  312. pinctrl-0 = <&pinctrl_usbotg>;
  313. disable-over-current;
  314. dr_mode = "otg";
  315. status = "okay";
  316. };
  317. &usdhc2 {
  318. pinctrl-names = "default";
  319. pinctrl-0 = <&pinctrl_usdhc2>;
  320. pinctrl-1 = <&pinctrl_usdhc2_100mhz>;
  321. pinctrl-2 = <&pinctrl_usdhc2_200mhz>;
  322. vmmc-supply = <&reg_3v3>;
  323. no-1-8-v;
  324. keep-power-in-suspend;
  325. cd-gpios = <&gpio1 4 GPIO_ACTIVE_LOW>;
  326. status = "okay";
  327. };
  328. &iomuxc {
  329. pinctrl_audmux: audmuxgrp {
  330. fsl,pins = <
  331. MX6QDL_PAD_DISP0_DAT20__AUD4_TXC 0x130b0
  332. MX6QDL_PAD_DISP0_DAT21__AUD4_TXD 0x110b0
  333. MX6QDL_PAD_DISP0_DAT22__AUD4_TXFS 0x130b0
  334. MX6QDL_PAD_DISP0_DAT23__AUD4_RXD 0x130b0
  335. >;
  336. };
  337. pinctrl_ecspi1: ecspi1grp {
  338. fsl,pins = <
  339. MX6QDL_PAD_KEY_COL0__ECSPI1_SCLK 0x100b1
  340. MX6QDL_PAD_KEY_ROW0__ECSPI1_MOSI 0x100b1
  341. MX6QDL_PAD_KEY_COL1__ECSPI1_MISO 0x100b1
  342. MX6QDL_PAD_KEY_ROW1__GPIO4_IO09 0x1b0b0
  343. >;
  344. };
  345. pinctrl_enet: enetgrp {
  346. fsl,pins = <
  347. MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b8b0
  348. MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0
  349. MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b030
  350. MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b030
  351. MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b030
  352. MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b030
  353. MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b030
  354. MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x100b0
  355. MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b030
  356. MX6QDL_PAD_GPIO_16__ENET_REF_CLK 0x4001b0a8
  357. MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b030
  358. MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x13030
  359. MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x13030
  360. MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b030
  361. MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b030
  362. MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x13030
  363. MX6QDL_PAD_ENET_CRS_DV__GPIO1_IO25 0x1b0b0 /* ENET_INT */
  364. MX6QDL_PAD_ENET_RX_ER__GPIO1_IO24 0x1b0b0 /* ETHR_nRST */
  365. >;
  366. };
  367. pinctrl_i2c1: i2c1grp {
  368. fsl,pins = <
  369. MX6QDL_PAD_EIM_D21__I2C1_SCL 0x4001b8b1
  370. MX6QDL_PAD_EIM_D28__I2C1_SDA 0x4001b8b1
  371. >;
  372. };
  373. pinctrl_led0: led0grp {
  374. fsl,pins = <
  375. MX6QDL_PAD_ENET_TXD0__GPIO1_IO30 0x1b0b0
  376. >;
  377. };
  378. pinctrl_ov5640: ov5640grp {
  379. fsl,pins = <
  380. MX6QDL_PAD_EIM_D26__GPIO3_IO26 0x1b0b1
  381. MX6QDL_PAD_EIM_D27__GPIO3_IO27 0x1b0b1
  382. >;
  383. };
  384. pinctrl_pcf8574: pcf8575grp {
  385. fsl,pins = <
  386. MX6QDL_PAD_EIM_BCLK__GPIO6_IO31 0x1b0b0
  387. >;
  388. };
  389. pinctrl_pcie: pciegrp {
  390. fsl,pins = <
  391. MX6QDL_PAD_GPIO_8__GPIO1_IO08 0x1b0b0
  392. MX6QDL_PAD_GPIO_9__GPIO1_IO09 0x1b0b0
  393. >;
  394. };
  395. pinctrl_pwm3: pwm3grp {
  396. fsl,pins = <
  397. MX6QDL_PAD_SD4_DAT1__PWM3_OUT 0x1b0b1
  398. >;
  399. };
  400. pinctrl_reg_1v8: reg1v8grp {
  401. fsl,pins = <
  402. MX6QDL_PAD_EIM_D30__GPIO3_IO30 0x1b0b0
  403. >;
  404. };
  405. pinctrl_reg_3v3: reg3v3grp {
  406. fsl,pins = <
  407. MX6QDL_PAD_ENET_RXD1__GPIO1_IO26 0x1b0b0
  408. >;
  409. };
  410. pinctrl_reg_audio: reg-audiogrp {
  411. fsl,pins = <
  412. MX6QDL_PAD_ENET_TXD1__GPIO1_IO29 0x1b0b0
  413. >;
  414. };
  415. pinctrl_reg_enet: reg-enetgrp {
  416. fsl,pins = <
  417. MX6QDL_PAD_EIM_D31__GPIO3_IO31 0x1b0b0
  418. >;
  419. };
  420. pinctrl_reg_hdmi: reg-hdmigrp {
  421. fsl,pins = <
  422. MX6QDL_PAD_EIM_D20__GPIO3_IO20 0x1b0b0
  423. >;
  424. };
  425. pinctrl_reg_mipi: reg-mipigrp {
  426. fsl,pins = <MX6QDL_PAD_EIM_D19__GPIO3_IO19 0x1b0b1>;
  427. };
  428. pinctrl_reg_pcie: reg-pciegrp {
  429. fsl,pins = <
  430. MX6QDL_PAD_GPIO_2__GPIO1_IO02 0x1b0b0
  431. >;
  432. };
  433. pinctrl_reg_uart3: reguart3grp {
  434. fsl,pins = <
  435. MX6QDL_PAD_ENET_TX_EN__GPIO1_IO28 0x1b0b0
  436. >;
  437. };
  438. pinctrl_reg_usb_h1_vbus: usbh1grp {
  439. fsl,pins = <
  440. MX6QDL_PAD_GPIO_17__GPIO7_IO12 0x1b0b0
  441. >;
  442. };
  443. pinctrl_reg_usb_otg: reg-usb-otggrp {
  444. fsl,pins = <
  445. MX6QDL_PAD_KEY_ROW4__GPIO4_IO15 0x1b0b0
  446. >;
  447. };
  448. pinctrl_uart3: uart3grp {
  449. fsl,pins = <
  450. MX6QDL_PAD_EIM_D23__UART3_CTS_B 0x1b0b1
  451. MX6QDL_PAD_EIM_D24__UART3_TX_DATA 0x1b0b1
  452. MX6QDL_PAD_EIM_D25__UART3_RX_DATA 0x1b0b1
  453. MX6QDL_PAD_EIM_EB3__UART3_RTS_B 0x1b0b1
  454. >;
  455. };
  456. pinctrl_usbotg: usbotggrp {
  457. fsl,pins = <
  458. MX6QDL_PAD_GPIO_1__USB_OTG_ID 0xd17059
  459. >;
  460. };
  461. pinctrl_usdhc2: usdhc2grp {
  462. fsl,pins = <
  463. MX6QDL_PAD_GPIO_4__GPIO1_IO04 0x1b0b0 /* CD */
  464. MX6QDL_PAD_SD2_CMD__SD2_CMD 0x17069
  465. MX6QDL_PAD_SD2_CLK__SD2_CLK 0x10069
  466. MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x17069
  467. MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x17069
  468. MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x17069
  469. MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x17069
  470. >;
  471. };
  472. pinctrl_usdhc2_100mhz: h100-usdhc2-100mhz {
  473. fsl,pins = <
  474. MX6QDL_PAD_GPIO_4__GPIO1_IO04 0x1b0b0 /* CD */
  475. MX6QDL_PAD_SD2_CMD__SD2_CMD 0x170b9
  476. MX6QDL_PAD_SD2_CLK__SD2_CLK 0x100b9
  477. MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x170b9
  478. MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x170b9
  479. MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x170b9
  480. MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x170b9
  481. >;
  482. };
  483. pinctrl_usdhc2_200mhz: h100-usdhc2-200mhz {
  484. fsl,pins = <
  485. MX6QDL_PAD_GPIO_4__GPIO1_IO04 0x1b0b0 /* CD */
  486. MX6QDL_PAD_SD2_CMD__SD2_CMD 0x170f9
  487. MX6QDL_PAD_SD2_CLK__SD2_CLK 0x100f9
  488. MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x170f9
  489. MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x170f9
  490. MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x170f9
  491. MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x170f9
  492. >;
  493. };
  494. };