imx28.dtsi 33 KB

1234567891011121314151617181920212223242526272829303132333435363738394041424344454647484950515253545556575859606162636465666768697071727374757677787980818283848586878889909192939495969798991001011021031041051061071081091101111121131141151161171181191201211221231241251261271281291301311321331341351361371381391401411421431441451461471481491501511521531541551561571581591601611621631641651661671681691701711721731741751761771781791801811821831841851861871881891901911921931941951961971981992002012022032042052062072082092102112122132142152162172182192202212222232242252262272282292302312322332342352362372382392402412422432442452462472482492502512522532542552562572582592602612622632642652662672682692702712722732742752762772782792802812822832842852862872882892902912922932942952962972982993003013023033043053063073083093103113123133143153163173183193203213223233243253263273283293303313323333343353363373383393403413423433443453463473483493503513523533543553563573583593603613623633643653663673683693703713723733743753763773783793803813823833843853863873883893903913923933943953963973983994004014024034044054064074084094104114124134144154164174184194204214224234244254264274284294304314324334344354364374384394404414424434444454464474484494504514524534544554564574584594604614624634644654664674684694704714724734744754764774784794804814824834844854864874884894904914924934944954964974984995005015025035045055065075085095105115125135145155165175185195205215225235245255265275285295305315325335345355365375385395405415425435445455465475485495505515525535545555565575585595605615625635645655665675685695705715725735745755765775785795805815825835845855865875885895905915925935945955965975985996006016026036046056066076086096106116126136146156166176186196206216226236246256266276286296306316326336346356366376386396406416426436446456466476486496506516526536546556566576586596606616626636646656666676686696706716726736746756766776786796806816826836846856866876886896906916926936946956966976986997007017027037047057067077087097107117127137147157167177187197207217227237247257267277287297307317327337347357367377387397407417427437447457467477487497507517527537547557567577587597607617627637647657667677687697707717727737747757767777787797807817827837847857867877887897907917927937947957967977987998008018028038048058068078088098108118128138148158168178188198208218228238248258268278288298308318328338348358368378388398408418428438448458468478488498508518528538548558568578588598608618628638648658668678688698708718728738748758768778788798808818828838848858868878888898908918928938948958968978988999009019029039049059069079089099109119129139149159169179189199209219229239249259269279289299309319329339349359369379389399409419429439449459469479489499509519529539549559569579589599609619629639649659669679689699709719729739749759769779789799809819829839849859869879889899909919929939949959969979989991000100110021003100410051006100710081009101010111012101310141015101610171018101910201021102210231024102510261027102810291030103110321033103410351036103710381039104010411042104310441045104610471048104910501051105210531054105510561057105810591060106110621063106410651066106710681069107010711072107310741075107610771078107910801081108210831084108510861087108810891090109110921093109410951096109710981099110011011102110311041105110611071108110911101111111211131114111511161117111811191120112111221123112411251126112711281129113011311132113311341135113611371138113911401141114211431144114511461147114811491150115111521153115411551156115711581159116011611162116311641165116611671168116911701171117211731174117511761177117811791180118111821183118411851186118711881189119011911192119311941195119611971198119912001201120212031204120512061207120812091210121112121213121412151216121712181219122012211222122312241225122612271228122912301231123212331234123512361237123812391240124112421243124412451246124712481249125012511252125312541255125612571258125912601261126212631264126512661267126812691270127112721273127412751276127712781279128012811282128312841285128612871288128912901291129212931294129512961297129812991300130113021303130413051306130713081309131013111312131313141315131613171318131913201321132213231324132513261327132813291330133113321333133413351336133713381339134013411342
  1. // SPDX-License-Identifier: GPL-2.0+
  2. //
  3. // Copyright 2012 Freescale Semiconductor, Inc.
  4. #include <dt-bindings/gpio/gpio.h>
  5. #include "imx28-pinfunc.h"
  6. / {
  7. #address-cells = <1>;
  8. #size-cells = <1>;
  9. interrupt-parent = <&icoll>;
  10. /*
  11. * The decompressor and also some bootloaders rely on a
  12. * pre-existing /chosen node to be available to insert the
  13. * command line and merge other ATAGS info.
  14. */
  15. chosen {};
  16. aliases {
  17. ethernet0 = &mac0;
  18. ethernet1 = &mac1;
  19. gpio0 = &gpio0;
  20. gpio1 = &gpio1;
  21. gpio2 = &gpio2;
  22. gpio3 = &gpio3;
  23. gpio4 = &gpio4;
  24. saif0 = &saif0;
  25. saif1 = &saif1;
  26. serial0 = &auart0;
  27. serial1 = &auart1;
  28. serial2 = &auart2;
  29. serial3 = &auart3;
  30. serial4 = &auart4;
  31. spi0 = &ssp1;
  32. spi1 = &ssp2;
  33. usbphy0 = &usbphy0;
  34. usbphy1 = &usbphy1;
  35. };
  36. cpus {
  37. #address-cells = <1>;
  38. #size-cells = <0>;
  39. cpu@0 {
  40. compatible = "arm,arm926ej-s";
  41. device_type = "cpu";
  42. reg = <0>;
  43. };
  44. };
  45. apb@80000000 {
  46. compatible = "simple-bus";
  47. #address-cells = <1>;
  48. #size-cells = <1>;
  49. reg = <0x80000000 0x80000>;
  50. ranges;
  51. apbh@80000000 {
  52. compatible = "simple-bus";
  53. #address-cells = <1>;
  54. #size-cells = <1>;
  55. reg = <0x80000000 0x3c900>;
  56. ranges;
  57. icoll: interrupt-controller@80000000 {
  58. compatible = "fsl,imx28-icoll", "fsl,icoll";
  59. interrupt-controller;
  60. #interrupt-cells = <1>;
  61. reg = <0x80000000 0x2000>;
  62. };
  63. hsadc: hsadc@80002000 {
  64. reg = <0x80002000 0x2000>;
  65. interrupts = <13>;
  66. dmas = <&dma_apbh 12>;
  67. dma-names = "rx";
  68. status = "disabled";
  69. };
  70. dma_apbh: dma-apbh@80004000 {
  71. compatible = "fsl,imx28-dma-apbh";
  72. reg = <0x80004000 0x2000>;
  73. interrupts = <82 83 84 85
  74. 88 88 88 88
  75. 88 88 88 88
  76. 87 86 0 0>;
  77. interrupt-names = "ssp0", "ssp1", "ssp2", "ssp3",
  78. "gpmi0", "gmpi1", "gpmi2", "gmpi3",
  79. "gpmi4", "gmpi5", "gpmi6", "gmpi7",
  80. "hsadc", "lcdif", "empty", "empty";
  81. #dma-cells = <1>;
  82. dma-channels = <16>;
  83. clocks = <&clks 25>;
  84. };
  85. perfmon: perfmon@80006000 {
  86. reg = <0x80006000 0x800>;
  87. interrupts = <27>;
  88. status = "disabled";
  89. };
  90. gpmi: nand-controller@8000c000 {
  91. compatible = "fsl,imx28-gpmi-nand";
  92. #address-cells = <1>;
  93. #size-cells = <1>;
  94. reg = <0x8000c000 0x2000>, <0x8000a000 0x2000>;
  95. reg-names = "gpmi-nand", "bch";
  96. interrupts = <41>;
  97. interrupt-names = "bch";
  98. clocks = <&clks 50>;
  99. clock-names = "gpmi_io";
  100. assigned-clocks = <&clks 13>;
  101. assigned-clock-parents = <&clks 10>;
  102. dmas = <&dma_apbh 4>;
  103. dma-names = "rx-tx";
  104. status = "disabled";
  105. };
  106. ssp0: spi@80010000 {
  107. #address-cells = <1>;
  108. #size-cells = <0>;
  109. reg = <0x80010000 0x2000>;
  110. interrupts = <96>;
  111. clocks = <&clks 46>;
  112. dmas = <&dma_apbh 0>;
  113. dma-names = "rx-tx";
  114. status = "disabled";
  115. };
  116. ssp1: spi@80012000 {
  117. #address-cells = <1>;
  118. #size-cells = <0>;
  119. reg = <0x80012000 0x2000>;
  120. interrupts = <97>;
  121. clocks = <&clks 47>;
  122. dmas = <&dma_apbh 1>;
  123. dma-names = "rx-tx";
  124. status = "disabled";
  125. };
  126. ssp2: spi@80014000 {
  127. #address-cells = <1>;
  128. #size-cells = <0>;
  129. reg = <0x80014000 0x2000>;
  130. interrupts = <98>;
  131. clocks = <&clks 48>;
  132. dmas = <&dma_apbh 2>;
  133. dma-names = "rx-tx";
  134. status = "disabled";
  135. };
  136. ssp3: spi@80016000 {
  137. #address-cells = <1>;
  138. #size-cells = <0>;
  139. reg = <0x80016000 0x2000>;
  140. interrupts = <99>;
  141. clocks = <&clks 49>;
  142. dmas = <&dma_apbh 3>;
  143. dma-names = "rx-tx";
  144. status = "disabled";
  145. };
  146. pinctrl: pinctrl@80018000 {
  147. #address-cells = <1>;
  148. #size-cells = <0>;
  149. compatible = "fsl,imx28-pinctrl", "simple-bus";
  150. reg = <0x80018000 0x2000>;
  151. gpio0: gpio@0 {
  152. compatible = "fsl,imx28-gpio", "fsl,mxs-gpio";
  153. reg = <0>;
  154. interrupts = <127>;
  155. gpio-controller;
  156. #gpio-cells = <2>;
  157. interrupt-controller;
  158. #interrupt-cells = <2>;
  159. };
  160. gpio1: gpio@1 {
  161. compatible = "fsl,imx28-gpio", "fsl,mxs-gpio";
  162. reg = <1>;
  163. interrupts = <126>;
  164. gpio-controller;
  165. #gpio-cells = <2>;
  166. interrupt-controller;
  167. #interrupt-cells = <2>;
  168. };
  169. gpio2: gpio@2 {
  170. compatible = "fsl,imx28-gpio", "fsl,mxs-gpio";
  171. reg = <2>;
  172. interrupts = <125>;
  173. gpio-controller;
  174. #gpio-cells = <2>;
  175. interrupt-controller;
  176. #interrupt-cells = <2>;
  177. };
  178. gpio3: gpio@3 {
  179. compatible = "fsl,imx28-gpio", "fsl,mxs-gpio";
  180. reg = <3>;
  181. interrupts = <124>;
  182. gpio-controller;
  183. #gpio-cells = <2>;
  184. interrupt-controller;
  185. #interrupt-cells = <2>;
  186. };
  187. gpio4: gpio@4 {
  188. compatible = "fsl,imx28-gpio", "fsl,mxs-gpio";
  189. reg = <4>;
  190. interrupts = <123>;
  191. gpio-controller;
  192. #gpio-cells = <2>;
  193. interrupt-controller;
  194. #interrupt-cells = <2>;
  195. };
  196. duart_pins_a: duart@0 {
  197. reg = <0>;
  198. fsl,pinmux-ids = <
  199. MX28_PAD_PWM0__DUART_RX
  200. MX28_PAD_PWM1__DUART_TX
  201. >;
  202. fsl,drive-strength = <MXS_DRIVE_4mA>;
  203. fsl,voltage = <MXS_VOLTAGE_HIGH>;
  204. fsl,pull-up = <MXS_PULL_DISABLE>;
  205. };
  206. duart_pins_b: duart@1 {
  207. reg = <1>;
  208. fsl,pinmux-ids = <
  209. MX28_PAD_AUART0_CTS__DUART_RX
  210. MX28_PAD_AUART0_RTS__DUART_TX
  211. >;
  212. fsl,drive-strength = <MXS_DRIVE_4mA>;
  213. fsl,voltage = <MXS_VOLTAGE_HIGH>;
  214. fsl,pull-up = <MXS_PULL_DISABLE>;
  215. };
  216. duart_4pins_a: duart-4pins@0 {
  217. reg = <0>;
  218. fsl,pinmux-ids = <
  219. MX28_PAD_AUART0_CTS__DUART_RX
  220. MX28_PAD_AUART0_RTS__DUART_TX
  221. MX28_PAD_AUART0_RX__DUART_CTS
  222. MX28_PAD_AUART0_TX__DUART_RTS
  223. >;
  224. fsl,drive-strength = <MXS_DRIVE_4mA>;
  225. fsl,voltage = <MXS_VOLTAGE_HIGH>;
  226. fsl,pull-up = <MXS_PULL_DISABLE>;
  227. };
  228. gpmi_pins_a: gpmi-nand@0 {
  229. reg = <0>;
  230. fsl,pinmux-ids = <
  231. MX28_PAD_GPMI_D00__GPMI_D0
  232. MX28_PAD_GPMI_D01__GPMI_D1
  233. MX28_PAD_GPMI_D02__GPMI_D2
  234. MX28_PAD_GPMI_D03__GPMI_D3
  235. MX28_PAD_GPMI_D04__GPMI_D4
  236. MX28_PAD_GPMI_D05__GPMI_D5
  237. MX28_PAD_GPMI_D06__GPMI_D6
  238. MX28_PAD_GPMI_D07__GPMI_D7
  239. MX28_PAD_GPMI_CE0N__GPMI_CE0N
  240. MX28_PAD_GPMI_RDY0__GPMI_READY0
  241. MX28_PAD_GPMI_RDN__GPMI_RDN
  242. MX28_PAD_GPMI_WRN__GPMI_WRN
  243. MX28_PAD_GPMI_ALE__GPMI_ALE
  244. MX28_PAD_GPMI_CLE__GPMI_CLE
  245. MX28_PAD_GPMI_RESETN__GPMI_RESETN
  246. >;
  247. fsl,drive-strength = <MXS_DRIVE_4mA>;
  248. fsl,voltage = <MXS_VOLTAGE_HIGH>;
  249. fsl,pull-up = <MXS_PULL_DISABLE>;
  250. };
  251. gpmi_status_cfg: gpmi-status-cfg@0 {
  252. reg = <0>;
  253. fsl,pinmux-ids = <
  254. MX28_PAD_GPMI_RDN__GPMI_RDN
  255. MX28_PAD_GPMI_WRN__GPMI_WRN
  256. MX28_PAD_GPMI_RESETN__GPMI_RESETN
  257. >;
  258. fsl,drive-strength = <MXS_DRIVE_12mA>;
  259. };
  260. auart0_pins_a: auart0@0 {
  261. reg = <0>;
  262. fsl,pinmux-ids = <
  263. MX28_PAD_AUART0_RX__AUART0_RX
  264. MX28_PAD_AUART0_TX__AUART0_TX
  265. MX28_PAD_AUART0_CTS__AUART0_CTS
  266. MX28_PAD_AUART0_RTS__AUART0_RTS
  267. >;
  268. fsl,drive-strength = <MXS_DRIVE_4mA>;
  269. fsl,voltage = <MXS_VOLTAGE_HIGH>;
  270. fsl,pull-up = <MXS_PULL_DISABLE>;
  271. };
  272. auart0_2pins_a: auart0-2pins@0 {
  273. reg = <0>;
  274. fsl,pinmux-ids = <
  275. MX28_PAD_AUART0_RX__AUART0_RX
  276. MX28_PAD_AUART0_TX__AUART0_TX
  277. >;
  278. fsl,drive-strength = <MXS_DRIVE_4mA>;
  279. fsl,voltage = <MXS_VOLTAGE_HIGH>;
  280. fsl,pull-up = <MXS_PULL_DISABLE>;
  281. };
  282. auart1_pins_a: auart1@0 {
  283. reg = <0>;
  284. fsl,pinmux-ids = <
  285. MX28_PAD_AUART1_RX__AUART1_RX
  286. MX28_PAD_AUART1_TX__AUART1_TX
  287. MX28_PAD_AUART1_CTS__AUART1_CTS
  288. MX28_PAD_AUART1_RTS__AUART1_RTS
  289. >;
  290. fsl,drive-strength = <MXS_DRIVE_4mA>;
  291. fsl,voltage = <MXS_VOLTAGE_HIGH>;
  292. fsl,pull-up = <MXS_PULL_DISABLE>;
  293. };
  294. auart1_2pins_a: auart1-2pins@0 {
  295. reg = <0>;
  296. fsl,pinmux-ids = <
  297. MX28_PAD_AUART1_RX__AUART1_RX
  298. MX28_PAD_AUART1_TX__AUART1_TX
  299. >;
  300. fsl,drive-strength = <MXS_DRIVE_4mA>;
  301. fsl,voltage = <MXS_VOLTAGE_HIGH>;
  302. fsl,pull-up = <MXS_PULL_DISABLE>;
  303. };
  304. auart2_2pins_a: auart2-2pins@0 {
  305. reg = <0>;
  306. fsl,pinmux-ids = <
  307. MX28_PAD_SSP2_SCK__AUART2_RX
  308. MX28_PAD_SSP2_MOSI__AUART2_TX
  309. >;
  310. fsl,drive-strength = <MXS_DRIVE_4mA>;
  311. fsl,voltage = <MXS_VOLTAGE_HIGH>;
  312. fsl,pull-up = <MXS_PULL_DISABLE>;
  313. };
  314. auart2_2pins_b: auart2-2pins@1 {
  315. reg = <1>;
  316. fsl,pinmux-ids = <
  317. MX28_PAD_AUART2_RX__AUART2_RX
  318. MX28_PAD_AUART2_TX__AUART2_TX
  319. >;
  320. fsl,drive-strength = <MXS_DRIVE_4mA>;
  321. fsl,voltage = <MXS_VOLTAGE_HIGH>;
  322. fsl,pull-up = <MXS_PULL_DISABLE>;
  323. };
  324. auart2_pins_a: auart2-pins@0 {
  325. reg = <0>;
  326. fsl,pinmux-ids = <
  327. MX28_PAD_AUART2_RX__AUART2_RX
  328. MX28_PAD_AUART2_TX__AUART2_TX
  329. MX28_PAD_AUART2_CTS__AUART2_CTS
  330. MX28_PAD_AUART2_RTS__AUART2_RTS
  331. >;
  332. fsl,drive-strength = <MXS_DRIVE_4mA>;
  333. fsl,voltage = <MXS_VOLTAGE_HIGH>;
  334. fsl,pull-up = <MXS_PULL_DISABLE>;
  335. };
  336. auart3_pins_a: auart3@0 {
  337. reg = <0>;
  338. fsl,pinmux-ids = <
  339. MX28_PAD_AUART3_RX__AUART3_RX
  340. MX28_PAD_AUART3_TX__AUART3_TX
  341. MX28_PAD_AUART3_CTS__AUART3_CTS
  342. MX28_PAD_AUART3_RTS__AUART3_RTS
  343. >;
  344. fsl,drive-strength = <MXS_DRIVE_4mA>;
  345. fsl,voltage = <MXS_VOLTAGE_HIGH>;
  346. fsl,pull-up = <MXS_PULL_DISABLE>;
  347. };
  348. auart3_2pins_a: auart3-2pins@0 {
  349. reg = <0>;
  350. fsl,pinmux-ids = <
  351. MX28_PAD_SSP2_MISO__AUART3_RX
  352. MX28_PAD_SSP2_SS0__AUART3_TX
  353. >;
  354. fsl,drive-strength = <MXS_DRIVE_4mA>;
  355. fsl,voltage = <MXS_VOLTAGE_HIGH>;
  356. fsl,pull-up = <MXS_PULL_DISABLE>;
  357. };
  358. auart3_2pins_b: auart3-2pins@1 {
  359. reg = <1>;
  360. fsl,pinmux-ids = <
  361. MX28_PAD_AUART3_RX__AUART3_RX
  362. MX28_PAD_AUART3_TX__AUART3_TX
  363. >;
  364. fsl,drive-strength = <MXS_DRIVE_4mA>;
  365. fsl,voltage = <MXS_VOLTAGE_HIGH>;
  366. fsl,pull-up = <MXS_PULL_DISABLE>;
  367. };
  368. auart4_2pins_a: auart4@0 {
  369. reg = <0>;
  370. fsl,pinmux-ids = <
  371. MX28_PAD_SSP3_SCK__AUART4_TX
  372. MX28_PAD_SSP3_MOSI__AUART4_RX
  373. >;
  374. fsl,drive-strength = <MXS_DRIVE_4mA>;
  375. fsl,voltage = <MXS_VOLTAGE_HIGH>;
  376. fsl,pull-up = <MXS_PULL_DISABLE>;
  377. };
  378. auart4_2pins_b: auart4@1 {
  379. reg = <1>;
  380. fsl,pinmux-ids = <
  381. MX28_PAD_AUART0_CTS__AUART4_RX
  382. MX28_PAD_AUART0_RTS__AUART4_TX
  383. >;
  384. fsl,drive-strength = <MXS_DRIVE_4mA>;
  385. fsl,voltage = <MXS_VOLTAGE_HIGH>;
  386. fsl,pull-up = <MXS_PULL_DISABLE>;
  387. };
  388. mac0_pins_a: mac0@0 {
  389. reg = <0>;
  390. fsl,pinmux-ids = <
  391. MX28_PAD_ENET0_MDC__ENET0_MDC
  392. MX28_PAD_ENET0_MDIO__ENET0_MDIO
  393. MX28_PAD_ENET0_RX_EN__ENET0_RX_EN
  394. MX28_PAD_ENET0_RXD0__ENET0_RXD0
  395. MX28_PAD_ENET0_RXD1__ENET0_RXD1
  396. MX28_PAD_ENET0_TX_EN__ENET0_TX_EN
  397. MX28_PAD_ENET0_TXD0__ENET0_TXD0
  398. MX28_PAD_ENET0_TXD1__ENET0_TXD1
  399. MX28_PAD_ENET_CLK__CLKCTRL_ENET
  400. >;
  401. fsl,drive-strength = <MXS_DRIVE_8mA>;
  402. fsl,voltage = <MXS_VOLTAGE_HIGH>;
  403. fsl,pull-up = <MXS_PULL_ENABLE>;
  404. };
  405. mac0_pins_b: mac0@1 {
  406. reg = <1>;
  407. fsl,pinmux-ids = <
  408. MX28_PAD_ENET0_MDC__ENET0_MDC
  409. MX28_PAD_ENET0_MDIO__ENET0_MDIO
  410. MX28_PAD_ENET0_RX_EN__ENET0_RX_EN
  411. MX28_PAD_ENET0_RXD0__ENET0_RXD0
  412. MX28_PAD_ENET0_RXD1__ENET0_RXD1
  413. MX28_PAD_ENET0_RXD2__ENET0_RXD2
  414. MX28_PAD_ENET0_RXD3__ENET0_RXD3
  415. MX28_PAD_ENET0_TX_EN__ENET0_TX_EN
  416. MX28_PAD_ENET0_TXD0__ENET0_TXD0
  417. MX28_PAD_ENET0_TXD1__ENET0_TXD1
  418. MX28_PAD_ENET0_TXD2__ENET0_TXD2
  419. MX28_PAD_ENET0_TXD3__ENET0_TXD3
  420. MX28_PAD_ENET_CLK__CLKCTRL_ENET
  421. MX28_PAD_ENET0_COL__ENET0_COL
  422. MX28_PAD_ENET0_CRS__ENET0_CRS
  423. MX28_PAD_ENET0_TX_CLK__ENET0_TX_CLK
  424. MX28_PAD_ENET0_RX_CLK__ENET0_RX_CLK
  425. >;
  426. fsl,drive-strength = <MXS_DRIVE_8mA>;
  427. fsl,voltage = <MXS_VOLTAGE_HIGH>;
  428. fsl,pull-up = <MXS_PULL_ENABLE>;
  429. };
  430. mac1_pins_a: mac1@0 {
  431. reg = <0>;
  432. fsl,pinmux-ids = <
  433. MX28_PAD_ENET0_CRS__ENET1_RX_EN
  434. MX28_PAD_ENET0_RXD2__ENET1_RXD0
  435. MX28_PAD_ENET0_RXD3__ENET1_RXD1
  436. MX28_PAD_ENET0_COL__ENET1_TX_EN
  437. MX28_PAD_ENET0_TXD2__ENET1_TXD0
  438. MX28_PAD_ENET0_TXD3__ENET1_TXD1
  439. >;
  440. fsl,drive-strength = <MXS_DRIVE_8mA>;
  441. fsl,voltage = <MXS_VOLTAGE_HIGH>;
  442. fsl,pull-up = <MXS_PULL_ENABLE>;
  443. };
  444. mmc0_8bit_pins_a: mmc0-8bit@0 {
  445. reg = <0>;
  446. fsl,pinmux-ids = <
  447. MX28_PAD_SSP0_DATA0__SSP0_D0
  448. MX28_PAD_SSP0_DATA1__SSP0_D1
  449. MX28_PAD_SSP0_DATA2__SSP0_D2
  450. MX28_PAD_SSP0_DATA3__SSP0_D3
  451. MX28_PAD_SSP0_DATA4__SSP0_D4
  452. MX28_PAD_SSP0_DATA5__SSP0_D5
  453. MX28_PAD_SSP0_DATA6__SSP0_D6
  454. MX28_PAD_SSP0_DATA7__SSP0_D7
  455. MX28_PAD_SSP0_CMD__SSP0_CMD
  456. MX28_PAD_SSP0_DETECT__SSP0_CARD_DETECT
  457. MX28_PAD_SSP0_SCK__SSP0_SCK
  458. >;
  459. fsl,drive-strength = <MXS_DRIVE_8mA>;
  460. fsl,voltage = <MXS_VOLTAGE_HIGH>;
  461. fsl,pull-up = <MXS_PULL_ENABLE>;
  462. };
  463. mmc0_4bit_pins_a: mmc0-4bit@0 {
  464. reg = <0>;
  465. fsl,pinmux-ids = <
  466. MX28_PAD_SSP0_DATA0__SSP0_D0
  467. MX28_PAD_SSP0_DATA1__SSP0_D1
  468. MX28_PAD_SSP0_DATA2__SSP0_D2
  469. MX28_PAD_SSP0_DATA3__SSP0_D3
  470. MX28_PAD_SSP0_CMD__SSP0_CMD
  471. MX28_PAD_SSP0_DETECT__SSP0_CARD_DETECT
  472. MX28_PAD_SSP0_SCK__SSP0_SCK
  473. >;
  474. fsl,drive-strength = <MXS_DRIVE_8mA>;
  475. fsl,voltage = <MXS_VOLTAGE_HIGH>;
  476. fsl,pull-up = <MXS_PULL_ENABLE>;
  477. };
  478. mmc0_cd_cfg: mmc0-cd-cfg@0 {
  479. reg = <0>;
  480. fsl,pinmux-ids = <
  481. MX28_PAD_SSP0_DETECT__SSP0_CARD_DETECT
  482. >;
  483. fsl,pull-up = <MXS_PULL_DISABLE>;
  484. };
  485. mmc0_sck_cfg: mmc0-sck-cfg@0 {
  486. reg = <0>;
  487. fsl,pinmux-ids = <
  488. MX28_PAD_SSP0_SCK__SSP0_SCK
  489. >;
  490. fsl,drive-strength = <MXS_DRIVE_12mA>;
  491. fsl,pull-up = <MXS_PULL_DISABLE>;
  492. };
  493. mmc1_4bit_pins_a: mmc1-4bit@0 {
  494. reg = <0>;
  495. fsl,pinmux-ids = <
  496. MX28_PAD_GPMI_D00__SSP1_D0
  497. MX28_PAD_GPMI_D01__SSP1_D1
  498. MX28_PAD_GPMI_D02__SSP1_D2
  499. MX28_PAD_GPMI_D03__SSP1_D3
  500. MX28_PAD_GPMI_RDY1__SSP1_CMD
  501. MX28_PAD_GPMI_RDY0__SSP1_CARD_DETECT
  502. MX28_PAD_GPMI_WRN__SSP1_SCK
  503. >;
  504. fsl,drive-strength = <MXS_DRIVE_8mA>;
  505. fsl,voltage = <MXS_VOLTAGE_HIGH>;
  506. fsl,pull-up = <MXS_PULL_ENABLE>;
  507. };
  508. mmc1_cd_cfg: mmc1-cd-cfg@0 {
  509. reg = <0>;
  510. fsl,pinmux-ids = <
  511. MX28_PAD_GPMI_RDY0__SSP1_CARD_DETECT
  512. >;
  513. fsl,pull-up = <MXS_PULL_DISABLE>;
  514. };
  515. mmc1_sck_cfg: mmc1-sck-cfg@0 {
  516. reg = <0>;
  517. fsl,pinmux-ids = <
  518. MX28_PAD_GPMI_WRN__SSP1_SCK
  519. >;
  520. fsl,drive-strength = <MXS_DRIVE_12mA>;
  521. fsl,pull-up = <MXS_PULL_DISABLE>;
  522. };
  523. mmc2_4bit_pins_a: mmc2-4bit@0 {
  524. reg = <0>;
  525. fsl,pinmux-ids = <
  526. MX28_PAD_SSP0_DATA4__SSP2_D0
  527. MX28_PAD_SSP1_SCK__SSP2_D1
  528. MX28_PAD_SSP1_CMD__SSP2_D2
  529. MX28_PAD_SSP0_DATA5__SSP2_D3
  530. MX28_PAD_SSP0_DATA6__SSP2_CMD
  531. MX28_PAD_AUART1_RX__SSP2_CARD_DETECT
  532. MX28_PAD_SSP0_DATA7__SSP2_SCK
  533. >;
  534. fsl,drive-strength = <MXS_DRIVE_8mA>;
  535. fsl,voltage = <MXS_VOLTAGE_HIGH>;
  536. fsl,pull-up = <MXS_PULL_ENABLE>;
  537. };
  538. mmc2_4bit_pins_b: mmc2-4bit@1 {
  539. reg = <1>;
  540. fsl,pinmux-ids = <
  541. MX28_PAD_SSP2_SCK__SSP2_SCK
  542. MX28_PAD_SSP2_MOSI__SSP2_CMD
  543. MX28_PAD_SSP2_MISO__SSP2_D0
  544. MX28_PAD_SSP2_SS0__SSP2_D3
  545. MX28_PAD_SSP2_SS1__SSP2_D1
  546. MX28_PAD_SSP2_SS2__SSP2_D2
  547. MX28_PAD_AUART1_RX__SSP2_CARD_DETECT
  548. >;
  549. fsl,drive-strength = <MXS_DRIVE_8mA>;
  550. fsl,voltage = <MXS_VOLTAGE_HIGH>;
  551. fsl,pull-up = <MXS_PULL_ENABLE>;
  552. };
  553. mmc2_cd_cfg: mmc2-cd-cfg@0 {
  554. reg = <0>;
  555. fsl,pinmux-ids = <
  556. MX28_PAD_AUART1_RX__SSP2_CARD_DETECT
  557. >;
  558. fsl,pull-up = <MXS_PULL_DISABLE>;
  559. };
  560. mmc2_sck_cfg_a: mmc2-sck-cfg@0 {
  561. reg = <0>;
  562. fsl,pinmux-ids = <
  563. MX28_PAD_SSP0_DATA7__SSP2_SCK
  564. >;
  565. fsl,drive-strength = <MXS_DRIVE_12mA>;
  566. fsl,pull-up = <MXS_PULL_DISABLE>;
  567. };
  568. mmc2_sck_cfg_b: mmc2-sck-cfg@1 {
  569. reg = <1>;
  570. fsl,pinmux-ids = <
  571. MX28_PAD_SSP2_SCK__SSP2_SCK
  572. >;
  573. fsl,drive-strength = <MXS_DRIVE_12mA>;
  574. fsl,pull-up = <MXS_PULL_DISABLE>;
  575. };
  576. i2c0_pins_a: i2c0@0 {
  577. reg = <0>;
  578. fsl,pinmux-ids = <
  579. MX28_PAD_I2C0_SCL__I2C0_SCL
  580. MX28_PAD_I2C0_SDA__I2C0_SDA
  581. >;
  582. fsl,drive-strength = <MXS_DRIVE_8mA>;
  583. fsl,voltage = <MXS_VOLTAGE_HIGH>;
  584. fsl,pull-up = <MXS_PULL_ENABLE>;
  585. };
  586. i2c0_pins_b: i2c0@1 {
  587. reg = <1>;
  588. fsl,pinmux-ids = <
  589. MX28_PAD_AUART0_RX__I2C0_SCL
  590. MX28_PAD_AUART0_TX__I2C0_SDA
  591. >;
  592. fsl,drive-strength = <MXS_DRIVE_8mA>;
  593. fsl,voltage = <MXS_VOLTAGE_HIGH>;
  594. fsl,pull-up = <MXS_PULL_ENABLE>;
  595. };
  596. i2c1_pins_a: i2c1@0 {
  597. reg = <0>;
  598. fsl,pinmux-ids = <
  599. MX28_PAD_PWM0__I2C1_SCL
  600. MX28_PAD_PWM1__I2C1_SDA
  601. >;
  602. fsl,drive-strength = <MXS_DRIVE_8mA>;
  603. fsl,voltage = <MXS_VOLTAGE_HIGH>;
  604. fsl,pull-up = <MXS_PULL_ENABLE>;
  605. };
  606. i2c1_pins_b: i2c1@1 {
  607. reg = <1>;
  608. fsl,pinmux-ids = <
  609. MX28_PAD_AUART2_CTS__I2C1_SCL
  610. MX28_PAD_AUART2_RTS__I2C1_SDA
  611. >;
  612. fsl,drive-strength = <MXS_DRIVE_8mA>;
  613. fsl,voltage = <MXS_VOLTAGE_HIGH>;
  614. fsl,pull-up = <MXS_PULL_ENABLE>;
  615. };
  616. saif0_pins_a: saif0@0 {
  617. reg = <0>;
  618. fsl,pinmux-ids = <
  619. MX28_PAD_SAIF0_MCLK__SAIF0_MCLK
  620. MX28_PAD_SAIF0_LRCLK__SAIF0_LRCLK
  621. MX28_PAD_SAIF0_BITCLK__SAIF0_BITCLK
  622. MX28_PAD_SAIF0_SDATA0__SAIF0_SDATA0
  623. >;
  624. fsl,drive-strength = <MXS_DRIVE_12mA>;
  625. fsl,voltage = <MXS_VOLTAGE_HIGH>;
  626. fsl,pull-up = <MXS_PULL_ENABLE>;
  627. };
  628. saif0_pins_b: saif0@1 {
  629. reg = <1>;
  630. fsl,pinmux-ids = <
  631. MX28_PAD_SAIF0_LRCLK__SAIF0_LRCLK
  632. MX28_PAD_SAIF0_BITCLK__SAIF0_BITCLK
  633. MX28_PAD_SAIF0_SDATA0__SAIF0_SDATA0
  634. >;
  635. fsl,drive-strength = <MXS_DRIVE_12mA>;
  636. fsl,voltage = <MXS_VOLTAGE_HIGH>;
  637. fsl,pull-up = <MXS_PULL_ENABLE>;
  638. };
  639. saif1_pins_a: saif1@0 {
  640. reg = <0>;
  641. fsl,pinmux-ids = <
  642. MX28_PAD_SAIF1_SDATA0__SAIF1_SDATA0
  643. >;
  644. fsl,drive-strength = <MXS_DRIVE_12mA>;
  645. fsl,voltage = <MXS_VOLTAGE_HIGH>;
  646. fsl,pull-up = <MXS_PULL_ENABLE>;
  647. };
  648. pwm0_pins_a: pwm0@0 {
  649. reg = <0>;
  650. fsl,pinmux-ids = <
  651. MX28_PAD_PWM0__PWM_0
  652. >;
  653. fsl,drive-strength = <MXS_DRIVE_4mA>;
  654. fsl,voltage = <MXS_VOLTAGE_HIGH>;
  655. fsl,pull-up = <MXS_PULL_DISABLE>;
  656. };
  657. pwm2_pins_a: pwm2@0 {
  658. reg = <0>;
  659. fsl,pinmux-ids = <
  660. MX28_PAD_PWM2__PWM_2
  661. >;
  662. fsl,drive-strength = <MXS_DRIVE_4mA>;
  663. fsl,voltage = <MXS_VOLTAGE_HIGH>;
  664. fsl,pull-up = <MXS_PULL_DISABLE>;
  665. };
  666. pwm3_pins_a: pwm3@0 {
  667. reg = <0>;
  668. fsl,pinmux-ids = <
  669. MX28_PAD_PWM3__PWM_3
  670. >;
  671. fsl,drive-strength = <MXS_DRIVE_4mA>;
  672. fsl,voltage = <MXS_VOLTAGE_HIGH>;
  673. fsl,pull-up = <MXS_PULL_DISABLE>;
  674. };
  675. pwm3_pins_b: pwm3@1 {
  676. reg = <1>;
  677. fsl,pinmux-ids = <
  678. MX28_PAD_SAIF0_MCLK__PWM_3
  679. >;
  680. fsl,drive-strength = <MXS_DRIVE_4mA>;
  681. fsl,voltage = <MXS_VOLTAGE_HIGH>;
  682. fsl,pull-up = <MXS_PULL_DISABLE>;
  683. };
  684. pwm4_pins_a: pwm4@0 {
  685. reg = <0>;
  686. fsl,pinmux-ids = <
  687. MX28_PAD_PWM4__PWM_4
  688. >;
  689. fsl,drive-strength = <MXS_DRIVE_4mA>;
  690. fsl,voltage = <MXS_VOLTAGE_HIGH>;
  691. fsl,pull-up = <MXS_PULL_DISABLE>;
  692. };
  693. lcdif_24bit_pins_a: lcdif-24bit@0 {
  694. reg = <0>;
  695. fsl,pinmux-ids = <
  696. MX28_PAD_LCD_D00__LCD_D0
  697. MX28_PAD_LCD_D01__LCD_D1
  698. MX28_PAD_LCD_D02__LCD_D2
  699. MX28_PAD_LCD_D03__LCD_D3
  700. MX28_PAD_LCD_D04__LCD_D4
  701. MX28_PAD_LCD_D05__LCD_D5
  702. MX28_PAD_LCD_D06__LCD_D6
  703. MX28_PAD_LCD_D07__LCD_D7
  704. MX28_PAD_LCD_D08__LCD_D8
  705. MX28_PAD_LCD_D09__LCD_D9
  706. MX28_PAD_LCD_D10__LCD_D10
  707. MX28_PAD_LCD_D11__LCD_D11
  708. MX28_PAD_LCD_D12__LCD_D12
  709. MX28_PAD_LCD_D13__LCD_D13
  710. MX28_PAD_LCD_D14__LCD_D14
  711. MX28_PAD_LCD_D15__LCD_D15
  712. MX28_PAD_LCD_D16__LCD_D16
  713. MX28_PAD_LCD_D17__LCD_D17
  714. MX28_PAD_LCD_D18__LCD_D18
  715. MX28_PAD_LCD_D19__LCD_D19
  716. MX28_PAD_LCD_D20__LCD_D20
  717. MX28_PAD_LCD_D21__LCD_D21
  718. MX28_PAD_LCD_D22__LCD_D22
  719. MX28_PAD_LCD_D23__LCD_D23
  720. >;
  721. fsl,drive-strength = <MXS_DRIVE_4mA>;
  722. fsl,voltage = <MXS_VOLTAGE_HIGH>;
  723. fsl,pull-up = <MXS_PULL_DISABLE>;
  724. };
  725. lcdif_18bit_pins_a: lcdif-18bit@0 {
  726. reg = <0>;
  727. fsl,pinmux-ids = <
  728. MX28_PAD_LCD_D00__LCD_D0
  729. MX28_PAD_LCD_D01__LCD_D1
  730. MX28_PAD_LCD_D02__LCD_D2
  731. MX28_PAD_LCD_D03__LCD_D3
  732. MX28_PAD_LCD_D04__LCD_D4
  733. MX28_PAD_LCD_D05__LCD_D5
  734. MX28_PAD_LCD_D06__LCD_D6
  735. MX28_PAD_LCD_D07__LCD_D7
  736. MX28_PAD_LCD_D08__LCD_D8
  737. MX28_PAD_LCD_D09__LCD_D9
  738. MX28_PAD_LCD_D10__LCD_D10
  739. MX28_PAD_LCD_D11__LCD_D11
  740. MX28_PAD_LCD_D12__LCD_D12
  741. MX28_PAD_LCD_D13__LCD_D13
  742. MX28_PAD_LCD_D14__LCD_D14
  743. MX28_PAD_LCD_D15__LCD_D15
  744. MX28_PAD_LCD_D16__LCD_D16
  745. MX28_PAD_LCD_D17__LCD_D17
  746. >;
  747. fsl,drive-strength = <MXS_DRIVE_4mA>;
  748. fsl,voltage = <MXS_VOLTAGE_HIGH>;
  749. fsl,pull-up = <MXS_PULL_DISABLE>;
  750. };
  751. lcdif_16bit_pins_a: lcdif-16bit@0 {
  752. reg = <0>;
  753. fsl,pinmux-ids = <
  754. MX28_PAD_LCD_D00__LCD_D0
  755. MX28_PAD_LCD_D01__LCD_D1
  756. MX28_PAD_LCD_D02__LCD_D2
  757. MX28_PAD_LCD_D03__LCD_D3
  758. MX28_PAD_LCD_D04__LCD_D4
  759. MX28_PAD_LCD_D05__LCD_D5
  760. MX28_PAD_LCD_D06__LCD_D6
  761. MX28_PAD_LCD_D07__LCD_D7
  762. MX28_PAD_LCD_D08__LCD_D8
  763. MX28_PAD_LCD_D09__LCD_D9
  764. MX28_PAD_LCD_D10__LCD_D10
  765. MX28_PAD_LCD_D11__LCD_D11
  766. MX28_PAD_LCD_D12__LCD_D12
  767. MX28_PAD_LCD_D13__LCD_D13
  768. MX28_PAD_LCD_D14__LCD_D14
  769. MX28_PAD_LCD_D15__LCD_D15
  770. >;
  771. fsl,drive-strength = <MXS_DRIVE_4mA>;
  772. fsl,voltage = <MXS_VOLTAGE_HIGH>;
  773. fsl,pull-up = <MXS_PULL_DISABLE>;
  774. };
  775. lcdif_sync_pins_a: lcdif-sync@0 {
  776. reg = <0>;
  777. fsl,pinmux-ids = <
  778. MX28_PAD_LCD_RS__LCD_DOTCLK
  779. MX28_PAD_LCD_CS__LCD_ENABLE
  780. MX28_PAD_LCD_RD_E__LCD_VSYNC
  781. MX28_PAD_LCD_WR_RWN__LCD_HSYNC
  782. >;
  783. fsl,drive-strength = <MXS_DRIVE_4mA>;
  784. fsl,voltage = <MXS_VOLTAGE_HIGH>;
  785. fsl,pull-up = <MXS_PULL_DISABLE>;
  786. };
  787. can0_pins_a: can0@0 {
  788. reg = <0>;
  789. fsl,pinmux-ids = <
  790. MX28_PAD_GPMI_RDY2__CAN0_TX
  791. MX28_PAD_GPMI_RDY3__CAN0_RX
  792. >;
  793. fsl,drive-strength = <MXS_DRIVE_4mA>;
  794. fsl,voltage = <MXS_VOLTAGE_HIGH>;
  795. fsl,pull-up = <MXS_PULL_DISABLE>;
  796. };
  797. can1_pins_a: can1@0 {
  798. reg = <0>;
  799. fsl,pinmux-ids = <
  800. MX28_PAD_GPMI_CE2N__CAN1_TX
  801. MX28_PAD_GPMI_CE3N__CAN1_RX
  802. >;
  803. fsl,drive-strength = <MXS_DRIVE_4mA>;
  804. fsl,voltage = <MXS_VOLTAGE_HIGH>;
  805. fsl,pull-up = <MXS_PULL_DISABLE>;
  806. };
  807. spi2_pins_a: spi2@0 {
  808. reg = <0>;
  809. fsl,pinmux-ids = <
  810. MX28_PAD_SSP2_SCK__SSP2_SCK
  811. MX28_PAD_SSP2_MOSI__SSP2_CMD
  812. MX28_PAD_SSP2_MISO__SSP2_D0
  813. MX28_PAD_SSP2_SS0__SSP2_D3
  814. >;
  815. fsl,drive-strength = <MXS_DRIVE_8mA>;
  816. fsl,voltage = <MXS_VOLTAGE_HIGH>;
  817. fsl,pull-up = <MXS_PULL_ENABLE>;
  818. };
  819. spi3_pins_a: spi3@0 {
  820. reg = <0>;
  821. fsl,pinmux-ids = <
  822. MX28_PAD_AUART2_RX__SSP3_D4
  823. MX28_PAD_AUART2_TX__SSP3_D5
  824. MX28_PAD_SSP3_SCK__SSP3_SCK
  825. MX28_PAD_SSP3_MOSI__SSP3_CMD
  826. MX28_PAD_SSP3_MISO__SSP3_D0
  827. MX28_PAD_SSP3_SS0__SSP3_D3
  828. >;
  829. fsl,drive-strength = <MXS_DRIVE_8mA>;
  830. fsl,voltage = <MXS_VOLTAGE_HIGH>;
  831. fsl,pull-up = <MXS_PULL_DISABLE>;
  832. };
  833. spi3_pins_b: spi3@1 {
  834. reg = <1>;
  835. fsl,pinmux-ids = <
  836. MX28_PAD_SSP3_SCK__SSP3_SCK
  837. MX28_PAD_SSP3_MOSI__SSP3_CMD
  838. MX28_PAD_SSP3_MISO__SSP3_D0
  839. MX28_PAD_SSP3_SS0__SSP3_D3
  840. >;
  841. fsl,drive-strength = <MXS_DRIVE_8mA>;
  842. fsl,voltage = <MXS_VOLTAGE_HIGH>;
  843. fsl,pull-up = <MXS_PULL_ENABLE>;
  844. };
  845. usb0_pins_a: usb0@0 {
  846. reg = <0>;
  847. fsl,pinmux-ids = <
  848. MX28_PAD_SSP2_SS2__USB0_OVERCURRENT
  849. >;
  850. fsl,drive-strength = <MXS_DRIVE_12mA>;
  851. fsl,voltage = <MXS_VOLTAGE_HIGH>;
  852. fsl,pull-up = <MXS_PULL_DISABLE>;
  853. };
  854. usb0_pins_b: usb0@1 {
  855. reg = <1>;
  856. fsl,pinmux-ids = <
  857. MX28_PAD_AUART1_CTS__USB0_OVERCURRENT
  858. >;
  859. fsl,drive-strength = <MXS_DRIVE_12mA>;
  860. fsl,voltage = <MXS_VOLTAGE_HIGH>;
  861. fsl,pull-up = <MXS_PULL_DISABLE>;
  862. };
  863. usb1_pins_a: usb1@0 {
  864. reg = <0>;
  865. fsl,pinmux-ids = <
  866. MX28_PAD_SSP2_SS1__USB1_OVERCURRENT
  867. >;
  868. fsl,drive-strength = <MXS_DRIVE_12mA>;
  869. fsl,voltage = <MXS_VOLTAGE_HIGH>;
  870. fsl,pull-up = <MXS_PULL_DISABLE>;
  871. };
  872. usb1_pins_b: usb1@1 {
  873. reg = <1>;
  874. fsl,pinmux-ids = <
  875. MX28_PAD_PWM2__USB1_OVERCURRENT
  876. >;
  877. fsl,drive-strength = <MXS_DRIVE_12mA>;
  878. fsl,voltage = <MXS_VOLTAGE_HIGH>;
  879. fsl,pull-up = <MXS_PULL_DISABLE>;
  880. };
  881. usb0_id_pins_a: usb0id@0 {
  882. reg = <0>;
  883. fsl,pinmux-ids = <
  884. MX28_PAD_AUART1_RTS__USB0_ID
  885. >;
  886. fsl,drive-strength = <MXS_DRIVE_12mA>;
  887. fsl,voltage = <MXS_VOLTAGE_HIGH>;
  888. fsl,pull-up = <MXS_PULL_ENABLE>;
  889. };
  890. usb0_id_pins_b: usb0id1@0 {
  891. reg = <0>;
  892. fsl,pinmux-ids = <
  893. MX28_PAD_PWM2__USB0_ID
  894. >;
  895. fsl,drive-strength = <MXS_DRIVE_12mA>;
  896. fsl,voltage = <MXS_VOLTAGE_HIGH>;
  897. fsl,pull-up = <MXS_PULL_ENABLE>;
  898. };
  899. };
  900. digctl: digctl@8001c000 {
  901. compatible = "fsl,imx28-digctl", "fsl,imx23-digctl";
  902. reg = <0x8001c000 0x2000>;
  903. interrupts = <89>;
  904. status = "disabled";
  905. };
  906. etm: etm@80022000 {
  907. reg = <0x80022000 0x2000>;
  908. status = "disabled";
  909. };
  910. dma_apbx: dma-apbx@80024000 {
  911. compatible = "fsl,imx28-dma-apbx";
  912. reg = <0x80024000 0x2000>;
  913. interrupts = <78 79 66 0
  914. 80 81 68 69
  915. 70 71 72 73
  916. 74 75 76 77>;
  917. interrupt-names = "auart4-rx", "auart4-tx", "spdif-tx", "empty",
  918. "saif0", "saif1", "i2c0", "i2c1",
  919. "auart0-rx", "auart0-tx", "auart1-rx", "auart1-tx",
  920. "auart2-rx", "auart2-tx", "auart3-rx", "auart3-tx";
  921. #dma-cells = <1>;
  922. dma-channels = <16>;
  923. clocks = <&clks 26>;
  924. };
  925. dcp: crypto@80028000 {
  926. compatible = "fsl,imx28-dcp", "fsl,imx23-dcp";
  927. reg = <0x80028000 0x2000>;
  928. interrupts = <52 53 54>;
  929. status = "okay";
  930. };
  931. pxp: pxp@8002a000 {
  932. reg = <0x8002a000 0x2000>;
  933. interrupts = <39>;
  934. status = "disabled";
  935. };
  936. ocotp: efuse@8002c000 {
  937. compatible = "fsl,imx28-ocotp", "fsl,ocotp";
  938. #address-cells = <1>;
  939. #size-cells = <1>;
  940. reg = <0x8002c000 0x2000>;
  941. clocks = <&clks 25>;
  942. };
  943. axi-ahb@8002e000 {
  944. reg = <0x8002e000 0x2000>;
  945. status = "disabled";
  946. };
  947. lcdif: lcdif@80030000 {
  948. compatible = "fsl,imx28-lcdif";
  949. reg = <0x80030000 0x2000>;
  950. interrupts = <38>;
  951. clocks = <&clks 55>;
  952. dmas = <&dma_apbh 13>;
  953. dma-names = "rx";
  954. status = "disabled";
  955. };
  956. can0: can@80032000 {
  957. compatible = "fsl,imx28-flexcan";
  958. reg = <0x80032000 0x2000>;
  959. interrupts = <8>;
  960. clocks = <&clks 58>, <&clks 58>;
  961. clock-names = "ipg", "per";
  962. status = "disabled";
  963. };
  964. can1: can@80034000 {
  965. compatible = "fsl,imx28-flexcan";
  966. reg = <0x80034000 0x2000>;
  967. interrupts = <9>;
  968. clocks = <&clks 59>, <&clks 59>;
  969. clock-names = "ipg", "per";
  970. status = "disabled";
  971. };
  972. simdbg: simdbg@8003c000 {
  973. reg = <0x8003c000 0x200>;
  974. status = "disabled";
  975. };
  976. simgpmisel: simgpmisel@8003c200 {
  977. reg = <0x8003c200 0x100>;
  978. status = "disabled";
  979. };
  980. simsspsel: simsspsel@8003c300 {
  981. reg = <0x8003c300 0x100>;
  982. status = "disabled";
  983. };
  984. simmemsel: simmemsel@8003c400 {
  985. reg = <0x8003c400 0x100>;
  986. status = "disabled";
  987. };
  988. gpiomon: gpiomon@8003c500 {
  989. reg = <0x8003c500 0x100>;
  990. status = "disabled";
  991. };
  992. simenet: simenet@8003c700 {
  993. reg = <0x8003c700 0x100>;
  994. status = "disabled";
  995. };
  996. armjtag: armjtag@8003c800 {
  997. reg = <0x8003c800 0x100>;
  998. status = "disabled";
  999. };
  1000. };
  1001. apbx@80040000 {
  1002. compatible = "simple-bus";
  1003. #address-cells = <1>;
  1004. #size-cells = <1>;
  1005. reg = <0x80040000 0x40000>;
  1006. ranges;
  1007. clks: clkctrl@80040000 {
  1008. compatible = "fsl,imx28-clkctrl", "fsl,clkctrl";
  1009. reg = <0x80040000 0x2000>;
  1010. #clock-cells = <1>;
  1011. };
  1012. saif0: saif@80042000 {
  1013. #sound-dai-cells = <0>;
  1014. compatible = "fsl,imx28-saif";
  1015. reg = <0x80042000 0x2000>;
  1016. interrupts = <59>;
  1017. #clock-cells = <0>;
  1018. clocks = <&clks 53>;
  1019. dmas = <&dma_apbx 4>;
  1020. dma-names = "rx-tx";
  1021. status = "disabled";
  1022. };
  1023. power: power@80044000 {
  1024. reg = <0x80044000 0x2000>;
  1025. status = "disabled";
  1026. };
  1027. saif1: saif@80046000 {
  1028. #sound-dai-cells = <0>;
  1029. compatible = "fsl,imx28-saif";
  1030. reg = <0x80046000 0x2000>;
  1031. interrupts = <58>;
  1032. clocks = <&clks 54>;
  1033. dmas = <&dma_apbx 5>;
  1034. dma-names = "rx-tx";
  1035. status = "disabled";
  1036. };
  1037. lradc: lradc@80050000 {
  1038. compatible = "fsl,imx28-lradc";
  1039. reg = <0x80050000 0x2000>;
  1040. interrupts = <10 14 15 16 17 18 19
  1041. 20 21 22 23 24 25>;
  1042. status = "disabled";
  1043. clocks = <&clks 41>;
  1044. #io-channel-cells = <1>;
  1045. };
  1046. spdif: spdif@80054000 {
  1047. reg = <0x80054000 0x2000>;
  1048. interrupts = <45>;
  1049. dmas = <&dma_apbx 2>;
  1050. dma-names = "tx";
  1051. status = "disabled";
  1052. };
  1053. mxs_rtc: rtc@80056000 {
  1054. compatible = "fsl,imx28-rtc", "fsl,stmp3xxx-rtc";
  1055. reg = <0x80056000 0x2000>;
  1056. interrupts = <29>;
  1057. };
  1058. i2c0: i2c@80058000 {
  1059. #address-cells = <1>;
  1060. #size-cells = <0>;
  1061. compatible = "fsl,imx28-i2c";
  1062. reg = <0x80058000 0x2000>;
  1063. interrupts = <111>;
  1064. clock-frequency = <100000>;
  1065. dmas = <&dma_apbx 6>;
  1066. dma-names = "rx-tx";
  1067. status = "disabled";
  1068. };
  1069. i2c1: i2c@8005a000 {
  1070. #address-cells = <1>;
  1071. #size-cells = <0>;
  1072. compatible = "fsl,imx28-i2c";
  1073. reg = <0x8005a000 0x2000>;
  1074. interrupts = <110>;
  1075. clock-frequency = <100000>;
  1076. dmas = <&dma_apbx 7>;
  1077. dma-names = "rx-tx";
  1078. status = "disabled";
  1079. };
  1080. pwm: pwm@80064000 {
  1081. compatible = "fsl,imx28-pwm", "fsl,imx23-pwm";
  1082. reg = <0x80064000 0x2000>;
  1083. clocks = <&clks 44>;
  1084. #pwm-cells = <2>;
  1085. fsl,pwm-number = <8>;
  1086. status = "disabled";
  1087. };
  1088. timer: timrot@80068000 {
  1089. compatible = "fsl,imx28-timrot", "fsl,timrot";
  1090. reg = <0x80068000 0x2000>;
  1091. interrupts = <48 49 50 51>;
  1092. clocks = <&clks 26>;
  1093. };
  1094. auart0: serial@8006a000 {
  1095. compatible = "fsl,imx28-auart", "fsl,imx23-auart";
  1096. reg = <0x8006a000 0x2000>;
  1097. interrupts = <112>;
  1098. dmas = <&dma_apbx 8>, <&dma_apbx 9>;
  1099. dma-names = "rx", "tx";
  1100. clocks = <&clks 45>;
  1101. status = "disabled";
  1102. };
  1103. auart1: serial@8006c000 {
  1104. compatible = "fsl,imx28-auart", "fsl,imx23-auart";
  1105. reg = <0x8006c000 0x2000>;
  1106. interrupts = <113>;
  1107. dmas = <&dma_apbx 10>, <&dma_apbx 11>;
  1108. dma-names = "rx", "tx";
  1109. clocks = <&clks 45>;
  1110. status = "disabled";
  1111. };
  1112. auart2: serial@8006e000 {
  1113. compatible = "fsl,imx28-auart", "fsl,imx23-auart";
  1114. reg = <0x8006e000 0x2000>;
  1115. interrupts = <114>;
  1116. dmas = <&dma_apbx 12>, <&dma_apbx 13>;
  1117. dma-names = "rx", "tx";
  1118. clocks = <&clks 45>;
  1119. status = "disabled";
  1120. };
  1121. auart3: serial@80070000 {
  1122. compatible = "fsl,imx28-auart", "fsl,imx23-auart";
  1123. reg = <0x80070000 0x2000>;
  1124. interrupts = <115>;
  1125. dmas = <&dma_apbx 14>, <&dma_apbx 15>;
  1126. dma-names = "rx", "tx";
  1127. clocks = <&clks 45>;
  1128. status = "disabled";
  1129. };
  1130. auart4: serial@80072000 {
  1131. compatible = "fsl,imx28-auart", "fsl,imx23-auart";
  1132. reg = <0x80072000 0x2000>;
  1133. interrupts = <116>;
  1134. dmas = <&dma_apbx 0>, <&dma_apbx 1>;
  1135. dma-names = "rx", "tx";
  1136. clocks = <&clks 45>;
  1137. status = "disabled";
  1138. };
  1139. duart: serial@80074000 {
  1140. compatible = "arm,pl011", "arm,primecell";
  1141. reg = <0x80074000 0x1000>;
  1142. interrupts = <47>;
  1143. clocks = <&clks 45>, <&clks 26>;
  1144. clock-names = "uart", "apb_pclk";
  1145. status = "disabled";
  1146. };
  1147. usbphy0: usbphy@8007c000 {
  1148. compatible = "fsl,imx28-usbphy", "fsl,imx23-usbphy";
  1149. reg = <0x8007c000 0x2000>;
  1150. clocks = <&clks 62>;
  1151. status = "disabled";
  1152. };
  1153. usbphy1: usbphy@8007e000 {
  1154. compatible = "fsl,imx28-usbphy", "fsl,imx23-usbphy";
  1155. reg = <0x8007e000 0x2000>;
  1156. clocks = <&clks 63>;
  1157. status = "disabled";
  1158. };
  1159. };
  1160. };
  1161. ahb@80080000 {
  1162. compatible = "simple-bus";
  1163. #address-cells = <1>;
  1164. #size-cells = <1>;
  1165. reg = <0x80080000 0x80000>;
  1166. ranges;
  1167. usb0: usb@80080000 {
  1168. compatible = "fsl,imx28-usb", "fsl,imx27-usb";
  1169. reg = <0x80080000 0x10000>;
  1170. interrupts = <93>;
  1171. clocks = <&clks 60>;
  1172. fsl,usbphy = <&usbphy0>;
  1173. status = "disabled";
  1174. };
  1175. usb1: usb@80090000 {
  1176. compatible = "fsl,imx28-usb", "fsl,imx27-usb";
  1177. reg = <0x80090000 0x10000>;
  1178. interrupts = <92>;
  1179. clocks = <&clks 61>;
  1180. fsl,usbphy = <&usbphy1>;
  1181. dr_mode = "host";
  1182. status = "disabled";
  1183. };
  1184. dflpt: dflpt@800c0000 {
  1185. reg = <0x800c0000 0x10000>;
  1186. status = "disabled";
  1187. };
  1188. mac0: ethernet@800f0000 {
  1189. compatible = "fsl,imx28-fec";
  1190. reg = <0x800f0000 0x4000>;
  1191. interrupts = <101>;
  1192. clocks = <&clks 57>, <&clks 57>, <&clks 64>;
  1193. clock-names = "ipg", "ahb", "enet_out";
  1194. status = "disabled";
  1195. };
  1196. mac1: ethernet@800f4000 {
  1197. compatible = "fsl,imx28-fec";
  1198. reg = <0x800f4000 0x4000>;
  1199. interrupts = <102>;
  1200. clocks = <&clks 57>, <&clks 57>;
  1201. clock-names = "ipg", "ahb";
  1202. status = "disabled";
  1203. };
  1204. eth_switch: switch@800f8000 {
  1205. reg = <0x800f8000 0x8000>;
  1206. status = "disabled";
  1207. };
  1208. };
  1209. iio-hwmon {
  1210. compatible = "iio-hwmon";
  1211. io-channels = <&lradc 8>;
  1212. };
  1213. };