hisi-x5hd2-dkb.dts 1.3 KB

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  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. * Copyright (c) 2013-2014 Linaro Ltd.
  4. * Copyright (c) 2013-2014 HiSilicon Limited.
  5. */
  6. /dts-v1/;
  7. #include "hisi-x5hd2.dtsi"
  8. / {
  9. model = "Hisilicon HIX5HD2 Development Board";
  10. compatible = "hisilicon,hix5hd2";
  11. chosen {
  12. stdout-path = "serial0:115200n8";
  13. };
  14. cpus {
  15. #address-cells = <1>;
  16. #size-cells = <0>;
  17. enable-method = "hisilicon,hix5hd2-smp";
  18. cpu@0 {
  19. compatible = "arm,cortex-a9";
  20. device_type = "cpu";
  21. reg = <0>;
  22. next-level-cache = <&l2>;
  23. };
  24. cpu@1 {
  25. compatible = "arm,cortex-a9";
  26. device_type = "cpu";
  27. reg = <1>;
  28. next-level-cache = <&l2>;
  29. };
  30. };
  31. memory@0 {
  32. device_type = "memory";
  33. reg = <0x00000000 0x80000000>;
  34. };
  35. };
  36. &timer0 {
  37. status = "okay";
  38. };
  39. &uart0 {
  40. status = "okay";
  41. };
  42. &gmac0 {
  43. #address-cells = <1>;
  44. #size-cells = <0>;
  45. phy-handle = <&phy2>;
  46. phy-mode = "mii";
  47. /* Placeholder, overwritten by bootloader */
  48. mac-address = [00 00 00 00 00 00];
  49. status = "okay";
  50. phy2: ethernet-phy@2 {
  51. reg = <2>;
  52. };
  53. };
  54. &gmac1 {
  55. #address-cells = <1>;
  56. #size-cells = <0>;
  57. phy-handle = <&phy1>;
  58. phy-mode = "rgmii";
  59. /* Placeholder, overwritten by bootloader */
  60. mac-address = [00 00 00 00 00 00];
  61. status = "okay";
  62. phy1: ethernet-phy@1 {
  63. reg = <1>;
  64. };
  65. };
  66. &ahci {
  67. phys = <&sata_phy>;
  68. phy-names = "sata-phy";
  69. };