exynos-pinctrl.h 1.5 KB

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  1. /* SPDX-License-Identifier: GPL-2.0 */
  2. /*
  3. * Samsung Exynos DTS pinctrl constants
  4. *
  5. * Copyright (c) 2016 Samsung Electronics Co., Ltd.
  6. * http://www.samsung.com
  7. * Copyright (c) 2022 Linaro Ltd
  8. * Author: Krzysztof Kozlowski <[email protected]>
  9. */
  10. #ifndef __DTS_ARM_SAMSUNG_EXYNOS_PINCTRL_H__
  11. #define __DTS_ARM_SAMSUNG_EXYNOS_PINCTRL_H__
  12. #define EXYNOS_PIN_PULL_NONE 0
  13. #define EXYNOS_PIN_PULL_DOWN 1
  14. #define EXYNOS_PIN_PULL_UP 3
  15. /* Pin function in power down mode */
  16. #define EXYNOS_PIN_PDN_OUT0 0
  17. #define EXYNOS_PIN_PDN_OUT1 1
  18. #define EXYNOS_PIN_PDN_INPUT 2
  19. #define EXYNOS_PIN_PDN_PREV 3
  20. /* Drive strengths for Exynos3250, Exynos4 (all) and Exynos5250 */
  21. #define EXYNOS4_PIN_DRV_LV1 0
  22. #define EXYNOS4_PIN_DRV_LV2 2
  23. #define EXYNOS4_PIN_DRV_LV3 1
  24. #define EXYNOS4_PIN_DRV_LV4 3
  25. /* Drive strengths for Exynos5260 */
  26. #define EXYNOS5260_PIN_DRV_LV1 0
  27. #define EXYNOS5260_PIN_DRV_LV2 1
  28. #define EXYNOS5260_PIN_DRV_LV4 2
  29. #define EXYNOS5260_PIN_DRV_LV6 3
  30. /*
  31. * Drive strengths for Exynos5410, Exynos542x, Exynos5800 and Exynos850 (except
  32. * GPIO_HSI block)
  33. */
  34. #define EXYNOS5420_PIN_DRV_LV1 0
  35. #define EXYNOS5420_PIN_DRV_LV2 1
  36. #define EXYNOS5420_PIN_DRV_LV3 2
  37. #define EXYNOS5420_PIN_DRV_LV4 3
  38. #define EXYNOS_PIN_FUNC_INPUT 0
  39. #define EXYNOS_PIN_FUNC_OUTPUT 1
  40. #define EXYNOS_PIN_FUNC_2 2
  41. #define EXYNOS_PIN_FUNC_3 3
  42. #define EXYNOS_PIN_FUNC_4 4
  43. #define EXYNOS_PIN_FUNC_5 5
  44. #define EXYNOS_PIN_FUNC_6 6
  45. #define EXYNOS_PIN_FUNC_EINT 0xf
  46. #define EXYNOS_PIN_FUNC_F EXYNOS_PIN_FUNC_EINT
  47. #endif /* __DTS_ARM_SAMSUNG_EXYNOS_PINCTRL_H__ */