at91-cosino.dtsi 2.6 KB

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  1. // SPDX-License-Identifier: GPL-2.0-or-later
  2. /*
  3. * at91-cosino.dtsi - Device Tree file for Cosino core module
  4. *
  5. * Copyright (C) 2013 - Rodolfo Giometti <[email protected]>
  6. * HCE Engineering
  7. *
  8. * Derived from at91sam9x5ek.dtsi by:
  9. * Copyright (C) 2012 Atmel,
  10. * 2012 Nicolas Ferre <[email protected]>
  11. */
  12. #include "at91sam9g35.dtsi"
  13. / {
  14. model = "HCE Cosino core module";
  15. compatible = "hce,cosino", "atmel,at91sam9x5", "atmel,at91sam9";
  16. chosen {
  17. bootargs = "console=ttyS0,115200 root=/dev/mmcblk0p2 rw rootfstype=ext3 rootwait";
  18. };
  19. memory@20000000 {
  20. reg = <0x20000000 0x8000000>;
  21. };
  22. clocks {
  23. slow_xtal {
  24. clock-frequency = <32768>;
  25. };
  26. main_xtal {
  27. clock-frequency = <12000000>;
  28. };
  29. };
  30. };
  31. &adc0 {
  32. atmel,adc-ts-wires = <4>;
  33. atmel,adc-ts-pressure-threshold = <10000>;
  34. status = "okay";
  35. };
  36. &dbgu {
  37. status = "okay";
  38. };
  39. &ebi {
  40. pinctrl-0 = <&pinctrl_ebi_addr_nand
  41. &pinctrl_ebi_data_0_7>;
  42. pinctrl-names = "default";
  43. status = "okay";
  44. nand-controller {
  45. pinctrl-0 = <&pinctrl_nand_oe_we
  46. &pinctrl_nand_cs
  47. &pinctrl_nand_rb>;
  48. pinctrl-names = "default";
  49. status = "okay";
  50. nand@3 {
  51. reg = <0x3 0x0 0x800000>;
  52. rb-gpios = <&pioD 5 GPIO_ACTIVE_HIGH>;
  53. cs-gpios = <&pioD 4 GPIO_ACTIVE_HIGH>;
  54. nand-bus-width = <8>;
  55. nand-ecc-mode = "hw";
  56. nand-ecc-strength = <4>;
  57. nand-ecc-step-size = <512>;
  58. nand-on-flash-bbt;
  59. label = "atmel_nand";
  60. partitions {
  61. compatible = "fixed-partitions";
  62. #address-cells = <1>;
  63. #size-cells = <1>;
  64. at91bootstrap@0 {
  65. label = "at91bootstrap";
  66. reg = <0x0 0x40000>;
  67. };
  68. uboot@40000 {
  69. label = "u-boot";
  70. reg = <0x40000 0x80000>;
  71. };
  72. ubootenv@c0000 {
  73. label = "U-Boot Env";
  74. reg = <0xc0000 0x140000>;
  75. };
  76. kernel@200000 {
  77. label = "kernel";
  78. reg = <0x200000 0x600000>;
  79. };
  80. rootfs@800000 {
  81. label = "rootfs";
  82. reg = <0x800000 0x0f800000>;
  83. };
  84. };
  85. };
  86. };
  87. };
  88. &i2c0 {
  89. status = "okay";
  90. };
  91. &mmc0 {
  92. pinctrl-0 = <
  93. &pinctrl_board_mmc0
  94. &pinctrl_mmc0_slot0_clk_cmd_dat0
  95. &pinctrl_mmc0_slot0_dat1_3>;
  96. pinctrl-names = "default";
  97. status = "okay";
  98. slot@0 {
  99. reg = <0>;
  100. bus-width = <4>;
  101. cd-gpios = <&pioD 15 GPIO_ACTIVE_HIGH>;
  102. };
  103. };
  104. &pinctrl {
  105. mmc0 {
  106. pinctrl_board_mmc0: mmc0-board {
  107. atmel,pins =
  108. <AT91_PIOD 15 AT91_PERIPH_GPIO AT91_PINCTRL_PULL_UP_DEGLITCH>; /* PD15 gpio CD pin pull up and deglitch */
  109. };
  110. };
  111. };
  112. &tcb0 {
  113. timer@0 {
  114. compatible = "atmel,tcb-timer";
  115. reg = <0>;
  116. };
  117. timer@1 {
  118. compatible = "atmel,tcb-timer";
  119. reg = <1>;
  120. };
  121. };
  122. &usart0 {
  123. status = "okay";
  124. };
  125. &watchdog {
  126. status = "okay";
  127. };