aspeed-bmc-vegman-sx20.dts 6.0 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. // Copyright (C) 2021 YADRO
  3. /dts-v1/;
  4. #include "aspeed-bmc-vegman.dtsi"
  5. / {
  6. model = "YADRO VEGMAN Sx20 BMC";
  7. compatible = "yadro,vegman-sx20-bmc", "aspeed,ast2500";
  8. };
  9. &gpio {
  10. status = "okay";
  11. gpio-line-names =
  12. /*A0-A7*/ "CHASSIS_INTRUSION","CASE_OPEN_FAULT_RST","","","SPEAKER_BMC","FM_FORCE_BMC_UPDATE","","",
  13. /*B0-B7*/ "","","","","","","","",
  14. /*C0-C7*/ "","","","","","","","",
  15. /*D0-D7*/ "","","","","","","","",
  16. /*E0-E7*/ "RESET_BUTTON","RESET_OUT","POWER_BUTTON","POWER_OUT","","","","",
  17. /*F0-F7*/ "NMI_OUT","CPU1_DISABLE_COD","","","SKT0_FAULT_LED","SKT1_FAULT_LED","RST_RGMII_PHYRST_DNP","",
  18. /*G0-G7*/ "CPU_ERR2","CPU_CATERR","PCH_BMC_THERMTRIP","","IRQ_NMI_EVENT","","","",
  19. /*H0-H7*/ "PWRGD_P3V3_RISER1","PWRGD_P3V3_RISER2","PWRGD_P3V3_RISER3","","MIO_BIOS_SEL","_SPI_FLASH_HOLD","_SPI_FLASH_WP","FM_240VA_STATUS",
  20. /*I0-I7*/ "","","","","","","","",
  21. /*J0-J7*/ "","","","","","","","",
  22. /*K0-K7*/ "","","","","","","","",
  23. /*L0-L7*/ "","","","","","","","",
  24. /*M0-M7*/ "","","","","BMC_GPU_RISER_ID1","BMC_GPU_RISER_ID0","","",
  25. /*N0-N7*/ "","","","","","","","",
  26. /*O0-O7*/ "","","","","","","","_SPI2_BMC_CS_SEL",
  27. /*P0-P7*/ "","P12V_HDDS_A_EN","P12V_HDDS_B_EN","P5V_HDDS_A_EN","PWRGD_P5V_HDDS_A","P5V_HDDS_B_EN","PWRGD_P5V_HDDS_B","",
  28. /*Q0-Q7*/ "","","","","","","","",
  29. /*R0-R7*/ "_SPI_RMM4_LITE_CS","","","","","","","",
  30. /*S0-S7*/ "_SPI2_BMC_CS1","","","IRQ_SML0_ALERT_MUX","FP_LED_STATUS_GREEN","FP_LED_STATUS_AMBER","FP_ID_LED","",
  31. /*T0-T7*/ "","","","","","","","",
  32. /*U0-U7*/ "","","","","","","","",
  33. /*V0-V7*/ "","","","","","","","",
  34. /*W0-W7*/ "","","","","","","","",
  35. /*X0-X7*/ "","","","","","","","",
  36. /*Y0-Y7*/ "SIO_S3","SIO_S5","","SIO_ONCONTROL","","","","",
  37. /*Z0-Z7*/ "FM_BMC_PWR_BTN","SIO_POWER_GOOD","FM_BMC_PWRBTN_OUT","FM_BMC_PCH_SCI_LPC","","","","",
  38. /*AA0-AA7*/ "CPU_CLK_MUX_SEL","IRQ_SML1_PMBUS_ALERT","FM_PVCCIN_CPU0_PWR_IN_ALERT","FM_PVCCIN_CPU1_PWR_IN_ALERT","BMC_SYS_PWR_FAULT","BMC_SYS_PWR_OK","SMI","POST_COMPLETE",
  39. /*AB0-AB7*/ "FM_CPU_BMCINIT","NMI_BUTTON","ID_BUTTON","PS_PWROK","","","","",
  40. /*AC0-AC7*/ "","","","","","","","";
  41. };
  42. &sgpio {
  43. ngpios = <80>;
  44. bus-frequency = <2000000>;
  45. status = "okay";
  46. /* SGPIO lines. even: input, odd: output */
  47. gpio-line-names =
  48. /*A0-A7*/ "CPU1_PRESENCE","","CPU1_THERMTRIP","","CPU1_VRHOT","","CPU1_FIVR_FAULT","","CPU1_MEM_ABCD_VRHOT","","CPU1_MEM_EFGH_VRHOT","","","","","",
  49. /*B0-B7*/ "CPU1_MISMATCH","","CPU1_MEM_THERM_EVENT","","CPU2_PRESENCE","","CPU2_THERMTRIP","","CPU2_VRHOT","","CPU2_FIVR_FAULT","","CPU2_MEM_ABCD_VRHOT","","CPU2_MEM_EFGH_VRHOT","",
  50. /*C0-C7*/ "","","","","CPU2_MISMATCH","","CPU2_MEM_THERM_EVENT","","","","","","","","","",
  51. /*D0-D7*/ "","","","","","","","","","","","","","","","",
  52. /*E0-E7*/ "","","","","","","","","","","","","","","","",
  53. /*F0-F7*/ "SGPIO_PLD_MINOR_REV_BIT0","","SGPIO_PLD_MINOR_REV_BIT1","","SGPIO_PLD_MINOR_REV_BIT2","","SGPIO_PLD_MINOR_REV_BIT3","","SGPIO_PLD_MAJOR_REV_BIT0","","SGPIO_PLD_MAJOR_REV_BIT1","","SGPIO_PLD_MAJOR_REV_BIT2","","SGPIO_PLD_MAJOR_REV_BIT3","",
  54. /*G0-G7*/ "MAIN_PLD_MINOR_REV_BIT0","","MAIN_PLD_MINOR_REV_BIT1","","MAIN_PLD_MINOR_REV_BIT2","","MAIN_PLD_MINOR_REV_BIT3","","MAIN_PLD_MAJOR_REV_BIT0","","MAIN_PLD_MAJOR_REV_BIT1","","MAIN_PLD_MAJOR_REV_BIT2","","MAIN_PLD_MAJOR_REV_BIT3","",
  55. /*H0-H7*/ "","","","","","","","","","","","","","","","",
  56. /*I0-I7*/ "","","","","","","","","","","","","","","","",
  57. /*J0-J7*/ "","","","","","","","","","","","","","","","";
  58. };
  59. &i2c11 {
  60. /* SMB_BMC_MGMT_LVC3 */
  61. gpio@21 {
  62. compatible = "nxp,pcal9535";
  63. reg = <0x21>;
  64. gpio-controller;
  65. #gpio-cells = <2>;
  66. gpio-line-names =
  67. /*IO0.0-0.7*/ "", "", "CPU1_PE3_0_SLOT_PRSNT", "", "CPU1_PE1_GPU_PRSNT", "CPU1_PE3_1_SLOT_PRSNT", "PE_PCH_MEZ_PRSNT", "CPU0_PE3_1_SLOT_PRSNT",
  68. /*IO1.0-1.7*/ "CPU0_PE1_GPU_PRSNT", "CPU0_PE2_NVME2_PRSNT", "CPU1_PE2_NVME3_PRSNT", "CPU1_PE2_SLOT_PRSNT", "CPU1_PE2_NVME4_PRSNT", "", "CPU0_PE2_NVME1_PRSNT", "CPU0_PE3_0_RAID_PRSNT";
  69. };
  70. gpio@27 {
  71. compatible = "nxp,pca9698";
  72. reg = <0x27>;
  73. gpio-controller;
  74. #gpio-cells = <2>;
  75. gpio-line-names =
  76. /*IO0.0-0.7*/ "PWRGD_PS_PWROK", "PWRGD_DSW_PWROK", "PWRGD_P5V_AUX", "PWRGD_P3V3_AUX", "PWRGD_P5V", "PWRGD_P3V3", "PWRGD_P1V8_PCH_AUX", "PWRGD_PCH_PVNN_AUX",
  77. /*IO1.0-1.7*/ "PWRGD_P1V05_PCH_AUX", "PWRGD_PCH_AUX_VRS", "PWRGD_PVCCIN_CPU0", "PWRGD_PVCCSA_CPU0", "PWRGD_PVCCIO_CPU0", "PWRGD_PVMCP_CPU0", "PWRGD_P1V0_CPU0", "PWRGD_PVDDQ_ABC_CPU0",
  78. /*IO2.0-2.7*/ "PWRGD_PVPP_ABC_CPU0", "PWRGD_PVTT_ABC_CPU0", "PWRGD_PVDDQ_DEF_CPU0", "PWRGD_PVPP_DEF_CPU0", "PWRGD_PVTT_DEF_CPU0", "PWRGD_PVCCIN_CPU1", "PWRGD_PVCCSA_CPU1", "PWRGD_PVCCIO_CPU1",
  79. /*IO3.0-3.7*/ "PWRGD_PVMCP_CPU1", "PWRGD_P1V0_CPU1", "PWRGD_PVDDQ_GHJ_CPU1", "PWRGD_PVPP_GHJ_CPU1", "PWRGD_PVTT_GHJ_CPU1", "PWRGD_PVDDQ_KLM_CPU1", "PWRGD_PVPP_KLM_CPU1", "PWRGD_PVTT_KLM_CPU1",
  80. /*IO4.0-4.7*/ "PWRGD_P5V_HDDS_A_R", "PWRGD_P5V_HDDS_B_R", "", "", "", "", "", "";
  81. };
  82. };
  83. &i2c13 {
  84. /* SMB_PCIE2_STBY_LVC3 */
  85. mux-expa@73 {
  86. compatible = "nxp,pca9545";
  87. reg = <0x73>;
  88. #address-cells = <1>;
  89. #size-cells = <0>;
  90. i2c-mux-idle-disconnect;
  91. };
  92. mux-sata@71 {
  93. compatible = "nxp,pca9543";
  94. reg = <0x71>;
  95. #address-cells = <1>;
  96. #size-cells = <0>;
  97. i2c-mux-idle-disconnect;
  98. };
  99. };
  100. &i2c2 {
  101. /* SMB_PCIE_STBY_LVC3 */
  102. mux-expb@71 {
  103. compatible = "nxp,pca9545";
  104. reg = <0x71>;
  105. #address-cells = <1>;
  106. #size-cells = <0>;
  107. i2c-mux-idle-disconnect;
  108. };
  109. };
  110. &pwm_tacho {
  111. status = "okay";
  112. pinctrl-names = "default";
  113. pinctrl-0 = <&pinctrl_pwm0_default &pinctrl_pwm1_default
  114. &pinctrl_pwm2_default &pinctrl_pwm3_default
  115. &pinctrl_pwm4_default &pinctrl_pwm5_default
  116. &pinctrl_pwm6_default>;
  117. fan@0 {
  118. reg = <0x00>;
  119. aspeed,fan-tach-ch = /bits/ 8 <0x00>;
  120. };
  121. fan@1 {
  122. reg = <0x01>;
  123. aspeed,fan-tach-ch = /bits/ 8 <0x01>;
  124. };
  125. fan@2 {
  126. reg = <0x02>;
  127. aspeed,fan-tach-ch = /bits/ 8 <0x02>;
  128. };
  129. fan@3 {
  130. reg = <0x03>;
  131. aspeed,fan-tach-ch = /bits/ 8 <0x03>;
  132. };
  133. fan@4 {
  134. reg = <0x04>;
  135. aspeed,fan-tach-ch = /bits/ 8 <0x04>;
  136. };
  137. fan@5 {
  138. reg = <0x05>;
  139. aspeed,fan-tach-ch = /bits/ 8 <0x05>;
  140. };
  141. fan@6 {
  142. reg = <0x06>;
  143. aspeed,fan-tach-ch = /bits/ 8 <0x06>;
  144. };
  145. };