aspeed-bmc-vegman-rx20.dts 8.4 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. // Copyright (C) 2021 YADRO
  3. /dts-v1/;
  4. #include "aspeed-bmc-vegman.dtsi"
  5. / {
  6. model = "YADRO VEGMAN Rx20 BMC";
  7. compatible = "yadro,vegman-rx20-bmc", "aspeed,ast2500";
  8. leds {
  9. compatible = "gpio-leds";
  10. temp_alarm {
  11. label = "temp:red:status";
  12. default-state = "off";
  13. gpios = <&gpio ASPEED_GPIO(E, 4) GPIO_ACTIVE_LOW>;
  14. };
  15. temp_ok {
  16. label = "temp:green:status";
  17. default-state = "off";
  18. gpios = <&gpio ASPEED_GPIO(E, 5) GPIO_ACTIVE_LOW>;
  19. };
  20. psu_fault {
  21. label = "psu:red:status";
  22. default-state = "off";
  23. gpios = <&gpio ASPEED_GPIO(E, 6) GPIO_ACTIVE_LOW>;
  24. };
  25. psu_ok {
  26. label = "psu:green:status";
  27. default-state = "off";
  28. gpios = <&gpio ASPEED_GPIO(E, 7) GPIO_ACTIVE_LOW>;
  29. };
  30. };
  31. };
  32. &gpio {
  33. status = "okay";
  34. gpio-line-names =
  35. /*A0-A7*/ "CASE_OPEN_DNP","CASE_OPEN_FAULT_RST_DNP","BEZEL_ON_PWR_P3V3","PWM_PWRGD_EXP_EN","SPEAKER_BMC","FM_FORCE_BMC_UPDATE","","",
  36. /*B0-B7*/ "","","","","","","","",
  37. /*C0-C7*/ "","","","","","","","",
  38. /*D0-D7*/ "","","","","","","","",
  39. /*E0-E7*/ "RESET_BUTTON","RESET_OUT","POWER_BUTTON","POWER_OUT","LED_TEMP_STATUS_R","LED_TEMP_STATUS_G","LED_PWR_STATUS_R","LED_PWR_STATUS_G",
  40. /*F0-F7*/ "NMI_OUT","CPU1_DISABLE_COD","","","SKT0_FAULT_LED_DNP","SKT1_FAULT_LED_DNP","RST_RGMII_PHYRST_DNP","",
  41. /*G0-G7*/ "CPU_ERR2","CPU_CATERR","PCH_BMC_THERMTRIP","SPI_BMC_BOOT_HD","IRQ_NMI_EVENT","SPI_BMC_BOOT_WP","SPI_BMC_BOOT_WP1","",
  42. /*H0-H7*/ "PWRGD_P3V3_RISER1","PWRGD_P3V3_RISER2","PWRGD_P3V3_RISER3","","MIO_BIOS_SEL","_SPI_FLASH_HOLD","_SPI_FLASH_WP","FM_240VA_STATUS",
  43. /*I0-I7*/ "","","","","","","","",
  44. /*J0-J7*/ "","","","","","","","",
  45. /*K0-K7*/ "","","","","","","","",
  46. /*L0-L7*/ "","","","","","","","",
  47. /*M0-M7*/ "SEL_FLASH_SOFT","STATUS_SEL_BMC","","","BMC_WDT_P","ID_BUTTON","PS_PWROK","",
  48. /*N0-N7*/ "","","","","","","","",
  49. /*O0-O7*/ "","","","","","","","",
  50. /*P0-P7*/ "","","","","","","SPI_BIOS_ACTIVE_FLASH_SEL","STATUS_SEL_BIOS",
  51. /*Q0-Q7*/ "","","","","","","","",
  52. /*R0-R7*/ "_SPI_BMC_BOOT_CS1","","","","","","","",
  53. /*S0-S7*/ "_SPI2_BMC_CS1","RSR_A_SMBEXP_RST_INT","RSR_B_SMBEXP_RST_INT","IRQ_SML0_ALERT_MUX","FP_LED_STATUS_GREEN","FP_LED_STATUS_AMBER","FP_ID_LED","",
  54. /*T0-T7*/ "","","","","","","","",
  55. /*U0-U7*/ "","","","","","","","",
  56. /*V0-V7*/ "","","","","","","","",
  57. /*W0-W7*/ "","","","","","","","",
  58. /*X0-X7*/ "","","","","","","","",
  59. /*Y0-Y7*/ "SIO_S3","SIO_S5","","SIO_ONCONTROL","","","","",
  60. /*Z0-Z7*/ "FM_BMC_PWR_BTN","SIO_POWER_GOOD","FM_BMC_PWRBTN_OUT","FM_BMC_PCH_SCI_LPC","","","","",
  61. /*AA0-AA7*/ "CPU_CLK_MUX_SEL","IRQ_SML1_PMBUS_ALERT","FM_PVCCIN_CPU0_PWR_IN_ALERT","FM_PVCCIN_CPU1_PWR_IN_ALERT","BMC_SYS_PWR_FAULT","BMC_SYS_PWR_OK","SMI","POST_COMPLETE",
  62. /*AB0-AB7*/ "FM_CPU_BMCINIT","NMI_BUTTON","BMC_WDT_RST1","BMC_WDT_RST2","","","","",
  63. /*AC0-AC7*/ "","","","","","","","";
  64. };
  65. &sgpio {
  66. ngpios = <80>;
  67. bus-frequency = <2000000>;
  68. status = "okay";
  69. /* SGPIO lines. even: input, odd: output */
  70. gpio-line-names =
  71. /*A0-A7*/ "CPU1_PRESENCE","","CPU1_THERMTRIP","","CPU1_VRHOT","","CPU1_FIVR_FAULT","","CPU1_MEM_ABCD_VRHOT","","CPU1_MEM_EFGH_VRHOT","","","","","",
  72. /*B0-B7*/ "CPU1_MISMATCH","","CPU1_MEM_THERM_EVENT","","CPU2_PRESENCE","","CPU2_THERMTRIP","","CPU2_VRHOT","","CPU2_FIVR_FAULT","","CPU2_MEM_ABCD_VRHOT","","CPU2_MEM_EFGH_VRHOT","",
  73. /*C0-C7*/ "","","","","CPU2_MISMATCH","","CPU2_MEM_THERM_EVENT","","","","","","","","","",
  74. /*D0-D7*/ "","","","","","","","","","","","","","","","",
  75. /*E0-E7*/ "","","","","","","","","","","","","","","","",
  76. /*F0-F7*/ "SGPIO_PLD_MINOR_REV_BIT0","","SGPIO_PLD_MINOR_REV_BIT1","","SGPIO_PLD_MINOR_REV_BIT2","","SGPIO_PLD_MINOR_REV_BIT3","","SGPIO_PLD_MAJOR_REV_BIT0","","SGPIO_PLD_MAJOR_REV_BIT1","","SGPIO_PLD_MAJOR_REV_BIT2","","SGPIO_PLD_MAJOR_REV_BIT3","",
  77. /*G0-G7*/ "MAIN_PLD_MINOR_REV_BIT0","","MAIN_PLD_MINOR_REV_BIT1","","MAIN_PLD_MINOR_REV_BIT2","","MAIN_PLD_MINOR_REV_BIT3","","MAIN_PLD_MAJOR_REV_BIT0","","MAIN_PLD_MAJOR_REV_BIT1","","MAIN_PLD_MAJOR_REV_BIT2","","MAIN_PLD_MAJOR_REV_BIT3","",
  78. /*H0-H7*/ "","","","","","","","","","","","","","","","",
  79. /*I0-I7*/ "","","","","","","","","","","","","","","","",
  80. /*J0-J7*/ "","","","","","","","","","","","","","","","";
  81. };
  82. &i2c11 {
  83. /* SMB_BMC_MGMT_LVC3 */
  84. gpio@21 {
  85. compatible = "nxp,pcal9535";
  86. reg = <0x21>;
  87. gpio-controller;
  88. #gpio-cells = <2>;
  89. gpio-line-names =
  90. /*IO0.0-0.7*/ "ETH3_CLK_REQ", "ETH2_CLK_REQ", "RSR_A_PCIE_X16_2_PRSNT", "RSR_B_PCIE_X16_2_PRSNT", "", "RSR_B_PCIE_X8_3_PRSNT", "RSR_B_PCIE_X8_4_PRSNT", "RSR_B_PCIE_X16_PRSNT_N",
  91. /*IO1.0-1.7*/ "RSR_B_PCIE_X8_2_PRSNT", "RSR_B_PCIE_X8_1_PRSNT", "NIC_1_PE_BUF_PRSNT", "RSR_A_PCIE_X16_PRSNT", "RSR_A_PCIE_X8_3_PRSNT", "RSR_A_PCIE_X8_2_PRSNT", "RSR_A_PCIE_X8_1_PRSNT_N", "";
  92. };
  93. gpio@23 {
  94. compatible = "nxp,pcal9535";
  95. reg = <0x23>;
  96. gpio-controller;
  97. #gpio-cells = <2>;
  98. gpio-line-names =
  99. /*IO0.0-0.7*/ "FM_LINK_WIDTH_ID0", "FM_LINK_WIDTH_ID0", "FM_LINK_WIDTH_ID0", "FM_LINK_WIDTH_ID0", "FM_LINK_WIDTH_ID0", "", "", "",
  100. /*IO1.0-1.7*/ "", "", "", "", "", "", "", "";
  101. };
  102. gpio@27 {
  103. compatible = "nxp,pca9698";
  104. reg = <0x27>;
  105. gpio-controller;
  106. #gpio-cells = <2>;
  107. gpio-line-names =
  108. /*IO0.0-0.7*/ "PWRGD_PS_PWROK", "PWRGD_DSW_PWROK", "PWRGD_P5V_AUX", "PWRGD_P3V3_AUX", "PWRGD_P5V", "PWRGD_P3V3", "PWRGD_P1V8_PCH_AUX", "PWRGD_PCH_PVNN_AUX",
  109. /*IO1.0-1.7*/ "PWRGD_P1V05_PCH_AUX", "PWRGD_PCH_AUX_VRS", "PWRGD_PVCCIN_CPU0", "PWRGD_PVCCSA_CPU0", "PWRGD_PVCCIO_CPU0", "PWRGD_PVMCP_CPU0", "PWRGD_P1V0_CPU0", "PWRGD_PVDDQ_ABC_CPU0",
  110. /*IO2.0-2.7*/ "PWRGD_PVPP_ABC_CPU0", "PWRGD_PVTT_ABC_CPU0", "PWRGD_PVDDQ_DEF_CPU0", "PWRGD_PVPP_DEF_CPU0", "PWRGD_PVTT_DEF_CPU0", "PWRGD_PVCCIN_CPU1", "PWRGD_PVCCSA_CPU1", "PWRGD_PVCCIO_CPU1",
  111. /*IO3.0-3.7*/ "PWRGD_PVMCP_CPU1", "PWRGD_P1V0_CPU1", "PWRGD_PVDDQ_GHJ_CPU1", "PWRGD_PVPP_GHJ_CPU1", "PWRGD_PVTT_GHJ_CPU1", "PWRGD_PVDDQ_KLM_CPU1", "PWRGD_PVPP_KLM_CPU1", "PWRGD_PVTT_KLM_CPU1",
  112. /*IO4.0-4.7*/ "PCH_PWR_RESET_N", "FM_BOARD_SKU_ID0", "FM_BOARD_SKU_ID1", "FM_BOARD_SKU_ID2", "FM_BOARD_SKU_ID3", "FM_BOARD_SKU_ID4", "FM_BOARD_REV_ID0", "FM_BOARD_REV_ID1";
  113. };
  114. gpio@39 {
  115. compatible = "nxp,pca9554";
  116. reg = <0x39>;
  117. gpio-controller;
  118. #gpio-cells = <2>;
  119. gpio-line-names =
  120. /*IO0.0-0.7*/ "FAN_FAULT_0", "FAN_FAULT_1", "FAN_FAULT_2", "FAN_FAULT_3", "FAN_FAULT_4", "FAN_FAULT_5", "FAN_FAULT_6", "";
  121. };
  122. };
  123. &i2c13 {
  124. /* SMB_PCIE2_STBY_LVC3 */
  125. mux-expa@70 {
  126. compatible = "nxp,pca9548";
  127. reg = <0x70>;
  128. #address-cells = <1>;
  129. #size-cells = <0>;
  130. i2c-mux-idle-disconnect;
  131. i2c@2 {
  132. #address-cells = <1>;
  133. #size-cells = <0>;
  134. reg = <2>;
  135. rsra-mux@72 {
  136. compatible = "nxp,pca9548";
  137. reg = <0x72>;
  138. #address-cells = <1>;
  139. #size-cells = <0>;
  140. i2c@7 {
  141. #address-cells = <1>;
  142. #size-cells = <0>;
  143. reg = <7>;
  144. at24@50 {
  145. compatible = "atmel,24c64";
  146. reg = <0x50>;
  147. pagesize = <32>;
  148. size = <8192>;
  149. address-width = <16>;
  150. };
  151. };
  152. };
  153. };
  154. };
  155. mux-sata@71 {
  156. compatible = "nxp,pca9543";
  157. reg = <0x71>;
  158. #address-cells = <1>;
  159. #size-cells = <0>;
  160. i2c-mux-idle-disconnect;
  161. };
  162. };
  163. &i2c2 {
  164. /* SMB_PCIE_STBY_LVC3 */
  165. mux-expb@71 {
  166. compatible = "nxp,pca9548";
  167. reg = <0x71>;
  168. #address-cells = <1>;
  169. #size-cells = <0>;
  170. i2c-mux-idle-disconnect;
  171. i2c@0 {
  172. #address-cells = <1>;
  173. #size-cells = <0>;
  174. reg = <0>;
  175. rsrb-mux@72 {
  176. compatible = "nxp,pca9548";
  177. reg = <0x72>;
  178. #address-cells = <1>;
  179. #size-cells = <0>;
  180. i2c@7 {
  181. #address-cells = <1>;
  182. #size-cells = <0>;
  183. reg = <7>;
  184. at24@50 {
  185. compatible = "atmel,24c64";
  186. reg = <0x50>;
  187. pagesize = <32>;
  188. size = <8192>;
  189. address-width = <16>;
  190. };
  191. };
  192. };
  193. at24@50 {
  194. compatible = "atmel,24c64";
  195. reg = <0x50>;
  196. pagesize = <32>;
  197. size = <8192>;
  198. address-width = <16>;
  199. };
  200. };
  201. };
  202. };
  203. &pwm_tacho {
  204. status = "okay";
  205. pinctrl-names = "default";
  206. pinctrl-0 = <&pinctrl_pwm0_default &pinctrl_pwm1_default
  207. &pinctrl_pwm2_default &pinctrl_pwm3_default
  208. &pinctrl_pwm4_default &pinctrl_pwm5_default
  209. &pinctrl_pwm6_default>;
  210. fan@0 {
  211. reg = <0x00>;
  212. aspeed,fan-tach-ch = /bits/ 8 <0x00 0x07>;
  213. };
  214. fan@1 {
  215. reg = <0x01>;
  216. aspeed,fan-tach-ch = /bits/ 8 <0x01 0x08>;
  217. };
  218. fan@2 {
  219. reg = <0x02>;
  220. aspeed,fan-tach-ch = /bits/ 8 <0x02 0x09>;
  221. };
  222. fan@3 {
  223. reg = <0x03>;
  224. aspeed,fan-tach-ch = /bits/ 8 <0x03 0x0A>;
  225. };
  226. fan@4 {
  227. reg = <0x04>;
  228. aspeed,fan-tach-ch = /bits/ 8 <0x04 0x0B>;
  229. };
  230. fan@5 {
  231. reg = <0x05>;
  232. aspeed,fan-tach-ch = /bits/ 8 <0x05 0x0C>;
  233. };
  234. fan@6 {
  235. reg = <0x06>;
  236. aspeed,fan-tach-ch = /bits/ 8 <0x06 0x0D>;
  237. };
  238. };