aspeed-bmc-quanta-s6q.dts 12 KB

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  1. // SPDX-License-Identifier: GPL-2.0-or-later
  2. // Copyright 2022 Quanta Corp.
  3. /dts-v1/;
  4. #include "aspeed-g6.dtsi"
  5. #include <dt-bindings/gpio/aspeed-gpio.h>
  6. #include <dt-bindings/i2c/i2c.h>
  7. / {
  8. model = "Quanta S6Q BMC";
  9. compatible = "quanta,s6q-bmc", "aspeed,ast2600";
  10. aliases {
  11. // bus 0
  12. i2c20 = &SMB_HOST_DB2000_3V3AUX_SCL;
  13. i2c21 = &U12_PCA9546_CH1;
  14. i2c22 = &SMB_HOST_DB800_B_SCL;
  15. i2c23 = &SMB_HOST_DB800_C_SCL;
  16. // bus 1
  17. i2c24 = &SMB_M2_P0_1V8AUX_SCL;
  18. i2c25 = &SMB_M2_P1_1V8AUX_SCL;
  19. i2c26 = &SMB_CPU_PIROM_3V3AUX_SCL;
  20. i2c27 = &SMB_TEMP_3V3AUX_SCL;
  21. i2c28 = &SMB_IPMB_3V3AUX_SSDSB_SCL;
  22. i2c29 = &SMB_IPMB_3V3AUX_SCL;
  23. i2c31 = &SMB_FB_SCL;
  24. // bus 1 - Fan board
  25. i2c32 = &SMB_IOEXP_SCL;
  26. i2c33 = &SMB_PROGRAM_SCL;
  27. i2c34 = &SMB_FB_SCL_CH2;
  28. i2c35 = &SMB_FAN_SENSE_SCL;
  29. // bus 6
  30. i2c36 = &U197_PCA9546_CH0;
  31. i2c37 = &U197_PCA9546_CH1;
  32. i2c38 = &U197_PCA9546_CH2;
  33. i2c39 = &U197_PCA9546_CH3;
  34. //bus 7
  35. i2c40 = &SMB_OCP_SFF_3V3AUX_SCL; //OCP1
  36. i2c41 = &SMB_OCP_LFF_3V3AUX_SCL; //OCP2
  37. };
  38. chosen {
  39. stdout-path = &uart5;
  40. bootargs = "console=ttyS4,115200n8 earlycon";
  41. };
  42. memory@80000000 {
  43. device_type = "memory";
  44. reg = <0x80000000 0x40000000>;
  45. };
  46. iio-hwmon {
  47. compatible = "iio-hwmon";
  48. io-channels = <&adc0 0>, <&adc0 1>, <&adc0 2>, <&adc0 3>,
  49. <&adc0 4>, <&adc0 5>, <&adc0 6>, <&adc0 7>,
  50. <&adc1 0>, <&adc1 1>, <&adc1 2>, <&adc1 3>,
  51. <&adc1 4>, <&adc1 5>, <&adc1 6>, <&adc1 7>;
  52. };
  53. leds {
  54. compatible = "gpio-leds";
  55. BMC_HEARTBEAT_N {
  56. label = "BMC_HEARTBEAT_N";
  57. gpios = <&gpio0 ASPEED_GPIO(P, 7) GPIO_ACTIVE_LOW>;
  58. linux,default-trigger = "heartbeat";
  59. };
  60. BMC_LED_STATUS_AMBER_N {
  61. label = "BMC_LED_STATUS_AMBER_N";
  62. gpios = <&gpio0 ASPEED_GPIO(S, 6) GPIO_ACTIVE_LOW>;
  63. default-state = "off";
  64. };
  65. FM_ID_LED_N {
  66. label = "FM_ID_LED_N";
  67. gpios = <&gpio0 ASPEED_GPIO(B, 5) GPIO_ACTIVE_LOW>;
  68. default-state = "off";
  69. };
  70. };
  71. };
  72. &gpio0 {
  73. gpio-line-names =
  74. /*A0 - A7*/ "", "", "", "", "", "", "", "",
  75. /*B0 - B7*/ "", "", "", "", "", "", "", "",
  76. /*C0 - C7*/ "", "", "", "", "", "", "", "",
  77. /*D0 - D7*/ "", "", "", "", "", "", "", "",
  78. /*E0 - E7*/ "", "", "", "", "", "", "", "",
  79. /*F0 - F7*/ "PLTRST_N", "", "PWR_DEBUG_N", "", "", "", "", "",
  80. /*G0 - G7*/ "", "", "", "", "", "", "", "",
  81. /*H0 - H7*/ "", "", "", "", "", "", "", "",
  82. /*I0 - I7*/ "", "", "", "", "", "", "", "",
  83. /*J0 - J7*/ "", "", "", "", "", "", "", "",
  84. /*K0 - K7*/ "", "", "", "", "", "", "", "",
  85. /*L0 - L7*/ "", "", "", "", "PREQ_N", "TCK_MUX_SEL", "", "",
  86. /*M0 - M7*/ "", "", "", "PWRGD_SYS_PWROK", "", "PRDY_N", "", "",
  87. /*N0 - N7*/ "", "", "", "", "", "", "", "",
  88. /*O0 - O7*/ "", "", "", "", "", "", "", "",
  89. /*P0 - P7*/ "SYS_BMC_PWRBTN_R_N", "SYS_PWRBTN_N", "FM_MB_RST_BTN", "RST_BMC_RSTBTN_OUT_N", "", "", "", "",
  90. /*Q0 - Q7*/ "", "", "", "", "", "", "", "",
  91. /*R0 - R7*/ "", "", "", "", "", "", "", "",
  92. /*S0 - S7*/ "", "", "", "FP_ID_BTN_SCM_N", "", "", "", "",
  93. /*T0 - T7*/ "", "", "", "", "", "", "", "",
  94. /*U0 - U7*/ "", "", "", "", "", "", "", "",
  95. /*V0 - V7*/ "", "", "", "", "", "SMI", "", "",
  96. /*W0 - W7*/ "", "", "", "", "", "", "", "",
  97. /*X0 - X7*/ "", "", "", "", "", "", "", "",
  98. /*Y0 - Y7*/ "", "", "", "", "", "", "", "",
  99. /*Z0 - Z7*/ "FM_BMC_READY_N", "", "", "", "", "", "", "",
  100. /*AA0 - AA7*/ "", "", "", "", "", "", "", "",
  101. /*AB0 - AB7*/ "", "", "", "", "", "", "", "",
  102. /*AC0 - AC7*/ "", "", "", "", "", "", "", "";
  103. };
  104. &sgpiom0 {
  105. status = "okay";
  106. ngpios = <128>;
  107. bus-frequency = <48000>;
  108. gpio-line-names =
  109. /* SGPIO input lines */
  110. /*IOA0-IOA7*/ "","", "SIO_POWER_GOOD","OA1", "XDP_PRST_N","", "","", "FM_SLPS3_PLD_N","", "FM_SLPS4_PLD_N","", "FM_BIOS_POST_CMPLT_BMC_N","", "FM_ADR_TRIGGER_N","OA7",
  111. /*IOB0-IOB7*/ "FM_ADR_COMPLETE","", "FM_PMBUS_ALERT_B_EN","", "PSU0_PRESENT_N","", "PSU1_PRESENT_N","", "PSU0_VIN_BUF_GOOD","", "PSU01_VIN_BUF_GOOD","", "PWRGD_PS0_PWROK_R","", "PWRGD_PS1_PWROK_R","",
  112. /*IOC0-IOC7*/ "PWRGD_PS_PWROK_PLD_R","", "CHASSIS_INTRUSION","", "BMC_MFG_MODE","", "FM_BMC_EN_DET_R","", "FM_ME_BT_DONE","", "CPU1_PRESENCE","", "CPU2_PRESENCE","", "IRQ_PSYS_CRIT_N","",
  113. /*IOD0-IOD7*/ "","", "CPU1_THERMTRIP","", "CPU2_THERMTRIP","", "CPU1_MEM_THERM_EVENT","", "CPU2_MEM_THERM_EVENT","", "CPU1_VRHOT","", "CPU2_VRHOT","", "","",
  114. /*IOE0-IOE7*/ "","", "CPU1_MEM_VRHOT","", "CPU2_MEM_VRHOT","", "","", "PCH_BMC_THERMTRIP","", "","", "","", "","",
  115. /*IOF0-IOF7*/ "CPU_ERR0","", "CPU_ERR1","", "CPU_ERR2","", "","", "","", "CPU_CATERR","", "","", "","",
  116. /*IOG0-IOG7*/ "","", "","", "","", "","", "","", "","", "","", "","",
  117. /*IOH0-IOH7*/ "","", "FP_ID_BTN_R1_N","", "FP_RST_BTN_N","", "","", "","", "FP_PWR_BTN_PLD_N_R","", "","", "","",
  118. /*IOI0-IOI7*/ "","", "","", "","", "","", "","", "","", "","", "","",
  119. /*IOJ0-IOJ7*/ "","", "","", "","", "","", "","", "","", "","", "","",
  120. /*IOK0-IOK7*/ "","", "","", "","", "","", "","", "","", "","", "","",
  121. /*IOL0-IOL7*/ "","", "","", "","", "","", "","", "","", "","", "","",
  122. /*IOM0-IOM7*/ "","", "","", "","", "","", "","", "","", "","", "","",
  123. /*ION0-ION7*/ "","BMC_SW_HEARTBEAT_N_R", "","FP_LED_FAULT_N", "","FP_ID_LED_N", "","FM_BMC_RSTBTN_OUT_N", "","FM_THERMTRIP_DLY_LVC1_R_N", "","", "","RST_PCA9548_SENSOR_PLD_N", "","USB_OC1_REAR_N",
  124. /*IOO0-IOO7*/ "","IRQ_TPM_SPI_N", "","", "","IRQ_PCH_SCI_WHEA_R_N", "","IRQ_BMC_PCH_NMI_R", "","H_CPU_NMI_LVC1_R_N", "","", "","", "","FM_JTAG_BMC_PLD_MUX_SEL",
  125. /*IOP0-IOP7*/ "IP0","OP0", "","", "","", "","", "","", "","", "","", "IP7","OP7";
  126. };
  127. &adc0 {
  128. vref = <2500>;
  129. status = "okay";
  130. pinctrl-names = "default";
  131. pinctrl-0 = <&pinctrl_adc0_default &pinctrl_adc1_default
  132. &pinctrl_adc2_default &pinctrl_adc3_default
  133. &pinctrl_adc4_default &pinctrl_adc5_default
  134. &pinctrl_adc6_default &pinctrl_adc7_default>;
  135. };
  136. &adc1 {
  137. vref = <2500>;
  138. status = "okay";
  139. pinctrl-names = "default";
  140. pinctrl-0 = <&pinctrl_adc8_default &pinctrl_adc9_default
  141. &pinctrl_adc10_default &pinctrl_adc11_default
  142. &pinctrl_adc12_default &pinctrl_adc13_default
  143. &pinctrl_adc14_default &pinctrl_adc15_default>;
  144. };
  145. &mdio2 {
  146. status = "okay";
  147. ethphy2: ethernet-phy@0 {
  148. compatible = "ethernet-phy-ieee802.3-c22";
  149. reg = <0>;
  150. };
  151. };
  152. &mac2 {
  153. status = "okay";
  154. phy-mode = "rgmii";
  155. phy-handle = <&ethphy2>;
  156. pinctrl-names = "default";
  157. pinctrl-0 = <&pinctrl_rgmii3_default>;
  158. };
  159. &mac3 {
  160. status = "okay";
  161. phy-mode = "rmii";
  162. use-ncsi;
  163. pinctrl-names = "default";
  164. pinctrl-0 = <&pinctrl_rmii4_default>;
  165. };
  166. &fmc {
  167. status = "okay";
  168. flash@0 {
  169. status = "okay";
  170. m25p,fast-read;
  171. label = "bmc";
  172. spi-max-frequency = <50000000>;
  173. #include "openbmc-flash-layout-64.dtsi"
  174. };
  175. };
  176. &spi2 {
  177. pinctrl-names = "default";
  178. pinctrl-0 = <&pinctrl_spi2_default &pinctrl_spi2cs1_default
  179. &pinctrl_spi2cs2_default>;
  180. status = "okay";
  181. flash@0 {
  182. status = "okay";
  183. m25p,fast-read;
  184. label = "spi2:0";
  185. spi-max-frequency = <50000000>;
  186. };
  187. };
  188. &kcs1 {
  189. status = "okay";
  190. aspeed,lpc-io-reg = <0xCA0>;
  191. };
  192. &kcs2 {
  193. status = "okay";
  194. aspeed,lpc-io-reg = <0xCA8>;
  195. };
  196. &kcs3 {
  197. status = "okay";
  198. aspeed,lpc-io-reg = <0xCA2>;
  199. };
  200. &emmc_controller {
  201. status = "okay";
  202. };
  203. &emmc {
  204. non-removable;
  205. bus-width = <4>;
  206. max-frequency = <100000000>;
  207. };
  208. &vhub {
  209. status = "okay";
  210. };
  211. &lpc_snoop {
  212. status = "okay";
  213. snoop-ports = <0x80>;
  214. };
  215. &uart1 {
  216. status = "okay";
  217. };
  218. &uart2 {
  219. status = "okay";
  220. };
  221. &uart4 {
  222. status = "okay";
  223. };
  224. &uart5 {
  225. status = "okay";
  226. };
  227. &uart_routing {
  228. status = "okay";
  229. };
  230. &i2c0 {
  231. status = "okay";
  232. U34_PWR_ADC@48 {
  233. compatible = "ti,ads7830";
  234. reg = <0x48>;
  235. };
  236. U35_PWR_ADC@4b {
  237. compatible = "ti,ads7830";
  238. reg = <0x4b>;
  239. };
  240. i2c-switch@70 {
  241. compatible = "nxp,pca9546";
  242. reg = <0x70>;
  243. #address-cells = <1>;
  244. #size-cells = <0>;
  245. i2c-mux-idle-disconnect;
  246. SMB_HOST_DB2000_3V3AUX_SCL: i2c@0 {
  247. #address-cells = <1>;
  248. #size-cells = <0>;
  249. reg = <0>;
  250. };
  251. U12_PCA9546_CH1: i2c@1 {
  252. #address-cells = <1>;
  253. #size-cells = <0>;
  254. reg = <1>;
  255. };
  256. SMB_HOST_DB800_B_SCL: i2c@2 {
  257. #address-cells = <1>;
  258. #size-cells = <0>;
  259. reg = <2>;
  260. };
  261. SMB_HOST_DB800_C_SCL: i2c@3 {
  262. #address-cells = <1>;
  263. #size-cells = <0>;
  264. reg = <3>;
  265. };
  266. };
  267. };
  268. &i2c1 {
  269. status = "okay";
  270. i2c-switch@59 {
  271. compatible = "nxp,pca9848";
  272. reg = <0x59>;
  273. #address-cells = <1>;
  274. #size-cells = <0>;
  275. i2c-mux-idle-disconnect;
  276. SMB_M2_P0_1V8AUX_SCL: i2c@0 {
  277. #address-cells = <1>;
  278. #size-cells = <0>;
  279. reg = <0>;
  280. };
  281. SMB_M2_P1_1V8AUX_SCL: i2c@1 {
  282. #address-cells = <1>;
  283. #size-cells = <0>;
  284. reg = <1>;
  285. };
  286. SMB_CPU_PIROM_3V3AUX_SCL: i2c@2 {
  287. #address-cells = <1>;
  288. #size-cells = <0>;
  289. reg = <2>;
  290. };
  291. SMB_TEMP_3V3AUX_SCL: i2c@3 {
  292. #address-cells = <1>;
  293. #size-cells = <0>;
  294. reg = <3>;
  295. U163_tmp75@48 {
  296. compatible = "ti,tmp75";
  297. reg = <0x48>;
  298. };
  299. U114_tmp75@49 {
  300. compatible = "ti,tmp75";
  301. reg = <0x49>;
  302. };
  303. };
  304. SMB_IPMB_3V3AUX_SSDSB_SCL: i2c@4 {
  305. #address-cells = <1>;
  306. #size-cells = <0>;
  307. reg = <4>;
  308. U4_tmp75@4c {
  309. compatible = "ti,tmp75";
  310. reg = <0x4c>;
  311. };
  312. U73_tmp75@4d {
  313. compatible = "ti,tmp75";
  314. reg = <0x4d>;
  315. };
  316. };
  317. SMB_IPMB_3V3AUX_SCL: i2c@5 {
  318. #address-cells = <1>;
  319. #size-cells = <0>;
  320. reg = <5>;
  321. U190_fru@51 {
  322. compatible = "atmel,24c128";
  323. reg = <0x51>;
  324. pagesize = <32>;
  325. };
  326. };
  327. SMB_FB_SCL: i2c@7 {
  328. #address-cells = <1>;
  329. #size-cells = <0>;
  330. reg = <7>;
  331. i2c-switch@77 {
  332. compatible = "nxp,pca9546";
  333. reg = <0x77>;
  334. #address-cells = <1>;
  335. #size-cells = <0>;
  336. i2c-mux-idle-disconnect;
  337. SMB_IOEXP_SCL: i2c@0 {
  338. #address-cells = <1>;
  339. #size-cells = <0>;
  340. reg = <0>;
  341. };
  342. SMB_PROGRAM_SCL: i2c@1 {
  343. #address-cells = <1>;
  344. #size-cells = <0>;
  345. reg = <1>;
  346. };
  347. SMB_FB_SCL_CH2: i2c@2 {
  348. #address-cells = <1>;
  349. #size-cells = <0>;
  350. reg = <2>;
  351. };
  352. SMB_FAN_SENSE_SCL: i2c@3 {
  353. #address-cells = <1>;
  354. #size-cells = <0>;
  355. reg = <3>;
  356. Current_Meter_U2@45 {
  357. compatible = "ti,ina219";
  358. reg = <0x45>;
  359. shunt-resistor = <1000>; /* = 1 mOhm */
  360. };
  361. Current_Meter_U3@44 {
  362. compatible = "ti,ina219";
  363. reg = <0x44>;
  364. shunt-resistor = <1000>; /* = 1 mOhm */
  365. };
  366. TEMP_sensor_U2@4b {
  367. compatible = "ti,tmp75";
  368. reg = <0x4b>;
  369. };
  370. };
  371. };
  372. };
  373. };
  374. };
  375. &i2c2 {
  376. status = "okay";
  377. bus-frequency = <400000>;
  378. ipmb@10 {
  379. compatible = "ipmb-dev";
  380. reg = <(0x10 | I2C_OWN_SLAVE_ADDRESS)>;
  381. i2c-protocol;
  382. };
  383. };
  384. &i2c3 {
  385. status = "okay";
  386. /* MB FRU (U173) @ 0xA2 */
  387. mb_fru: mb_fru@51 {
  388. compatible = "atmel,24c128";
  389. reg = <0x51>;
  390. pagesize = <32>;
  391. };
  392. /* FP_U1 Inlet */
  393. FP_U1_tmp75@4a {
  394. compatible = "ti,tmp75";
  395. reg = <0x4a>;
  396. };
  397. FP_U4_fru@52 {
  398. compatible = "atmel,24c02";
  399. reg = <0x52>;
  400. pagesize = <16>;
  401. };
  402. };
  403. &i2c4 {
  404. status = "okay";
  405. };
  406. &i2c5 {
  407. status = "okay";
  408. };
  409. &i2c6 {
  410. status = "okay";
  411. i2c-switch@77 {
  412. compatible = "nxp,pca9548";
  413. #address-cells = <1>;
  414. #size-cells = <0>;
  415. reg = <0x77>;
  416. i2c-mux-idle-disconnect;
  417. U197_PCA9546_CH0: i2c@0 {
  418. #address-cells = <1>;
  419. #size-cells = <0>;
  420. reg = <0>;
  421. };
  422. U197_PCA9546_CH1: i2c@1 {
  423. #address-cells = <1>;
  424. #size-cells = <0>;
  425. reg = <1>;
  426. cpu0_pvccin@60 {
  427. compatible = "isil,raa229004";
  428. reg = <0x60>;
  429. };
  430. cpu0_pvccinfaon@61 {
  431. compatible = "isil,isl69260";
  432. reg = <0x61>;
  433. };
  434. cpu0_pvccd_hv@63 {
  435. compatible = "isil,isl69260";
  436. reg = <0x63>;
  437. };
  438. };
  439. U197_PCA9546_CH2: i2c@2 {
  440. #address-cells = <1>;
  441. #size-cells = <0>;
  442. reg = <2>;
  443. cpu1_pvccin@72 {
  444. compatible = "isil,raa229004";
  445. reg = <0x72>;
  446. };
  447. cpu1_pvccinfaon@74 {
  448. compatible = "isil,isl69260";
  449. reg = <0x74>;
  450. };
  451. cpu1_pvccd_hv@76 {
  452. compatible = "isil,isl69260";
  453. reg = <0x76>;
  454. };
  455. };
  456. U197_PCA9546_CH3: i2c@3 {
  457. #address-cells = <1>;
  458. #size-cells = <0>;
  459. reg = <3>;
  460. };
  461. };
  462. };
  463. &i2c7 {
  464. status = "okay";
  465. i2c-switch@75 {
  466. compatible = "nxp,pca9546";
  467. #address-cells = <1>;
  468. #size-cells = <0>;
  469. reg = <0x75>;
  470. i2c-mux-idle-disconnect;
  471. SMB_OCP_SFF_3V3AUX_SCL: i2c@0 {
  472. #address-cells = <1>;
  473. #size-cells = <0>;
  474. reg = <0>;
  475. };
  476. SMB_OCP_LFF_3V3AUX_SCL: i2c@1 {
  477. #address-cells = <1>;
  478. #size-cells = <0>;
  479. reg = <1>;
  480. };
  481. };
  482. };
  483. &i2c8 {
  484. status = "okay";
  485. };
  486. &i2c9 {
  487. status = "okay";
  488. };
  489. &i2c11 {
  490. status = "okay";
  491. };
  492. &i2c14 {
  493. status = "okay";
  494. /* SCM FRU (U19) @ 0xA2 */
  495. scm_fru: scm_fru@51 {
  496. compatible = "atmel,24c128";
  497. reg = <0x51>;
  498. pagesize = <32>;
  499. };
  500. scm_tmp75_u4@4a {
  501. compatible = "ti,tmp75";
  502. reg = <0x4a>;
  503. };
  504. };
  505. &i2c15 {
  506. status = "okay";
  507. };