aspeed-bmc-facebook-tiogapass.dts 9.9 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241242243244245246247248249250251252253254255256257258259260261262263264265266267268269270271272273274275276277278279280281282283284285286287288289290291292293294295296297298299300301302303304305306307308309310311312313314315316317318319320321322323324325326327328329330331332333334335336337338339340341342343344345346347348349350351352353354355356357358359360361362363364365366367368369370371372373374375376377378379380381382383384385386387388389390391392393394395396397398399400401402403404405406407408409410411412413414415416417418419420421422423424425426427428429430431432433434435436437438439440441442443444445446447448449450451452453454455456457458459460461462463464465466467468469470471472473474475476477478479480481482483484485486487488489490491492493494495496497498499500501502503504505506507508509510511512513514515516517518519520521522523524525526527528529530531532533534535536537538539540541542543544545546547548549
  1. // SPDX-License-Identifier: GPL-2.0+
  2. // Copyright (c) 2018 Facebook Inc.
  3. // Author: Vijay Khemka <[email protected]>
  4. /dts-v1/;
  5. #include "aspeed-g5.dtsi"
  6. #include <dt-bindings/gpio/aspeed-gpio.h>
  7. #include <dt-bindings/i2c/i2c.h>
  8. / {
  9. model = "Facebook TiogaPass BMC";
  10. compatible = "facebook,tiogapass-bmc", "aspeed,ast2500";
  11. aliases {
  12. serial0 = &uart1;
  13. serial4 = &uart5;
  14. /*
  15. * Hardcode the bus number of i2c switches' channels to
  16. * avoid breaking the legacy applications.
  17. */
  18. i2c16 = &imux16;
  19. i2c17 = &imux17;
  20. i2c18 = &imux18;
  21. i2c19 = &imux19;
  22. i2c20 = &imux20;
  23. i2c21 = &imux21;
  24. i2c22 = &imux22;
  25. i2c23 = &imux23;
  26. i2c24 = &imux24;
  27. i2c25 = &imux25;
  28. i2c26 = &imux26;
  29. i2c27 = &imux27;
  30. i2c28 = &imux28;
  31. i2c29 = &imux29;
  32. i2c30 = &imux30;
  33. i2c31 = &imux31;
  34. };
  35. chosen {
  36. stdout-path = &uart5;
  37. bootargs = "console=ttyS4,115200 earlycon";
  38. };
  39. memory@80000000 {
  40. reg = <0x80000000 0x20000000>;
  41. };
  42. iio-hwmon {
  43. compatible = "iio-hwmon";
  44. io-channels = <&adc 0>, <&adc 1>, <&adc 2>, <&adc 3>,
  45. <&adc 4>, <&adc 5>, <&adc 6>, <&adc 7>;
  46. };
  47. };
  48. &fmc {
  49. status = "okay";
  50. flash@0 {
  51. status = "okay";
  52. m25p,fast-read;
  53. #include "openbmc-flash-layout.dtsi"
  54. };
  55. };
  56. &spi1 {
  57. status = "okay";
  58. pinctrl-names = "default";
  59. pinctrl-0 = <&pinctrl_spi1_default>;
  60. flash@0 {
  61. status = "okay";
  62. m25p,fast-read;
  63. label = "pnor";
  64. };
  65. };
  66. &lpc_snoop {
  67. status = "okay";
  68. snoop-ports = <0x80>;
  69. };
  70. &lpc_ctrl {
  71. // Enable lpc clock
  72. status = "okay";
  73. };
  74. &uart1 {
  75. // Host Console
  76. status = "okay";
  77. pinctrl-names = "default";
  78. pinctrl-0 = <&pinctrl_txd1_default
  79. &pinctrl_rxd1_default>;
  80. };
  81. &uart2 {
  82. // SoL Host Console
  83. status = "okay";
  84. };
  85. &uart3 {
  86. // SoL BMC Console
  87. status = "okay";
  88. };
  89. &uart5 {
  90. // BMC Console
  91. status = "okay";
  92. };
  93. &kcs2 {
  94. // BMC KCS channel 2
  95. status = "okay";
  96. aspeed,lpc-io-reg = <0xca8>;
  97. };
  98. &kcs3 {
  99. // BMC KCS channel 3
  100. status = "okay";
  101. aspeed,lpc-io-reg = <0xca2>;
  102. };
  103. &gpio {
  104. status = "okay";
  105. gpio-line-names =
  106. /*A0-A7*/ "BMC_CPLD_FPGA_SEL","","","","","","","",
  107. /*B0-B7*/ "","BMC_DEBUG_EN","","","","BMC_PPIN","PS_PWROK",
  108. "IRQ_PVDDQ_GHJ_VRHOT_LVT3",
  109. /*C0-C7*/ "","","","","","","","",
  110. /*D0-D7*/ "BIOS_MRC_DEBUG_MSG_DIS","BOARD_REV_ID0","",
  111. "BOARD_REV_ID1","IRQ_DIMM_SAVE_LVT3","BOARD_REV_ID2",
  112. "CPU_ERR0_LVT3_BMC","CPU_ERR1_LVT3_BMC",
  113. /*E0-E7*/ "RESET_BUTTON","RESET_OUT","POWER_BUTTON",
  114. "POWER_OUT","NMI_BUTTON","","CPU0_PROCHOT_LVT3_ BMC",
  115. "CPU1_PROCHOT_LVT3_ BMC",
  116. /*F0-F7*/ "IRQ_PVDDQ_ABC_VRHOT_LVT3","",
  117. "IRQ_PVCCIN_CPU0_VRHOT_LVC3",
  118. "IRQ_PVCCIN_CPU1_VRHOT_LVC3",
  119. "IRQ_PVDDQ_KLM_VRHOT_LVT3","","P3VBAT_BRIDGE_EN","",
  120. /*G0-G7*/ "CPU_ERR2_LVT3","CPU_CATERR_LVT3","PCH_BMC_THERMTRIP",
  121. "CPU0_SKTOCC_LVT3","","","","BIOS_SMI_ACTIVE",
  122. /*H0-H7*/ "LED_POST_CODE_0","LED_POST_CODE_1","LED_POST_CODE_2",
  123. "LED_POST_CODE_3","LED_POST_CODE_4","LED_POST_CODE_5",
  124. "LED_POST_CODE_6","LED_POST_CODE_7",
  125. /*I0-I7*/ "CPU0_FIVR_FAULT_LVT3","CPU1_FIVR_FAULT_LVT3",
  126. "FORCE_ADR","UV_ADR_TRIGGER_EN","","","","",
  127. /*J0-J7*/ "","","","","","","","",
  128. /*K0-K7*/ "","","","","","","","",
  129. /*L0-L7*/ "IRQ_UV_DETECT","IRQ_OC_DETECT","HSC_TIMER_EXP","",
  130. "MEM_THERM_EVENT_PCH","PMBUS_ALERT_BUF_EN","","",
  131. /*M0-M7*/ "CPU0_RC_ERROR","CPU1_RC_ERROR","","OC_DETECT_EN",
  132. "CPU0_THERMTRIP_LATCH_LVT3",
  133. "CPU1_THERMTRIP_LATCH_LVT3","","",
  134. /*N0-N7*/ "","","","CPU_MSMI_LVT3","","BIOS_SPI_BMC_CTRL","","",
  135. /*O0-O7*/ "","","","","","","","",
  136. /*P0-P7*/ "BOARD_SKU_ID0","BOARD_SKU_ID1","BOARD_SKU_ID2",
  137. "BOARD_SKU_ID3","BOARD_SKU_ID4","BMC_PREQ",
  138. "BMC_PWR_DEBUG","RST_RSMRST",
  139. /*Q0-Q7*/ "","","","","UARTSW_LSB","UARTSW_MSB",
  140. "POST_CARD_PRES_BMC","PE_BMC_WAKE",
  141. /*R0-R7*/ "","","BMC_TCK_MUX_SEL","BMC_PRDY",
  142. "BMC_XDP_PRSNT_IN","RST_BMC_PLTRST_BUF","SLT_CFG0",
  143. "SLT_CFG1",
  144. /*S0-S7*/ "THROTTLE","BMC_READY","","HSC_SMBUS_SWITCH_EN","",
  145. "","","",
  146. /*T0-T7*/ "","","","","","","","",
  147. /*U0-U7*/ "","","","","","BMC_FAULT","","",
  148. /*V0-V7*/ "","","","FAST_PROCHOT_EN","","","","",
  149. /*W0-W7*/ "","","","","","","","",
  150. /*X0-X7*/ "","","","GLOBAL_RST_WARN",
  151. "CPU0_MEMABC_MEMHOT_LVT3_BMC",
  152. "CPU0_MEMDEF_MEMHOT_LVT3_BMC",
  153. "CPU1_MEMGHJ_MEMHOT_LVT3_BMC",
  154. "CPU1_MEMKLM_MEMHOT_LVT3_BMC",
  155. /*Y0-Y7*/ "SIO_S3","SIO_S5","BMC_JTAG_SEL","SIO_ONCONTROL","",
  156. "","","",
  157. /*Z0-Z7*/ "","SIO_POWER_GOOD","IRQ_PVDDQ_DEF_VRHOT_LVT3","",
  158. "","","","",
  159. /*AA0-AA7*/ "CPU1_SKTOCC_LVT3","IRQ_SML1_PMBUS_ALERT",
  160. "SERVER_POWER_LED","","PECI_MUX_SELECT","UV_HIGH_SET",
  161. "","POST_COMPLETE",
  162. /*AB0-AB7*/ "IRQ_HSC_FAULT","OCP_MEZZA_PRES","","","","","","",
  163. /*AC0-AC7*/ "","","","","","","","";
  164. };
  165. &mac0 {
  166. status = "okay";
  167. pinctrl-names = "default";
  168. pinctrl-0 = <&pinctrl_rmii1_default>;
  169. clocks = <&syscon ASPEED_CLK_GATE_MAC1CLK>,
  170. <&syscon ASPEED_CLK_MAC1RCLK>;
  171. clock-names = "MACCLK", "RCLK";
  172. use-ncsi;
  173. };
  174. &mac1 {
  175. status = "okay";
  176. pinctrl-names = "default";
  177. pinctrl-0 = <&pinctrl_rmii2_default>;
  178. use-ncsi;
  179. };
  180. &adc {
  181. status = "okay";
  182. };
  183. &i2c0 {
  184. status = "okay";
  185. //Airmax Conn B, CPU0 PIROM, CPU1 PIROM
  186. };
  187. &i2c1 {
  188. status = "okay";
  189. //X24 Riser
  190. i2c-switch@71 {
  191. compatible = "nxp,pca9544";
  192. #address-cells = <1>;
  193. #size-cells = <0>;
  194. reg = <0x71>;
  195. imux16: i2c@0 {
  196. #address-cells = <1>;
  197. #size-cells = <0>;
  198. reg = <0>;
  199. ina230@45 {
  200. compatible = "ti,ina230";
  201. reg = <0x45>;
  202. };
  203. tmp75@48 {
  204. compatible = "ti,tmp75";
  205. reg = <0x48>;
  206. };
  207. tmp421@49 {
  208. compatible = "ti,tmp75";
  209. reg = <0x49>;
  210. };
  211. eeprom@50 {
  212. compatible = "atmel,24c64";
  213. reg = <0x50>;
  214. pagesize = <32>;
  215. };
  216. i2c-switch@73 {
  217. compatible = "nxp,pca9546";
  218. #address-cells = <1>;
  219. #size-cells = <0>;
  220. reg = <0x73>;
  221. imux20: i2c@0 {
  222. #address-cells = <1>;
  223. #size-cells = <0>;
  224. reg = <0>;
  225. };
  226. imux21: i2c@1 {
  227. #address-cells = <1>;
  228. #size-cells = <0>;
  229. reg = <1>;
  230. };
  231. imux22: i2c@2 {
  232. #address-cells = <1>;
  233. #size-cells = <0>;
  234. reg = <2>;
  235. };
  236. imux23: i2c@3 {
  237. #address-cells = <1>;
  238. #size-cells = <0>;
  239. reg = <3>;
  240. };
  241. };
  242. };
  243. imux17: i2c@1 {
  244. #address-cells = <1>;
  245. #size-cells = <0>;
  246. reg = <1>;
  247. ina230@45 {
  248. compatible = "ti,ina230";
  249. reg = <0x45>;
  250. };
  251. tmp421@48 {
  252. compatible = "ti,tmp75";
  253. reg = <0x48>;
  254. };
  255. tmp421@49 {
  256. compatible = "ti,tmp75";
  257. reg = <0x49>;
  258. };
  259. eeprom@50 {
  260. compatible = "atmel,24c64";
  261. reg = <0x50>;
  262. pagesize = <32>;
  263. };
  264. i2c-switch@73 {
  265. compatible = "nxp,pca9546";
  266. #address-cells = <1>;
  267. #size-cells = <0>;
  268. reg = <0x73>;
  269. imux24: i2c@0 {
  270. #address-cells = <1>;
  271. #size-cells = <0>;
  272. reg = <0>;
  273. };
  274. imux25: i2c@1 {
  275. #address-cells = <1>;
  276. #size-cells = <0>;
  277. reg = <1>;
  278. };
  279. imux26: i2c@2 {
  280. #address-cells = <1>;
  281. #size-cells = <0>;
  282. reg = <2>;
  283. };
  284. imux27: i2c@3 {
  285. #address-cells = <1>;
  286. #size-cells = <0>;
  287. reg = <3>;
  288. };
  289. };
  290. };
  291. imux18: i2c@2 {
  292. #address-cells = <1>;
  293. #size-cells = <0>;
  294. reg = <2>;
  295. ina230@45 {
  296. compatible = "ti,ina230";
  297. reg = <0x45>;
  298. };
  299. tmp421@48 {
  300. compatible = "ti,tmp75";
  301. reg = <0x48>;
  302. };
  303. tmp421@49 {
  304. compatible = "ti,tmp75";
  305. reg = <0x49>;
  306. };
  307. eeprom@50 {
  308. compatible = "atmel,24c64";
  309. reg = <0x50>;
  310. pagesize = <32>;
  311. };
  312. i2c-switch@73 {
  313. compatible = "nxp,pca9546";
  314. #address-cells = <1>;
  315. #size-cells = <0>;
  316. reg = <0x73>;
  317. imux28: i2c@0 {
  318. #address-cells = <1>;
  319. #size-cells = <0>;
  320. reg = <0>;
  321. };
  322. imux29: i2c@1 {
  323. #address-cells = <1>;
  324. #size-cells = <0>;
  325. reg = <1>;
  326. };
  327. imux30: i2c@2 {
  328. #address-cells = <1>;
  329. #size-cells = <0>;
  330. reg = <2>;
  331. };
  332. imux31: i2c@3 {
  333. #address-cells = <1>;
  334. #size-cells = <0>;
  335. reg = <3>;
  336. };
  337. };
  338. };
  339. imux19: i2c@3 {
  340. #address-cells = <1>;
  341. #size-cells = <0>;
  342. reg = <3>;
  343. i2c-switch@40 {
  344. compatible = "ti,ina230";
  345. reg = <0x40>;
  346. };
  347. i2c-switch@41 {
  348. compatible = "ti,ina230";
  349. reg = <0x41>;
  350. };
  351. i2c-switch@45 {
  352. compatible = "ti,ina230";
  353. reg = <0x45>;
  354. };
  355. };
  356. };
  357. };
  358. &i2c2 {
  359. status = "okay";
  360. // Mezz Management SMBus
  361. };
  362. &i2c3 {
  363. status = "okay";
  364. // SMBus to Board ID EEPROM
  365. };
  366. &i2c4 {
  367. status = "okay";
  368. // BMC Debug Header
  369. ipmb0@10 {
  370. compatible = "ipmb-dev";
  371. reg = <(0x10 | I2C_OWN_SLAVE_ADDRESS)>;
  372. i2c-protocol;
  373. };
  374. };
  375. &i2c5 {
  376. status = "okay";
  377. // CPU Voltage regulators
  378. regulator@48 {
  379. compatible = "infineon,pxe1610";
  380. reg = <0x48>;
  381. };
  382. regulator@4a {
  383. compatible = "infineon,pxe1610";
  384. reg = <0x4a>;
  385. };
  386. regulator@50 {
  387. compatible = "infineon,pxe1610";
  388. reg = <0x50>;
  389. };
  390. regulator@52 {
  391. compatible = "infineon,pxe1610";
  392. reg = <0x52>;
  393. };
  394. regulator@58 {
  395. compatible = "infineon,pxe1610";
  396. reg = <0x58>;
  397. };
  398. regulator@5a {
  399. compatible = "infineon,pxe1610";
  400. reg = <0x5a>;
  401. };
  402. regulator@68 {
  403. compatible = "infineon,pxe1610";
  404. reg = <0x68>;
  405. };
  406. regulator@70 {
  407. compatible = "infineon,pxe1610";
  408. reg = <0x70>;
  409. };
  410. regulator@72 {
  411. compatible = "infineon,pxe1610";
  412. reg = <0x72>;
  413. };
  414. };
  415. &i2c6 {
  416. status = "okay";
  417. tpm@20 {
  418. compatible = "infineon,slb9645tt";
  419. reg = <0x20>;
  420. };
  421. tmp421@4e {
  422. compatible = "ti,tmp421";
  423. reg = <0x4e>;
  424. };
  425. tmp421@4f {
  426. compatible = "ti,tmp421";
  427. reg = <0x4f>;
  428. };
  429. eeprom@54 {
  430. compatible = "atmel,24c64";
  431. reg = <0x54>;
  432. pagesize = <32>;
  433. };
  434. };
  435. &i2c7 {
  436. status = "okay";
  437. //HSC, AirMax Conn A
  438. adm1278@45 {
  439. compatible = "adm1275";
  440. reg = <0x45>;
  441. shunt-resistor-micro-ohms = <250>;
  442. };
  443. };
  444. &i2c8 {
  445. status = "okay";
  446. tmp421@1f {
  447. compatible = "ti,tmp421";
  448. reg = <0x1f>;
  449. };
  450. //Mezz Sensor SMBus
  451. };
  452. &i2c9 {
  453. status = "okay";
  454. //USB Debug Connector
  455. ipmb0@10 {
  456. compatible = "ipmb-dev";
  457. reg = <(0x10 | I2C_OWN_SLAVE_ADDRESS)>;
  458. i2c-protocol;
  459. };
  460. };
  461. &pwm_tacho {
  462. status = "okay";
  463. pinctrl-names = "default";
  464. pinctrl-0 = <&pinctrl_pwm0_default &pinctrl_pwm1_default>;
  465. fan@0 {
  466. reg = <0x00>;
  467. aspeed,fan-tach-ch = /bits/ 8 <0x00>;
  468. };
  469. fan@1 {
  470. reg = <0x01>;
  471. aspeed,fan-tach-ch = /bits/ 8 <0x02>;
  472. };
  473. };