armada-xp-linksys-mamba.dts 6.9 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241242243244245246247248249250251252253254255256257258259260261262263264265266267268269270271272273274275276277278279280281282283284285286287288289290291292293294295296297298299300301302303304305306307308309310311312313314315316317318319320321322323324325326327328329330331332333334335336337338339340341342343344345346347348349350351352353354355356357358359360361362363364365366367368369370371372373374375376377378379380381382383384385386387388389390391392393394395396397
  1. // SPDX-License-Identifier: (GPL-2.0 OR MIT)
  2. /*
  3. * Device Tree file for the Linksys WRT1900AC (Mamba).
  4. *
  5. * Note: this board is shipped with a new generation boot loader that
  6. * remaps internal registers at 0xf1000000. Therefore, if earlyprintk
  7. * is used, the CONFIG_DEBUG_MVEBU_UART0_ALTERNATE option should be
  8. * used.
  9. *
  10. * Copyright (C) 2014 Imre Kaloz <[email protected]>
  11. *
  12. * Based on armada-xp-axpwifiap.dts:
  13. *
  14. * Copyright (C) 2013 Marvell
  15. *
  16. * Thomas Petazzoni <[email protected]>
  17. */
  18. /dts-v1/;
  19. #include <dt-bindings/gpio/gpio.h>
  20. #include <dt-bindings/input/input.h>
  21. #include "armada-xp-mv78230.dtsi"
  22. / {
  23. model = "Linksys WRT1900AC";
  24. compatible = "linksys,mamba", "marvell,armadaxp-mv78230",
  25. "marvell,armadaxp", "marvell,armada-370-xp";
  26. chosen {
  27. bootargs = "console=ttyS0,115200";
  28. stdout-path = &uart0;
  29. };
  30. memory@0 {
  31. device_type = "memory";
  32. reg = <0x00000000 0x00000000 0x00000000 0x10000000>; /* 256MB */
  33. };
  34. soc {
  35. ranges = <MBUS_ID(0xf0, 0x01) 0 0 0xf1000000 0x100000
  36. MBUS_ID(0x01, 0x1d) 0 0 0xfff00000 0x100000
  37. MBUS_ID(0x09, 0x09) 0 0 0xf1100000 0x10000
  38. MBUS_ID(0x09, 0x05) 0 0 0xf1110000 0x10000
  39. MBUS_ID(0x0c, 0x04) 0 0 0xf1200000 0x100000>;
  40. internal-regs {
  41. rtc@10300 {
  42. /* No crystal connected to the internal RTC */
  43. status = "disabled";
  44. };
  45. /* J10: VCC, NC, RX, NC, TX, GND */
  46. serial@12000 {
  47. status = "okay";
  48. };
  49. sata@a0000 {
  50. nr-ports = <1>;
  51. status = "okay";
  52. };
  53. ethernet@70000 {
  54. pinctrl-0 = <&ge0_rgmii_pins>;
  55. pinctrl-names = "default";
  56. status = "okay";
  57. phy-mode = "rgmii-id";
  58. buffer-manager = <&bm>;
  59. bm,pool-long = <0>;
  60. bm,pool-short = <1>;
  61. fixed-link {
  62. speed = <1000>;
  63. full-duplex;
  64. };
  65. };
  66. ethernet@74000 {
  67. pinctrl-0 = <&ge1_rgmii_pins>;
  68. pinctrl-names = "default";
  69. status = "okay";
  70. phy-mode = "rgmii-id";
  71. buffer-manager = <&bm>;
  72. bm,pool-long = <2>;
  73. bm,pool-short = <3>;
  74. fixed-link {
  75. speed = <1000>;
  76. full-duplex;
  77. };
  78. };
  79. /* USB part of the eSATA/USB 2.0 port */
  80. usb@50000 {
  81. status = "okay";
  82. };
  83. i2c@11000 {
  84. status = "okay";
  85. clock-frequency = <100000>;
  86. tmp421@4c {
  87. compatible = "ti,tmp421";
  88. reg = <0x4c>;
  89. };
  90. tlc59116@68 {
  91. #address-cells = <1>;
  92. #size-cells = <0>;
  93. #gpio-cells = <2>;
  94. compatible = "ti,tlc59116";
  95. reg = <0x68>;
  96. wan_amber@0 {
  97. label = "mamba:amber:wan";
  98. reg = <0x0>;
  99. };
  100. wan_white@1 {
  101. label = "mamba:white:wan";
  102. reg = <0x1>;
  103. };
  104. wlan_2g@2 {
  105. label = "mamba:white:wlan_2g";
  106. reg = <0x2>;
  107. };
  108. wlan_5g@3 {
  109. label = "mamba:white:wlan_5g";
  110. reg = <0x3>;
  111. };
  112. esata@4 {
  113. label = "mamba:white:esata";
  114. reg = <0x4>;
  115. linux,default-trigger = "disk-activity";
  116. };
  117. usb2@5 {
  118. label = "mamba:white:usb2";
  119. reg = <0x5>;
  120. };
  121. usb3_1@6 {
  122. label = "mamba:white:usb3_1";
  123. reg = <0x6>;
  124. };
  125. usb3_2@7 {
  126. label = "mamba:white:usb3_2";
  127. reg = <0x7>;
  128. };
  129. wps_white@8 {
  130. label = "mamba:white:wps";
  131. reg = <0x8>;
  132. };
  133. wps_amber@9 {
  134. label = "mamba:amber:wps";
  135. reg = <0x9>;
  136. };
  137. };
  138. };
  139. bm@c8000 {
  140. status = "okay";
  141. };
  142. };
  143. bm-bppi {
  144. status = "okay";
  145. };
  146. };
  147. gpio-keys {
  148. compatible = "gpio-keys";
  149. pinctrl-0 = <&keys_pin>;
  150. pinctrl-names = "default";
  151. button-wps {
  152. label = "WPS";
  153. linux,code = <KEY_WPS_BUTTON>;
  154. gpios = <&gpio1 0 GPIO_ACTIVE_LOW>;
  155. };
  156. button-reset {
  157. label = "Factory Reset Button";
  158. linux,code = <KEY_RESTART>;
  159. gpios = <&gpio1 1 GPIO_ACTIVE_LOW>;
  160. };
  161. };
  162. gpio-leds {
  163. compatible = "gpio-leds";
  164. pinctrl-0 = <&power_led_pin>;
  165. pinctrl-names = "default";
  166. power {
  167. label = "mamba:white:power";
  168. gpios = <&gpio1 8 GPIO_ACTIVE_HIGH>;
  169. default-state = "on";
  170. };
  171. };
  172. pwm_fan {
  173. /* SUNON HA4010V4-0000-C99 */
  174. compatible = "pwm-fan";
  175. pwms = <&gpio0 24 4000>;
  176. };
  177. };
  178. &pciec {
  179. status = "okay";
  180. /* Etron EJ168 USB 3.0 controller */
  181. pcie@1,0 {
  182. /* Port 0, Lane 0 */
  183. status = "okay";
  184. };
  185. /* First mini-PCIe port */
  186. pcie@2,0 {
  187. /* Port 0, Lane 1 */
  188. status = "okay";
  189. };
  190. /* Second mini-PCIe port */
  191. pcie@3,0 {
  192. /* Port 0, Lane 3 */
  193. status = "okay";
  194. };
  195. };
  196. &pinctrl {
  197. keys_pin: keys-pin {
  198. marvell,pins = "mpp32", "mpp33";
  199. marvell,function = "gpio";
  200. };
  201. power_led_pin: power-led-pin {
  202. marvell,pins = "mpp40";
  203. marvell,function = "gpio";
  204. };
  205. gpio_fan_pin: gpio-fan-pin {
  206. marvell,pins = "mpp24";
  207. marvell,function = "gpio";
  208. };
  209. };
  210. &spi0 {
  211. status = "okay";
  212. flash@0 {
  213. #address-cells = <1>;
  214. #size-cells = <1>;
  215. compatible = "everspin,mr25h256";
  216. reg = <0>; /* Chip select 0 */
  217. spi-max-frequency = <40000000>;
  218. };
  219. };
  220. &mdio {
  221. status = "okay";
  222. switch@0 {
  223. compatible = "marvell,mv88e6085";
  224. #address-cells = <1>;
  225. #size-cells = <0>;
  226. reg = <0>;
  227. ports {
  228. #address-cells = <1>;
  229. #size-cells = <0>;
  230. port@0 {
  231. reg = <0>;
  232. label = "lan4";
  233. };
  234. port@1 {
  235. reg = <1>;
  236. label = "lan3";
  237. };
  238. port@2 {
  239. reg = <2>;
  240. label = "lan2";
  241. };
  242. port@3 {
  243. reg = <3>;
  244. label = "lan1";
  245. };
  246. port@4 {
  247. reg = <4>;
  248. label = "internet";
  249. };
  250. port@5 {
  251. reg = <5>;
  252. label = "cpu";
  253. ethernet = <&eth0>;
  254. fixed-link {
  255. speed = <1000>;
  256. full-duplex;
  257. };
  258. };
  259. };
  260. };
  261. };
  262. &nand_controller {
  263. status = "okay";
  264. nand@0 {
  265. reg = <0>;
  266. label = "pxa3xx_nand-0";
  267. nand-rb = <0>;
  268. marvell,nand-keep-config;
  269. nand-on-flash-bbt;
  270. nand-ecc-strength = <4>;
  271. nand-ecc-step-size = <512>;
  272. partitions {
  273. compatible = "fixed-partitions";
  274. #address-cells = <1>;
  275. #size-cells = <1>;
  276. partition@0 {
  277. label = "u-boot";
  278. reg = <0x0000000 0x100000>; /* 1MB */
  279. read-only;
  280. };
  281. partition@100000 {
  282. label = "u_env";
  283. reg = <0x100000 0x40000>; /* 256KB */
  284. };
  285. partition@140000 {
  286. label = "s_env";
  287. reg = <0x140000 0x40000>; /* 256KB */
  288. };
  289. partition@900000 {
  290. label = "devinfo";
  291. reg = <0x900000 0x100000>; /* 1MB */
  292. read-only;
  293. };
  294. /* kernel1 overlaps with rootfs1 by design */
  295. partition@a00000 {
  296. label = "kernel1";
  297. reg = <0xa00000 0x2800000>; /* 40MB */
  298. };
  299. partition@d00000 {
  300. label = "rootfs1";
  301. reg = <0xd00000 0x2500000>; /* 37MB */
  302. };
  303. /* kernel2 overlaps with rootfs2 by design */
  304. partition@3200000 {
  305. label = "kernel2";
  306. reg = <0x3200000 0x2800000>; /* 40MB */
  307. };
  308. partition@3500000 {
  309. label = "rootfs2";
  310. reg = <0x3500000 0x2500000>; /* 37MB */
  311. };
  312. /*
  313. * 38MB, last MB is for the BBT, not writable
  314. */
  315. partition@5a00000 {
  316. label = "syscfg";
  317. reg = <0x5a00000 0x2600000>;
  318. };
  319. /*
  320. * Unused area between "s_env" and "devinfo".
  321. * Moved here because otherwise the renumbered
  322. * partitions would break the bootloader
  323. * supplied bootargs
  324. */
  325. partition@180000 {
  326. label = "unused_area";
  327. reg = <0x180000 0x780000>; /* 7.5MB */
  328. };
  329. };
  330. };
  331. };