armada-xp-crs305-1g-4s.dtsi 2.1 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104
  1. // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
  2. /*
  3. * Device Tree file for CRS305-1G-4S board
  4. *
  5. * Copyright (C) 2016 Allied Telesis Labs
  6. * Copyright (C) 2020 Sartura Ltd.
  7. *
  8. * Based on armada-xp-db.dts
  9. *
  10. * Note: this Device Tree assumes that the bootloader has remapped the
  11. * internal registers to 0xf1000000 (instead of the default
  12. * 0xd0000000). The 0xf1000000 is the default used by the recent,
  13. * DT-capable, U-Boot bootloaders provided by Marvell. Some earlier
  14. * boards were delivered with an older version of the bootloader that
  15. * left internal registers mapped at 0xd0000000. If you are in this
  16. * situation, you should either update your bootloader (preferred
  17. * solution) or the below Device Tree should be adjusted.
  18. */
  19. /dts-v1/;
  20. #include "armada-xp-98dx3236.dtsi"
  21. / {
  22. model = "CRS305-1G-4S+";
  23. compatible = "mikrotik,crs305-1g-4s", "marvell,armadaxp-98dx3236", "marvell,armada-370-xp";
  24. chosen {
  25. bootargs = "console=ttyS0,115200 earlyprintk";
  26. };
  27. memory {
  28. device_type = "memory";
  29. reg = <0 0x00000000 0 0x20000000>; /* 512 MB */
  30. };
  31. };
  32. &L2 {
  33. arm,parity-enable;
  34. marvell,ecc-enable;
  35. };
  36. &devbus_bootcs {
  37. status = "okay";
  38. /* Device Bus parameters are required */
  39. /* Read parameters */
  40. devbus,bus-width = <16>;
  41. devbus,turn-off-ps = <60000>;
  42. devbus,badr-skew-ps = <0>;
  43. devbus,acc-first-ps = <124000>;
  44. devbus,acc-next-ps = <248000>;
  45. devbus,rd-setup-ps = <0>;
  46. devbus,rd-hold-ps = <0>;
  47. /* Write parameters */
  48. devbus,sync-enable = <0>;
  49. devbus,wr-high-ps = <60000>;
  50. devbus,wr-low-ps = <60000>;
  51. devbus,ale-wr-ps = <60000>;
  52. };
  53. &uart0 {
  54. status = "okay";
  55. };
  56. &uart1 {
  57. status = "okay";
  58. };
  59. &i2c0 {
  60. clock-frequency = <100000>;
  61. status = "okay";
  62. };
  63. &usb0 {
  64. status = "okay";
  65. };
  66. &spi0 {
  67. status = "okay";
  68. flash@0 {
  69. #address-cells = <1>;
  70. #size-cells = <1>;
  71. compatible = "jedec,spi-nor";
  72. reg = <0>; /* Chip select 0 */
  73. spi-max-frequency = <108000000>;
  74. m25p,fast-read;
  75. partition@u-boot {
  76. reg = <0x00000000 0x001f0000>;
  77. label = "u-boot";
  78. };
  79. partition@u-boot-env {
  80. reg = <0x001f0000 0x00010000>;
  81. label = "u-boot-env";
  82. };
  83. partition@ubi1 {
  84. reg = <0x00200000 0x00e00000>;
  85. label = "ubi1";
  86. };
  87. };
  88. };