armada-370-dlink-dns327l.dts 6.1 KB

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  1. // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
  2. /*
  3. * Device Tree file for D-Link DNS-327L
  4. *
  5. * Copyright (C) 2015, Andrew Andrianov <[email protected]>
  6. */
  7. /* Remaining unsolved:
  8. * There's still some unknown device on i2c address 0x13
  9. */
  10. /dts-v1/;
  11. #include <dt-bindings/input/input.h>
  12. #include <dt-bindings/gpio/gpio.h>
  13. #include "armada-370.dtsi"
  14. / {
  15. model = "D-Link DNS-327L";
  16. compatible = "dlink,dns327l",
  17. "marvell,armada370",
  18. "marvell,armada-370-xp";
  19. chosen {
  20. stdout-path = &uart0;
  21. };
  22. memory@0 {
  23. device_type = "memory";
  24. reg = <0x00000000 0x20000000>; /* 512 MiB */
  25. };
  26. soc {
  27. ranges = <MBUS_ID(0xf0, 0x01) 0 0xd0000000 0x100000
  28. MBUS_ID(0x01, 0xe0) 0 0xfff00000 0x100000
  29. MBUS_ID(0x09, 0x01) 0 0xf1100000 0x10000>;
  30. internal-regs {
  31. sata@a0000 {
  32. nr-ports = <2>;
  33. status = "okay";
  34. };
  35. usb@50000 {
  36. status = "okay";
  37. };
  38. };
  39. };
  40. gpio-keys {
  41. compatible = "gpio-keys";
  42. pinctrl-0 = <
  43. &backup_button_pin
  44. &power_button_pin
  45. &reset_button_pin>;
  46. pinctrl-names = "default";
  47. power-button {
  48. label = "Power Button";
  49. linux,code = <KEY_POWER>;
  50. gpios = <&gpio2 1 GPIO_ACTIVE_LOW>;
  51. };
  52. backup-button {
  53. label = "Backup Button";
  54. linux,code = <KEY_COPY>;
  55. gpios = <&gpio1 31 GPIO_ACTIVE_LOW>;
  56. };
  57. reset-button {
  58. label = "Reset Button";
  59. linux,code = <KEY_RESTART>;
  60. gpios = <&gpio2 0 GPIO_ACTIVE_LOW>;
  61. };
  62. };
  63. gpio-leds {
  64. compatible = "gpio-leds";
  65. pinctrl-0 = <
  66. &sata_l_amber_pin
  67. &sata_r_amber_pin
  68. &backup_led_pin
  69. /* Ensure these are managed by hardware */
  70. &sata_l_white_pin
  71. &sata_r_white_pin>;
  72. pinctrl-names = "default";
  73. sata-r-amber-pin {
  74. label = "dns327l:amber:sata-r";
  75. gpios = <&gpio1 20 GPIO_ACTIVE_HIGH>;
  76. default-state = "keep";
  77. };
  78. sata-l-amber-pin {
  79. label = "dns327l:amber:sata-l";
  80. gpios = <&gpio1 21 GPIO_ACTIVE_HIGH>;
  81. default-state = "keep";
  82. };
  83. backup-led-pin {
  84. label = "dns327l:white:usb";
  85. gpios = <&gpio1 29 GPIO_ACTIVE_HIGH>;
  86. default-state = "keep";
  87. };
  88. };
  89. regulators {
  90. compatible = "simple-bus";
  91. #address-cells = <1>;
  92. #size-cells = <0>;
  93. usb_power: regulator@1 {
  94. compatible = "regulator-fixed";
  95. reg = <1>;
  96. pinctrl-0 = <&xhci_pwr_pin>;
  97. pinctrl-names = "default";
  98. regulator-name = "USB3.0 Port Power";
  99. regulator-min-microvolt = <5000000>;
  100. regulator-max-microvolt = <5000000>;
  101. enable-active-high;
  102. regulator-boot-on;
  103. regulator-always-on;
  104. gpio = <&gpio0 13 GPIO_ACTIVE_HIGH>;
  105. };
  106. sata_r_power: regulator@2 {
  107. compatible = "regulator-fixed";
  108. reg = <2>;
  109. pinctrl-0 = <&sata_r_pwr_pin>;
  110. pinctrl-names = "default";
  111. regulator-name = "SATA-R Power";
  112. regulator-min-microvolt = <5000000>;
  113. regulator-max-microvolt = <5000000>;
  114. startup-delay-us = <2000000>;
  115. enable-active-high;
  116. regulator-always-on;
  117. regulator-boot-on;
  118. gpio = <&gpio1 22 GPIO_ACTIVE_HIGH>;
  119. };
  120. sata_l_power: regulator@3 {
  121. compatible = "regulator-fixed";
  122. reg = <3>;
  123. pinctrl-0 = <&sata_l_pwr_pin>;
  124. pinctrl-names = "default";
  125. regulator-name = "SATA-L Power";
  126. regulator-min-microvolt = <5000000>;
  127. regulator-max-microvolt = <5000000>;
  128. startup-delay-us = <4000000>;
  129. enable-active-high;
  130. regulator-always-on;
  131. regulator-boot-on;
  132. gpio = <&gpio1 24 GPIO_ACTIVE_HIGH>;
  133. };
  134. };
  135. };
  136. &pciec {
  137. status = "okay";
  138. pcie@1,0 {
  139. /* Port 0, Lane 0 */
  140. status = "okay";
  141. };
  142. pcie@2,0 {
  143. /* Port 1, Lane 0 */
  144. status = "okay";
  145. };
  146. };
  147. &pinctrl {
  148. sata_l_white_pin: sata-l-white-pin {
  149. marvell,pins = "mpp57";
  150. marvell,function = "sata0";
  151. };
  152. sata_r_white_pin: sata-r-white-pin {
  153. marvell,pins = "mpp55";
  154. marvell,function = "sata1";
  155. };
  156. sata_r_amber_pin: sata-r-amber-pin {
  157. marvell,pins = "mpp52";
  158. marvell,function = "gpio";
  159. };
  160. sata_l_amber_pin: sata-l-amber-pin {
  161. marvell,pins = "mpp53";
  162. marvell,function = "gpio";
  163. };
  164. backup_led_pin: backup-led-pin {
  165. marvell,pins = "mpp61";
  166. marvell,function = "gpo";
  167. };
  168. xhci_pwr_pin: xhci-pwr-pin {
  169. marvell,pins = "mpp13";
  170. marvell,function = "gpio";
  171. };
  172. sata_r_pwr_pin: sata-r-pwr-pin {
  173. marvell,pins = "mpp54";
  174. marvell,function = "gpio";
  175. };
  176. sata_l_pwr_pin: sata-l-pwr-pin {
  177. marvell,pins = "mpp56";
  178. marvell,function = "gpio";
  179. };
  180. uart1_pins: uart1-pins {
  181. marvell,pins = "mpp60", "mpp61";
  182. marvell,function = "uart1";
  183. };
  184. power_button_pin: power-button-pin {
  185. marvell,pins = "mpp65";
  186. marvell,function = "gpio";
  187. };
  188. backup_button_pin: backup-button-pin {
  189. marvell,pins = "mpp63";
  190. marvell,function = "gpio";
  191. };
  192. reset_button_pin: reset-button-pin {
  193. marvell,pins = "mpp64";
  194. marvell,function = "gpio";
  195. };
  196. };
  197. /* Serial console */
  198. &uart0 {
  199. status = "okay";
  200. };
  201. /* Connected to Weltrend MCU */
  202. &uart1 {
  203. pinctrl-0 = <&uart1_pins>;
  204. pinctrl-names = "default";
  205. status = "okay";
  206. };
  207. &mdio {
  208. phy0: ethernet-phy@0 { /* Marvell 88E1318 */
  209. reg = <0>;
  210. marvell,reg-init = <0x2 0x19 0x0 0x0077>,
  211. <0x2 0x18 0x0 0x5747>;
  212. };
  213. };
  214. &eth1 {
  215. phy = <&phy0>;
  216. phy-mode = "rgmii-id";
  217. status = "okay";
  218. };
  219. &i2c0 {
  220. compatible = "marvell,mv64xxx-i2c";
  221. clock-frequency = <100000>;
  222. status = "okay";
  223. };
  224. &nand_controller {
  225. status = "okay";
  226. nand@0 {
  227. reg = <0>;
  228. label = "pxa3xx_nand-0";
  229. nand-rb = <0>;
  230. marvell,nand-keep-config;
  231. nand-on-flash-bbt;
  232. nand-ecc-strength = <4>;
  233. nand-ecc-step-size = <512>;
  234. partitions {
  235. compatible = "fixed-partitions";
  236. #address-cells = <1>;
  237. #size-cells = <1>;
  238. partition@0 {
  239. label = "u-boot";
  240. /* 1.0 MiB */
  241. reg = <0x0000000 0x100000>;
  242. read-only;
  243. };
  244. partition@100000 {
  245. label = "u-boot-env";
  246. /* 128 KiB */
  247. reg = <0x100000 0x20000>;
  248. read-only;
  249. };
  250. partition@120000 {
  251. label = "uImage";
  252. /* 7 MiB */
  253. reg = <0x120000 0x700000>;
  254. };
  255. partition@820000 {
  256. label = "ubifs";
  257. /* ~ 84 MiB */
  258. reg = <0x820000 0x54e0000>;
  259. };
  260. /* Hardcoded into stock bootloader */
  261. partition@5d00000 {
  262. label = "failsafe-uImage";
  263. /* 5 MiB */
  264. reg = <0x5d00000 0x500000>;
  265. };
  266. partition@6200000 {
  267. label = "failsafe-fs";
  268. /* 29 MiB */
  269. reg = <0x6200000 0x1d00000>;
  270. };
  271. partition@7f00000 {
  272. label = "bbt";
  273. /* 1 MiB for BBT */
  274. reg = <0x7f00000 0x100000>;
  275. };
  276. };
  277. };
  278. };