am43x-epos-evm.dts 31 KB

12345678910111213141516171819202122232425262728293031323334353637383940414243444546474849505152535455565758596061626364656667686970717273747576777879808182838485868788899091929394959697989910010110210310410510610710810911011111211311411511611711811912012112212312412512612712812913013113213313413513613713813914014114214314414514614714814915015115215315415515615715815916016116216316416516616716816917017117217317417517617717817918018118218318418518618718818919019119219319419519619719819920020120220320420520620720820921021121221321421521621721821922022122222322422522622722822923023123223323423523623723823924024124224324424524624724824925025125225325425525625725825926026126226326426526626726826927027127227327427527627727827928028128228328428528628728828929029129229329429529629729829930030130230330430530630730830931031131231331431531631731831932032132232332432532632732832933033133233333433533633733833934034134234334434534634734834935035135235335435535635735835936036136236336436536636736836937037137237337437537637737837938038138238338438538638738838939039139239339439539639739839940040140240340440540640740840941041141241341441541641741841942042142242342442542642742842943043143243343443543643743843944044144244344444544644744844945045145245345445545645745845946046146246346446546646746846947047147247347447547647747847948048148248348448548648748848949049149249349449549649749849950050150250350450550650750850951051151251351451551651751851952052152252352452552652752852953053153253353453553653753853954054154254354454554654754854955055155255355455555655755855956056156256356456556656756856957057157257357457557657757857958058158258358458558658758858959059159259359459559659759859960060160260360460560660760860961061161261361461561661761861962062162262362462562662762862963063163263363463563663763863964064164264364464564664764864965065165265365465565665765865966066166266366466566666766866967067167267367467567667767867968068168268368468568668768868969069169269369469569669769869970070170270370470570670770870971071171271371471571671771871972072172272372472572672772872973073173273373473573673773873974074174274374474574674774874975075175275375475575675775875976076176276376476576676776876977077177277377477577677777877978078178278378478578678778878979079179279379479579679779879980080180280380480580680780880981081181281381481581681781881982082182282382482582682782882983083183283383483583683783883984084184284384484584684784884985085185285385485585685785885986086186286386486586686786886987087187287387487587687787887988088188288388488588688788888989089189289389489589689789889990090190290390490590690790890991091191291391491591691791891992092192292392492592692792892993093193293393493593693793893994094194294394494594694794894995095195295395495595695795895996096196296396496596696796896997097197297397497597697797897998098198298398498598698798898999099199299399499599699799899910001001100210031004100510061007100810091010101110121013101410151016101710181019102010211022102310241025102610271028
  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. * Copyright (C) 2013 Texas Instruments Incorporated - https://www.ti.com/
  4. */
  5. /* AM43x EPOS EVM */
  6. /dts-v1/;
  7. #include "am4372.dtsi"
  8. #include <dt-bindings/pinctrl/am43xx.h>
  9. #include <dt-bindings/gpio/gpio.h>
  10. #include <dt-bindings/pwm/pwm.h>
  11. #include <dt-bindings/sound/tlv320aic31xx.h>
  12. / {
  13. model = "TI AM43x EPOS EVM";
  14. compatible = "ti,am43x-epos-evm","ti,am438x","ti,am43";
  15. aliases {
  16. display0 = &lcd0;
  17. };
  18. chosen {
  19. stdout-path = &uart0;
  20. };
  21. vmmcsd_fixed: fixedregulator-sd {
  22. compatible = "regulator-fixed";
  23. regulator-name = "vmmcsd_fixed";
  24. regulator-min-microvolt = <3300000>;
  25. regulator-max-microvolt = <3300000>;
  26. enable-active-high;
  27. };
  28. vbat: fixedregulator0 {
  29. compatible = "regulator-fixed";
  30. regulator-name = "vbat";
  31. regulator-min-microvolt = <5000000>;
  32. regulator-max-microvolt = <5000000>;
  33. regulator-boot-on;
  34. };
  35. lcd0: display {
  36. compatible = "osddisplays,osd070t1718-19ts", "panel-dpi";
  37. label = "lcd";
  38. backlight = <&lcd_bl>;
  39. port {
  40. lcd_in: endpoint {
  41. remote-endpoint = <&dpi_out>;
  42. };
  43. };
  44. };
  45. matrix_keypad: matrix_keypad0 {
  46. compatible = "gpio-matrix-keypad";
  47. debounce-delay-ms = <5>;
  48. col-scan-delay-us = <2>;
  49. pinctrl-names = "default", "sleep";
  50. pinctrl-0 = <&matrix_keypad_default>;
  51. pinctrl-1 = <&matrix_keypad_sleep>;
  52. wakeup-source;
  53. row-gpios = <&gpio0 12 GPIO_ACTIVE_HIGH /* Bank0, pin12 */
  54. &gpio0 13 GPIO_ACTIVE_HIGH /* Bank0, pin13 */
  55. &gpio0 14 GPIO_ACTIVE_HIGH /* Bank0, pin14 */
  56. &gpio0 15 GPIO_ACTIVE_HIGH>; /* Bank0, pin15 */
  57. col-gpios = <&gpio3 9 GPIO_ACTIVE_HIGH /* Bank3, pin9 */
  58. &gpio3 10 GPIO_ACTIVE_HIGH /* Bank3, pin10 */
  59. &gpio2 18 GPIO_ACTIVE_HIGH /* Bank2, pin18 */
  60. &gpio2 19 GPIO_ACTIVE_HIGH>; /* Bank2, pin19 */
  61. linux,keymap = <0x00000201 /* P1 */
  62. 0x01000204 /* P4 */
  63. 0x02000207 /* P7 */
  64. 0x0300020a /* NUMERIC_STAR */
  65. 0x00010202 /* P2 */
  66. 0x01010205 /* P5 */
  67. 0x02010208 /* P8 */
  68. 0x03010200 /* P0 */
  69. 0x00020203 /* P3 */
  70. 0x01020206 /* P6 */
  71. 0x02020209 /* P9 */
  72. 0x0302020b /* NUMERIC_POUND */
  73. 0x00030067 /* UP */
  74. 0x0103006a /* RIGHT */
  75. 0x0203006c /* DOWN */
  76. 0x03030069>; /* LEFT */
  77. };
  78. lcd_bl: backlight {
  79. compatible = "pwm-backlight";
  80. pwms = <&ecap0 0 50000 PWM_POLARITY_INVERTED>;
  81. brightness-levels = <0 51 53 56 62 75 101 152 255>;
  82. default-brightness-level = <8>;
  83. };
  84. sound0: sound0 {
  85. compatible = "simple-audio-card";
  86. simple-audio-card,name = "AM43-EPOS-EVM";
  87. simple-audio-card,widgets =
  88. "Microphone", "Microphone Jack",
  89. "Headphone", "Headphone Jack",
  90. "Speaker", "Speaker";
  91. simple-audio-card,routing =
  92. "MIC1LP", "Microphone Jack",
  93. "MIC1RP", "Microphone Jack",
  94. "MIC1LP", "MICBIAS",
  95. "MIC1RP", "MICBIAS",
  96. "Headphone Jack", "HPL",
  97. "Headphone Jack", "HPR",
  98. "Speaker", "SPL",
  99. "Speaker", "SPR";
  100. simple-audio-card,format = "dsp_b";
  101. simple-audio-card,bitclock-master = <&sound0_master>;
  102. simple-audio-card,frame-master = <&sound0_master>;
  103. simple-audio-card,bitclock-inversion;
  104. simple-audio-card,cpu {
  105. sound-dai = <&mcasp1>;
  106. system-clock-frequency = <12000000>;
  107. };
  108. sound0_master: simple-audio-card,codec {
  109. sound-dai = <&tlv320aic3111>;
  110. system-clock-frequency = <12000000>;
  111. };
  112. };
  113. audio_mstrclk: clock {
  114. compatible = "fixed-clock";
  115. #clock-cells = <0>;
  116. clock-frequency = <12000000>;
  117. };
  118. };
  119. &am43xx_pinmux {
  120. pinctrl-names = "default";
  121. pinctrl-0 = <&unused_pins>;
  122. unused_pins: unused_pins {
  123. pinctrl-single,pins = <
  124. AM4372_IOPAD(0x848, DS0_PIN_OUTPUT_PULLUP | PIN_OUTPUT_PULLUP | MUX_MODE7)
  125. AM4372_IOPAD(0x850, DS0_PIN_INPUT | PIN_INPUT_PULLDOWN | MUX_MODE7)
  126. AM4372_IOPAD(0x858, DS0_PIN_INPUT | PIN_INPUT_PULLDOWN | MUX_MODE7)
  127. AM4372_IOPAD(0x860, DS0_PIN_INPUT | PIN_INPUT_PULLDOWN | MUX_MODE7)
  128. AM4372_IOPAD(0x864, DS0_PIN_INPUT | PIN_INPUT_PULLDOWN | MUX_MODE7)
  129. AM4372_IOPAD(0x868, DS0_PIN_INPUT | PIN_INPUT_PULLDOWN | MUX_MODE7)
  130. AM4372_IOPAD(0x86c, DS0_PIN_INPUT | PIN_INPUT_PULLDOWN | MUX_MODE7)
  131. AM4372_IOPAD(0x878, DS0_PIN_OUTPUT_PULLUP | PIN_OUTPUT_PULLUP | MUX_MODE7)
  132. AM4372_IOPAD(0x908, DS0_PIN_INPUT_PULLDOWN | PIN_INPUT_PULLDOWN | MUX_MODE7)
  133. AM4372_IOPAD(0x91c, DS0_PIN_OUTPUT_PULLDOWN | PIN_OUTPUT_PULLDOWN | MUX_MODE7)
  134. AM4372_IOPAD(0x920, DS0_PIN_INPUT | PIN_INPUT_PULLDOWN | MUX_MODE7)
  135. AM4372_IOPAD(0x9e0, DS0_PIN_INPUT_PULLDOWN | PIN_INPUT_PULLDOWN | MUX_MODE7)
  136. AM4372_IOPAD(0xA0c, DS0_PIN_OUTPUT_PULLDOWN | PIN_OUTPUT_PULLDOWN | MUX_MODE7)
  137. AM4372_IOPAD(0xA38, DS0_PIN_INPUT | PIN_INPUT_PULLDOWN | MUX_MODE7)
  138. AM4372_IOPAD(0xA3c, DS0_PIN_INPUT | PIN_INPUT_PULLDOWN | MUX_MODE7)
  139. AM4372_IOPAD(0xA40, DS0_PIN_INPUT | PIN_INPUT_PULLDOWN | MUX_MODE7)
  140. AM4372_IOPAD(0xA44, DS0_PIN_INPUT | PIN_INPUT_PULLDOWN | MUX_MODE7)
  141. AM4372_IOPAD(0xA48, DS0_PIN_INPUT | PIN_INPUT_PULLDOWN | MUX_MODE7)
  142. AM4372_IOPAD(0xA4c, DS0_PIN_INPUT | PIN_INPUT_PULLDOWN | MUX_MODE7)
  143. AM4372_IOPAD(0xA50, DS0_PIN_INPUT | PIN_INPUT_PULLDOWN | MUX_MODE7)
  144. AM4372_IOPAD(0xA54, DS0_PIN_INPUT | PIN_INPUT_PULLDOWN | MUX_MODE7)
  145. AM4372_IOPAD(0xA58, DS0_PIN_INPUT | PIN_INPUT_PULLDOWN | MUX_MODE7)
  146. AM4372_IOPAD(0xA5c, DS0_PIN_INPUT | PIN_INPUT_PULLDOWN | MUX_MODE7)
  147. AM4372_IOPAD(0xA60, DS0_PIN_INPUT | PIN_INPUT_PULLDOWN | MUX_MODE7)
  148. AM4372_IOPAD(0xA64, DS0_PIN_OUTPUT_PULLUP | PIN_OUTPUT_PULLUP | MUX_MODE7)
  149. AM4372_IOPAD(0xA68, DS0_PIN_INPUT | PIN_INPUT_PULLDOWN | MUX_MODE7)
  150. AM4372_IOPAD(0xA6C, DS0_PIN_INPUT | PIN_INPUT_PULLDOWN | MUX_MODE7)
  151. AM4372_IOPAD(0xA74, DS0_PIN_INPUT_PULLDOWN | PIN_INPUT_PULLDOWN | MUX_MODE7)
  152. AM4372_IOPAD(0xA78, DS0_PIN_INPUT | PIN_INPUT_PULLDOWN | MUX_MODE7)
  153. >;
  154. };
  155. cpsw_default: cpsw_default {
  156. pinctrl-single,pins = <
  157. /* Slave 1 */
  158. AM4372_IOPAD(0x90c, PIN_INPUT_PULLDOWN | MUX_MODE1) /* mii1_crs.rmii1_crs */
  159. AM4372_IOPAD(0x910, PIN_INPUT_PULLDOWN | MUX_MODE1) /* mii1_rxerr.rmii1_rxerr */
  160. AM4372_IOPAD(0x914, PIN_OUTPUT_PULLDOWN | MUX_MODE1) /* mii1_txen.rmii1_txen */
  161. AM4372_IOPAD(0x918, PIN_INPUT_PULLDOWN | MUX_MODE1) /* mii1_rxdv.rmii1_rxdv */
  162. AM4372_IOPAD(0x924, PIN_OUTPUT_PULLDOWN | MUX_MODE1) /* mii1_txd1.rmii1_txd1 */
  163. AM4372_IOPAD(0x928, PIN_OUTPUT_PULLDOWN | MUX_MODE1) /* mii1_txd0.rmii1_txd0 */
  164. AM4372_IOPAD(0x93c, PIN_INPUT_PULLDOWN | MUX_MODE1) /* mii1_rxd1.rmii1_rxd1 */
  165. AM4372_IOPAD(0x940, PIN_INPUT_PULLDOWN | MUX_MODE1) /* mii1_rxd0.rmii1_rxd0 */
  166. AM4372_IOPAD(0x944, PIN_INPUT_PULLDOWN | MUX_MODE0) /* rmii1_refclk.rmii1_refclk */
  167. >;
  168. };
  169. cpsw_sleep: cpsw_sleep {
  170. pinctrl-single,pins = <
  171. /* Slave 1 reset value */
  172. AM4372_IOPAD(0x90c, PIN_INPUT_PULLDOWN | MUX_MODE7)
  173. AM4372_IOPAD(0x910, PIN_INPUT_PULLDOWN | MUX_MODE7)
  174. AM4372_IOPAD(0x914, PIN_INPUT_PULLDOWN | MUX_MODE7)
  175. AM4372_IOPAD(0x918, PIN_INPUT_PULLDOWN | MUX_MODE7)
  176. AM4372_IOPAD(0x924, PIN_INPUT_PULLDOWN | MUX_MODE7)
  177. AM4372_IOPAD(0x928, PIN_INPUT_PULLDOWN | MUX_MODE7)
  178. AM4372_IOPAD(0x93c, PIN_INPUT_PULLDOWN | MUX_MODE7)
  179. AM4372_IOPAD(0x940, PIN_INPUT_PULLDOWN | MUX_MODE7)
  180. AM4372_IOPAD(0x944, PIN_INPUT_PULLDOWN | MUX_MODE7)
  181. >;
  182. };
  183. davinci_mdio_default: davinci_mdio_default {
  184. pinctrl-single,pins = <
  185. /* MDIO */
  186. AM4372_IOPAD(0x948, PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE0) /* mdio_data.mdio_data */
  187. AM4372_IOPAD(0x94c, PIN_OUTPUT_PULLUP | MUX_MODE0) /* mdio_clk.mdio_clk */
  188. >;
  189. };
  190. davinci_mdio_sleep: davinci_mdio_sleep {
  191. pinctrl-single,pins = <
  192. /* MDIO reset value */
  193. AM4372_IOPAD(0x948, PIN_INPUT_PULLDOWN | MUX_MODE7)
  194. AM4372_IOPAD(0x94c, PIN_INPUT_PULLDOWN | MUX_MODE7)
  195. >;
  196. };
  197. i2c0_pins: pinmux_i2c0_pins {
  198. pinctrl-single,pins = <
  199. AM4372_IOPAD(0x988, PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE0) /* i2c0_sda.i2c0_sda */
  200. AM4372_IOPAD(0x98c, PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE0) /* i2c0_scl.i2c0_scl */
  201. >;
  202. };
  203. nand_flash_x8_default: nand_flash_x8_default {
  204. pinctrl-single,pins = <
  205. AM4372_IOPAD(0x840, PIN_OUTPUT_PULLDOWN | MUX_MODE7) /* gpmc_a0.SELQSPIorNAND/GPIO */
  206. AM4372_IOPAD(0x800, PIN_INPUT_PULLDOWN | MUX_MODE0) /* gpmc_ad0.gpmc_ad0 */
  207. AM4372_IOPAD(0x804, PIN_INPUT_PULLDOWN | MUX_MODE0) /* gpmc_ad1.gpmc_ad1 */
  208. AM4372_IOPAD(0x808, PIN_INPUT_PULLDOWN | MUX_MODE0) /* gpmc_ad2.gpmc_ad2 */
  209. AM4372_IOPAD(0x80c, PIN_INPUT_PULLDOWN | MUX_MODE0) /* gpmc_ad3.gpmc_ad3 */
  210. AM4372_IOPAD(0x810, PIN_INPUT_PULLDOWN | MUX_MODE0) /* gpmc_ad4.gpmc_ad4 */
  211. AM4372_IOPAD(0x814, PIN_INPUT_PULLDOWN | MUX_MODE0) /* gpmc_ad5.gpmc_ad5 */
  212. AM4372_IOPAD(0x818, PIN_INPUT_PULLDOWN | MUX_MODE0) /* gpmc_ad6.gpmc_ad6 */
  213. AM4372_IOPAD(0x81c, PIN_INPUT_PULLDOWN | MUX_MODE0) /* gpmc_ad7.gpmc_ad7 */
  214. AM4372_IOPAD(0x870, PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_wait0.gpmc_wait0 */
  215. AM4372_IOPAD(0x874, PIN_OUTPUT_PULLUP | MUX_MODE7) /* gpmc_wpn.gpmc_wpn */
  216. AM4372_IOPAD(0x87c, PIN_OUTPUT | MUX_MODE0) /* gpmc_csn0.gpmc_csn0 */
  217. AM4372_IOPAD(0x890, PIN_OUTPUT | MUX_MODE0) /* gpmc_advn_ale.gpmc_advn_ale */
  218. AM4372_IOPAD(0x894, PIN_OUTPUT | MUX_MODE0) /* gpmc_oen_ren.gpmc_oen_ren */
  219. AM4372_IOPAD(0x898, PIN_OUTPUT | MUX_MODE0) /* gpmc_wen.gpmc_wen */
  220. AM4372_IOPAD(0x89c, PIN_OUTPUT | MUX_MODE0) /* gpmc_be0n_cle.gpmc_be0n_cle */
  221. >;
  222. };
  223. nand_flash_x8_sleep: nand_flash_x8_sleep {
  224. pinctrl-single,pins = <
  225. AM4372_IOPAD(0x840, DS0_PIN_OUTPUT_PULLDOWN | MUX_MODE7)
  226. AM4372_IOPAD(0x800, DS0_PIN_OUTPUT_PULLDOWN | MUX_MODE7)
  227. AM4372_IOPAD(0x804, DS0_PIN_OUTPUT_PULLDOWN | MUX_MODE7)
  228. AM4372_IOPAD(0x808, DS0_PIN_OUTPUT_PULLDOWN | MUX_MODE7)
  229. AM4372_IOPAD(0x80c, DS0_PIN_OUTPUT_PULLDOWN | MUX_MODE7)
  230. AM4372_IOPAD(0x810, DS0_PIN_OUTPUT_PULLDOWN | MUX_MODE7)
  231. AM4372_IOPAD(0x814, DS0_PIN_OUTPUT_PULLDOWN | MUX_MODE7)
  232. AM4372_IOPAD(0x818, DS0_PIN_OUTPUT_PULLDOWN | MUX_MODE7)
  233. AM4372_IOPAD(0x81c, DS0_PIN_OUTPUT_PULLDOWN | MUX_MODE7)
  234. AM4372_IOPAD(0x870, DS0_PIN_OUTPUT_PULLUP | MUX_MODE7)
  235. AM4372_IOPAD(0x874, DS0_PIN_OUTPUT_PULLUP | MUX_MODE7)
  236. AM4372_IOPAD(0x87c, DS0_PIN_OUTPUT_PULLUP | MUX_MODE7)
  237. AM4372_IOPAD(0x890, DS0_PIN_OUTPUT_PULLUP | MUX_MODE7)
  238. AM4372_IOPAD(0x894, DS0_PIN_OUTPUT_PULLUP | MUX_MODE7)
  239. AM4372_IOPAD(0x898, DS0_PIN_OUTPUT_PULLUP | MUX_MODE7)
  240. AM4372_IOPAD(0x89c, DS0_PIN_OUTPUT_PULLUP | MUX_MODE7)
  241. >;
  242. };
  243. ecap0_pins_default: backlight_pins_default {
  244. pinctrl-single,pins = <
  245. AM4372_IOPAD(0x964, MUX_MODE0) /* eCAP0_in_PWM0_out.eCAP0_in_PWM0_out MODE0 */
  246. >;
  247. };
  248. ecap0_pins_sleep: backlight_pins_sleep {
  249. pinctrl-single,pins = <
  250. AM4372_IOPAD(0x964, DS0_PIN_OUTPUT_PULLUP | MUX_MODE7)
  251. >;
  252. };
  253. i2c2_pins: pinmux_i2c2_pins {
  254. pinctrl-single,pins = <
  255. AM4372_IOPAD(0x9c0, PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE8) /* i2c2_sda.i2c2_sda */
  256. AM4372_IOPAD(0x9c4, PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE8) /* i2c2_scl.i2c2_scl */
  257. >;
  258. };
  259. spi0_pins_default: pinmux_spi0_pins_default {
  260. pinctrl-single,pins = <
  261. AM4372_IOPAD(0x950, PIN_INPUT | MUX_MODE0) /* spi0_clk.spi0_clk */
  262. AM4372_IOPAD(0x954, PIN_OUTPUT | MUX_MODE0) /* spi0_d0.spi0_d0 */
  263. AM4372_IOPAD(0x958, PIN_INPUT | MUX_MODE0) /* spi0_d1.spi0_d1 */
  264. AM4372_IOPAD(0x95c, PIN_OUTPUT | MUX_MODE0) /* spi0_cs0.spi0_cs0 */
  265. >;
  266. };
  267. spi0_pins_sleep: pinmux_spi0_pins_sleep {
  268. pinctrl-single,pins = <
  269. AM4372_IOPAD(0x950, DS0_PIN_OUTPUT_PULLUP | PIN_OUTPUT_PULLUP | MUX_MODE7)
  270. AM4372_IOPAD(0x954, DS0_PIN_OUTPUT_PULLUP | PIN_OUTPUT_PULLUP | MUX_MODE7)
  271. AM4372_IOPAD(0x958, DS0_PIN_OUTPUT_PULLUP | PIN_OUTPUT_PULLUP | MUX_MODE7)
  272. AM4372_IOPAD(0x95c, DS0_PIN_OUTPUT_PULLUP | PIN_OUTPUT_PULLUP | MUX_MODE7)
  273. >;
  274. };
  275. spi1_pins_default: pinmux_spi1_pins_default {
  276. pinctrl-single,pins = <
  277. AM4372_IOPAD(0x990, PIN_INPUT | MUX_MODE3) /* mcasp0_aclkx.spi1_clk */
  278. AM4372_IOPAD(0x994, PIN_OUTPUT | MUX_MODE3) /* mcasp0_fsx.spi1_d0 */
  279. AM4372_IOPAD(0x998, PIN_INPUT | MUX_MODE3) /* mcasp0_axr0.spi1_d1 */
  280. AM4372_IOPAD(0x99c, PIN_OUTPUT | MUX_MODE3) /* mcasp0_ahclkr.spi1_cs0 */
  281. >;
  282. };
  283. spi1_pins_sleep: pinmux_spi1_pins_sleep {
  284. pinctrl-single,pins = <
  285. AM4372_IOPAD(0x990, DS0_PIN_OUTPUT_PULLDOWN | PIN_OUTPUT_PULLDOWN | MUX_MODE7)
  286. AM4372_IOPAD(0x994, DS0_PIN_OUTPUT_PULLDOWN | PIN_OUTPUT_PULLDOWN | MUX_MODE7)
  287. AM4372_IOPAD(0x998, DS0_PIN_OUTPUT_PULLDOWN | PIN_OUTPUT_PULLDOWN | MUX_MODE7)
  288. AM4372_IOPAD(0x99c, DS0_PIN_OUTPUT_PULLDOWN | PIN_OUTPUT_PULLDOWN | MUX_MODE7)
  289. >;
  290. };
  291. mmc1_pins_default: pinmux_mmc1_pins_default {
  292. pinctrl-single,pins = <
  293. AM4372_IOPAD(0x960, PIN_INPUT | MUX_MODE7) /* spi0_cs1.gpio0_6 */
  294. >;
  295. };
  296. mmc1_pins_sleep: pinmux_mmc1_pins_sleep {
  297. pinctrl-single,pins = <
  298. AM4372_IOPAD(0x960, DS0_PIN_OUTPUT_PULLUP | PIN_INPUT | MUX_MODE7)
  299. >;
  300. };
  301. matrix_keypad_default: matrix_keypad_default {
  302. pinctrl-single,pins = <
  303. AM4372_IOPAD(0x92c, PIN_OUTPUT | MUX_MODE7) /* mii1_tx_clk.gpio3_9 */
  304. AM4372_IOPAD(0x930, PIN_OUTPUT | MUX_MODE7) /* mii1_rx_clk.gpio3_10 */
  305. AM4372_IOPAD(0x934, PIN_OUTPUT | MUX_MODE7) /* mii1_rxd3.gpio2_18 */
  306. AM4372_IOPAD(0x938, PIN_OUTPUT | MUX_MODE7) /* mii1_rxd2.gpio2_19 */
  307. AM4372_IOPAD(0x978, PIN_INPUT_PULLDOWN | MUX_MODE7) /* uart1_ctsn.gpio0_12 */
  308. AM4372_IOPAD(0x97C, PIN_INPUT_PULLDOWN | MUX_MODE7) /* uart1_rtsn.gpio0_13 */
  309. AM4372_IOPAD(0x980, PIN_INPUT_PULLDOWN | MUX_MODE7) /* uart1_rxd.gpio0_14 */
  310. AM4372_IOPAD(0x984, PIN_INPUT_PULLDOWN | MUX_MODE7) /* uart1_txd.gpio0_15 */
  311. >;
  312. };
  313. matrix_keypad_sleep: matrix_keypad_sleep {
  314. pinctrl-single,pins = <
  315. AM4372_IOPAD(0x92c, PIN_INPUT_PULLUP | MUX_MODE7)
  316. AM4372_IOPAD(0x930, PIN_INPUT_PULLUP | MUX_MODE7)
  317. AM4372_IOPAD(0x934, PIN_INPUT_PULLUP | MUX_MODE7)
  318. AM4372_IOPAD(0x938, PIN_INPUT_PULLUP | MUX_MODE7)
  319. AM4372_IOPAD(0x978, PIN_INPUT_PULLDOWN | MUX_MODE7)
  320. AM4372_IOPAD(0x97C, PIN_INPUT_PULLDOWN | MUX_MODE7)
  321. AM4372_IOPAD(0x980, PIN_INPUT_PULLDOWN | MUX_MODE7)
  322. AM4372_IOPAD(0x984, PIN_INPUT_PULLDOWN | MUX_MODE7)
  323. >;
  324. };
  325. qspi1_pins_default: qspi1_pins_default {
  326. pinctrl-single,pins = <
  327. AM4372_IOPAD(0x87c, PIN_INPUT_PULLUP | MUX_MODE3)
  328. AM4372_IOPAD(0x888, PIN_INPUT_PULLUP | MUX_MODE2)
  329. AM4372_IOPAD(0x890, PIN_INPUT_PULLUP | MUX_MODE3)
  330. AM4372_IOPAD(0x894, PIN_INPUT_PULLUP | MUX_MODE3)
  331. AM4372_IOPAD(0x898, PIN_INPUT_PULLUP | MUX_MODE3)
  332. AM4372_IOPAD(0x89c, PIN_INPUT_PULLUP | MUX_MODE3)
  333. >;
  334. };
  335. qspi1_pins_sleep: qspi1_pins_sleep {
  336. pinctrl-single,pins = <
  337. AM4372_IOPAD(0x87c, DS0_PIN_OUTPUT_PULLUP | MUX_MODE7)
  338. AM4372_IOPAD(0x888, DS0_PIN_OUTPUT_PULLUP | MUX_MODE7)
  339. AM4372_IOPAD(0x890, DS0_PIN_OUTPUT_PULLUP | MUX_MODE7)
  340. AM4372_IOPAD(0x894, DS0_PIN_OUTPUT_PULLUP | MUX_MODE7)
  341. AM4372_IOPAD(0x898, DS0_PIN_OUTPUT_PULLUP | MUX_MODE7)
  342. AM4372_IOPAD(0x89c, DS0_PIN_OUTPUT_PULLUP | MUX_MODE7)
  343. >;
  344. };
  345. pixcir_ts_pins_default: pixcir_ts_pins_default {
  346. pinctrl-single,pins = <
  347. AM4372_IOPAD(0x844, PIN_INPUT_PULLUP | MUX_MODE7) /* gpmc_a1.gpio1_17 */
  348. >;
  349. };
  350. pixcir_ts_pins_sleep: pixcir_ts_pins_sleep {
  351. pinctrl-single,pins = <
  352. AM4372_IOPAD(0x844, DS0_PIN_OUTPUT_PULLUP | PIN_OUTPUT_PULLUP | MUX_MODE7) /* gpmc_a1.gpio1_17 */
  353. >;
  354. };
  355. hdq_pins: pinmux_hdq_pins {
  356. pinctrl-single,pins = <
  357. AM4372_IOPAD(0xa34, PIN_INPUT_PULLUP | MUX_MODE1) /* cam1_wen.hdq_gpio */
  358. >;
  359. };
  360. dss_pins: dss_pins {
  361. pinctrl-single,pins = <
  362. AM4372_IOPAD(0x820, PIN_OUTPUT_PULLUP | MUX_MODE1) /*gpmc ad 8 -> DSS DATA 23 */
  363. AM4372_IOPAD(0x824, PIN_OUTPUT_PULLUP | MUX_MODE1)
  364. AM4372_IOPAD(0x828, PIN_OUTPUT_PULLUP | MUX_MODE1)
  365. AM4372_IOPAD(0x82c, PIN_OUTPUT_PULLUP | MUX_MODE1)
  366. AM4372_IOPAD(0x830, PIN_OUTPUT_PULLUP | MUX_MODE1)
  367. AM4372_IOPAD(0x834, PIN_OUTPUT_PULLUP | MUX_MODE1)
  368. AM4372_IOPAD(0x838, PIN_OUTPUT_PULLUP | MUX_MODE1)
  369. AM4372_IOPAD(0x83c, PIN_OUTPUT_PULLUP | MUX_MODE1) /*gpmc ad 15 -> DSS DATA 16 */
  370. AM4372_IOPAD(0x8a0, PIN_OUTPUT_PULLUP | MUX_MODE0) /* DSS DATA 0 */
  371. AM4372_IOPAD(0x8a4, PIN_OUTPUT_PULLUP | MUX_MODE0)
  372. AM4372_IOPAD(0x8a8, PIN_OUTPUT_PULLUP | MUX_MODE0)
  373. AM4372_IOPAD(0x8ac, PIN_OUTPUT_PULLUP | MUX_MODE0)
  374. AM4372_IOPAD(0x8b0, PIN_OUTPUT_PULLUP | MUX_MODE0)
  375. AM4372_IOPAD(0x8b4, PIN_OUTPUT_PULLUP | MUX_MODE0)
  376. AM4372_IOPAD(0x8B8, PIN_OUTPUT_PULLUP | MUX_MODE0)
  377. AM4372_IOPAD(0x8bc, PIN_OUTPUT_PULLUP | MUX_MODE0)
  378. AM4372_IOPAD(0x8c0, PIN_OUTPUT_PULLUP | MUX_MODE0)
  379. AM4372_IOPAD(0x8c4, PIN_OUTPUT_PULLUP | MUX_MODE0)
  380. AM4372_IOPAD(0x8c8, PIN_OUTPUT_PULLUP | MUX_MODE0)
  381. AM4372_IOPAD(0x8cc, PIN_OUTPUT_PULLUP | MUX_MODE0)
  382. AM4372_IOPAD(0x8d0, PIN_OUTPUT_PULLUP | MUX_MODE0)
  383. AM4372_IOPAD(0x8d4, PIN_OUTPUT_PULLUP | MUX_MODE0)
  384. AM4372_IOPAD(0x8d8, PIN_OUTPUT_PULLUP | MUX_MODE0)
  385. AM4372_IOPAD(0x8dc, PIN_OUTPUT_PULLUP | MUX_MODE0) /* DSS DATA 15 */
  386. AM4372_IOPAD(0x8e0, PIN_OUTPUT_PULLUP | MUX_MODE0) /* DSS VSYNC */
  387. AM4372_IOPAD(0x8e4, PIN_OUTPUT_PULLUP | MUX_MODE0) /* DSS HSYNC */
  388. AM4372_IOPAD(0x8e8, PIN_OUTPUT_PULLUP | MUX_MODE0) /* DSS PCLK */
  389. AM4372_IOPAD(0x8ec, PIN_OUTPUT_PULLUP | MUX_MODE0) /* DSS AC BIAS EN */
  390. >;
  391. };
  392. display_mux_pins: display_mux_pins {
  393. pinctrl-single,pins = <
  394. /* GPMC CLK -> GPIO 2_1 to select LCD / HDMI */
  395. AM4372_IOPAD(0x88C, PIN_OUTPUT_PULLUP | MUX_MODE7)
  396. >;
  397. };
  398. vpfe1_pins_default: vpfe1_pins_default {
  399. pinctrl-single,pins = <
  400. AM4372_IOPAD(0x9cc, PIN_INPUT_PULLUP | MUX_MODE0) /* cam1_data9 mode 0 */
  401. AM4372_IOPAD(0x9d0, PIN_INPUT_PULLUP | MUX_MODE0) /* cam1_data8 mode 0 */
  402. AM4372_IOPAD(0x9d4, PIN_INPUT_PULLUP | MUX_MODE0) /* cam1_hd mode 0 */
  403. AM4372_IOPAD(0x9d8, PIN_INPUT_PULLUP | MUX_MODE0) /* cam1_vd mode 0 */
  404. AM4372_IOPAD(0x9dc, PIN_INPUT_PULLUP | MUX_MODE0) /* cam1_pclk mode 0 */
  405. AM4372_IOPAD(0x9e8, PIN_INPUT_PULLUP | MUX_MODE0) /* cam1_data0 mode 0 */
  406. AM4372_IOPAD(0x9ec, PIN_INPUT_PULLUP | MUX_MODE0) /* cam1_data1 mode 0 */
  407. AM4372_IOPAD(0x9f0, PIN_INPUT_PULLUP | MUX_MODE0) /* cam1_data2 mode 0 */
  408. AM4372_IOPAD(0x9f4, PIN_INPUT_PULLUP | MUX_MODE0) /* cam1_data3 mode 0 */
  409. AM4372_IOPAD(0x9f8, PIN_INPUT_PULLUP | MUX_MODE0) /* cam1_data4 mode 0 */
  410. AM4372_IOPAD(0x9fc, PIN_INPUT_PULLUP | MUX_MODE0) /* cam1_data5 mode 0 */
  411. AM4372_IOPAD(0xa00, PIN_INPUT_PULLUP | MUX_MODE0) /* cam1_data6 mode 0 */
  412. AM4372_IOPAD(0xa04, PIN_INPUT_PULLUP | MUX_MODE0) /* cam1_data7 mode 0 */
  413. >;
  414. };
  415. vpfe1_pins_sleep: vpfe1_pins_sleep {
  416. pinctrl-single,pins = <
  417. AM4372_IOPAD(0x9cc, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7)
  418. AM4372_IOPAD(0x9d0, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7)
  419. AM4372_IOPAD(0x9d4, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7)
  420. AM4372_IOPAD(0x9d8, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7)
  421. AM4372_IOPAD(0x9dc, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7)
  422. AM4372_IOPAD(0x9e8, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7)
  423. AM4372_IOPAD(0x9ec, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7)
  424. AM4372_IOPAD(0x9f0, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7)
  425. AM4372_IOPAD(0x9f4, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7)
  426. AM4372_IOPAD(0x9f8, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7)
  427. AM4372_IOPAD(0x9fc, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7)
  428. AM4372_IOPAD(0xa00, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7)
  429. AM4372_IOPAD(0xa04, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7)
  430. >;
  431. };
  432. uart0_pins_default: uart0_pins_default {
  433. pinctrl-single,pins = <
  434. AM4372_IOPAD(0x968, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE0) /* uart0_ctsn.uart0_ctsn */
  435. AM4372_IOPAD(0x96C, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE0) /* uart0_rtsn.uart0_rtsn */
  436. AM4372_IOPAD(0x970, PIN_INPUT_PULLUP | SLEWCTRL_FAST | DS0_PULL_UP_DOWN_EN | MUX_MODE0) /* uart0_rxd.uart0_rxd */
  437. AM4372_IOPAD(0x974, PIN_INPUT | SLEWCTRL_FAST | DS0_PULL_UP_DOWN_EN | MUX_MODE0) /* uart0_txd.uart0_txd */
  438. >;
  439. };
  440. uart0_pins_sleep: uart0_pins_sleep {
  441. pinctrl-single,pins = <
  442. AM4372_IOPAD(0x968, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7)
  443. AM4372_IOPAD(0x96C, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7)
  444. AM4372_IOPAD(0x970, PIN_INPUT_PULLUP | SLEWCTRL_FAST | DS0_PULL_UP_DOWN_EN | MUX_MODE0)
  445. AM4372_IOPAD(0x974, PIN_INPUT | SLEWCTRL_FAST | DS0_PULL_UP_DOWN_EN | MUX_MODE0)
  446. >;
  447. };
  448. usb2_phy1_default: usb2_phy1_default {
  449. pinctrl-single,pins = <
  450. AM4372_IOPAD(0xac0, PIN_INPUT_PULLDOWN | MUX_MODE0)
  451. >;
  452. };
  453. usb2_phy1_sleep: usb2_phy1_sleep {
  454. pinctrl-single,pins = <
  455. AM4372_IOPAD(0xac0, DS0_PULL_UP_DOWN_EN | PIN_INPUT_PULLDOWN | MUX_MODE7)
  456. >;
  457. };
  458. usb2_phy2_default: usb2_phy2_default {
  459. pinctrl-single,pins = <
  460. AM4372_IOPAD(0xac4, PIN_INPUT_PULLDOWN | MUX_MODE0)
  461. >;
  462. };
  463. usb2_phy2_sleep: usb2_phy2_sleep {
  464. pinctrl-single,pins = <
  465. AM4372_IOPAD(0xac4, DS0_PULL_UP_DOWN_EN | PIN_INPUT_PULLDOWN | MUX_MODE7)
  466. >;
  467. };
  468. mcasp1_pins: mcasp1_pins {
  469. pinctrl-single,pins = <
  470. AM4372_IOPAD(0x9a0, PIN_INPUT_PULLDOWN | MUX_MODE3) /* MCASP0_ACLKR/MCASP1_ACLKX */
  471. AM4372_IOPAD(0x9a4, PIN_INPUT_PULLDOWN | MUX_MODE3) /* MCASP0_FSR/MCASP1_FSX */
  472. AM4372_IOPAD(0x9a8, PIN_OUTPUT_PULLDOWN | MUX_MODE3)/* MCASP0_AXR1/MCASP1_AXR0 */
  473. AM4372_IOPAD(0x9ac, PIN_INPUT_PULLDOWN | MUX_MODE3) /* MCASP0_AHCLKX/MCASP1_AXR1 */
  474. >;
  475. };
  476. mcasp1_sleep_pins: mcasp1_sleep_pins {
  477. pinctrl-single,pins = <
  478. AM4372_IOPAD(0x9a0, PIN_INPUT_PULLDOWN | MUX_MODE7)
  479. AM4372_IOPAD(0x9a4, PIN_INPUT_PULLDOWN | MUX_MODE7)
  480. AM4372_IOPAD(0x9a8, PIN_INPUT_PULLDOWN | MUX_MODE7)
  481. AM4372_IOPAD(0x9ac, PIN_INPUT_PULLDOWN | MUX_MODE7)
  482. >;
  483. };
  484. };
  485. &mmc1 {
  486. status = "okay";
  487. vmmc-supply = <&vmmcsd_fixed>;
  488. bus-width = <4>;
  489. pinctrl-names = "default", "sleep";
  490. pinctrl-0 = <&mmc1_pins_default>;
  491. pinctrl-1 = <&mmc1_pins_sleep>;
  492. cd-gpios = <&gpio0 6 GPIO_ACTIVE_LOW>;
  493. };
  494. &mac_sw {
  495. pinctrl-names = "default", "sleep";
  496. pinctrl-0 = <&cpsw_default>;
  497. pinctrl-1 = <&cpsw_sleep>;
  498. status = "okay";
  499. };
  500. &davinci_mdio_sw {
  501. pinctrl-names = "default", "sleep";
  502. pinctrl-0 = <&davinci_mdio_default>;
  503. pinctrl-1 = <&davinci_mdio_sleep>;
  504. ethphy0: ethernet-phy@16 {
  505. reg = <16>;
  506. };
  507. };
  508. &cpsw_port1 {
  509. phy-handle = <&ethphy0>;
  510. phy-mode = "rmii";
  511. phys = <&phy_gmii_sel 1 1>;
  512. ti,dual-emac-pvid = <1>;
  513. };
  514. &cpsw_port2 {
  515. status = "disabled";
  516. };
  517. &i2c0 {
  518. status = "okay";
  519. pinctrl-names = "default";
  520. pinctrl-0 = <&i2c0_pins>;
  521. clock-frequency = <100000>;
  522. tps65218: tps65218@24 {
  523. reg = <0x24>;
  524. compatible = "ti,tps65218";
  525. interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>; /* NMIn */
  526. interrupt-controller;
  527. #interrupt-cells = <2>;
  528. dcdc1: regulator-dcdc1 {
  529. regulator-name = "vdd_core";
  530. regulator-min-microvolt = <912000>;
  531. regulator-max-microvolt = <1144000>;
  532. regulator-boot-on;
  533. regulator-always-on;
  534. };
  535. dcdc2: regulator-dcdc2 {
  536. regulator-name = "vdd_mpu";
  537. regulator-min-microvolt = <912000>;
  538. regulator-max-microvolt = <1378000>;
  539. regulator-boot-on;
  540. regulator-always-on;
  541. };
  542. dcdc3: regulator-dcdc3 {
  543. regulator-name = "vdcdc3";
  544. regulator-boot-on;
  545. regulator-always-on;
  546. regulator-state-mem {
  547. regulator-on-in-suspend;
  548. };
  549. regulator-state-disk {
  550. regulator-off-in-suspend;
  551. };
  552. };
  553. dcdc4: regulator-dcdc4 {
  554. regulator-name = "vdcdc4";
  555. regulator-min-microvolt = <3300000>;
  556. regulator-max-microvolt = <3300000>;
  557. regulator-boot-on;
  558. regulator-always-on;
  559. };
  560. dcdc5: regulator-dcdc5 {
  561. regulator-name = "v1_0bat";
  562. regulator-min-microvolt = <1000000>;
  563. regulator-max-microvolt = <1000000>;
  564. regulator-boot-on;
  565. regulator-always-on;
  566. };
  567. dcdc6: regulator-dcdc6 {
  568. regulator-name = "v1_8bat";
  569. regulator-min-microvolt = <1800000>;
  570. regulator-max-microvolt = <1800000>;
  571. regulator-boot-on;
  572. regulator-always-on;
  573. };
  574. ldo1: regulator-ldo1 {
  575. regulator-min-microvolt = <1800000>;
  576. regulator-max-microvolt = <1800000>;
  577. regulator-boot-on;
  578. regulator-always-on;
  579. };
  580. };
  581. at24@50 {
  582. compatible = "atmel,24c256";
  583. pagesize = <64>;
  584. reg = <0x50>;
  585. };
  586. pixcir_ts@5c {
  587. compatible = "pixcir,pixcir_tangoc";
  588. pinctrl-names = "default", "sleep";
  589. pinctrl-0 = <&pixcir_ts_pins_default>;
  590. pinctrl-1 = <&pixcir_ts_pins_sleep>;
  591. reg = <0x5c>;
  592. interrupt-parent = <&gpio1>;
  593. interrupts = <17 IRQ_TYPE_EDGE_FALLING>;
  594. attb-gpio = <&gpio1 17 GPIO_ACTIVE_HIGH>;
  595. touchscreen-size-x = <1024>;
  596. touchscreen-size-y = <600>;
  597. };
  598. tlv320aic3111: tlv320aic3111@18 {
  599. #sound-dai-cells = <0>;
  600. compatible = "ti,tlv320aic3111";
  601. reg = <0x18>;
  602. status = "okay";
  603. ai31xx-micbias-vg = <MICBIAS_2_0V>;
  604. /* Regulators */
  605. HPVDD-supply = <&dcdc4>; /* v3_3AUD -> V3_3D -> DCDC4 */
  606. SPRVDD-supply = <&vbat>; /* vbat */
  607. SPLVDD-supply = <&vbat>; /* vbat */
  608. AVDD-supply = <&dcdc4>; /* v3_3AUD -> V3_3D -> DCDC4 */
  609. IOVDD-supply = <&dcdc4>; /* V3_3D -> DCDC4 */
  610. DVDD-supply = <&ldo1>; /* V1_8AUD -> V1_8D -> LDO1 */
  611. };
  612. ov2659@30 {
  613. compatible = "ovti,ov2659";
  614. reg = <0x30>;
  615. clocks = <&audio_mstrclk>;
  616. clock-names = "xvclk";
  617. port {
  618. ov2659_1: endpoint {
  619. remote-endpoint = <&vpfe1_ep>;
  620. link-frequencies = /bits/ 64 <70000000>;
  621. };
  622. };
  623. };
  624. };
  625. &i2c2 {
  626. pinctrl-names = "default";
  627. pinctrl-0 = <&i2c2_pins>;
  628. status = "okay";
  629. };
  630. &gpio0 {
  631. status = "okay";
  632. };
  633. &gpio1 {
  634. status = "okay";
  635. };
  636. &gpio2 {
  637. pinctrl-names = "default";
  638. pinctrl-0 = <&display_mux_pins>;
  639. status = "okay";
  640. sel-lcd-hdmi-hog {
  641. /*
  642. * SelLCDorHDMI selects between display and audio paths:
  643. * Low: HDMI display with audio via HDMI
  644. * High: LCD display with analog audio via aic3111 codec
  645. */
  646. gpio-hog;
  647. gpios = <1 GPIO_ACTIVE_HIGH>;
  648. output-high;
  649. line-name = "SelLCDorHDMI";
  650. };
  651. };
  652. &gpio3 {
  653. status = "okay";
  654. };
  655. &elm {
  656. status = "okay";
  657. };
  658. &gpmc {
  659. status = "okay"; /* Disable QSPI when enabling GPMC (NAND) */
  660. pinctrl-names = "default", "sleep";
  661. pinctrl-0 = <&nand_flash_x8_default>;
  662. pinctrl-1 = <&nand_flash_x8_sleep>;
  663. ranges = <0 0 0x08000000 0x01000000>; /* CS0 space. Min partition = 16MB */
  664. nand@0,0 {
  665. compatible = "ti,omap2-nand";
  666. reg = <0 0 4>; /* CS0, offset 0, IO size 4 */
  667. interrupt-parent = <&gpmc>;
  668. interrupts = <0 IRQ_TYPE_NONE>, /* fifoevent */
  669. <1 IRQ_TYPE_NONE>; /* termcount */
  670. rb-gpios = <&gpmc 0 GPIO_ACTIVE_HIGH>; /* gpmc_wait0 */
  671. ti,nand-xfer-type = "prefetch-dma";
  672. ti,nand-ecc-opt = "bch16";
  673. ti,elm-id = <&elm>;
  674. nand-bus-width = <8>;
  675. gpmc,device-width = <1>;
  676. gpmc,sync-clk-ps = <0>;
  677. gpmc,cs-on-ns = <0>;
  678. gpmc,cs-rd-off-ns = <40>; /* tCEA + tCHZ + 1 */
  679. gpmc,cs-wr-off-ns = <40>;
  680. gpmc,adv-on-ns = <0>; /* cs-on-ns */
  681. gpmc,adv-rd-off-ns = <25>; /* min( tALH + tALS + 1) */
  682. gpmc,adv-wr-off-ns = <25>; /* min( tALH + tALS + 1) */
  683. gpmc,we-on-ns = <0>; /* cs-on-ns */
  684. gpmc,we-off-ns = <20>; /* we-on-time + tWP + 2 */
  685. gpmc,oe-on-ns = <3>; /* cs-on-ns + tRR + 2 */
  686. gpmc,oe-off-ns = <30>; /* oe-on-ns + tRP + 2 */
  687. gpmc,access-ns = <30>; /* tCEA + 4*/
  688. gpmc,rd-cycle-ns = <40>;
  689. gpmc,wr-cycle-ns = <40>;
  690. gpmc,bus-turnaround-ns = <0>;
  691. gpmc,cycle2cycle-delay-ns = <0>;
  692. gpmc,clk-activation-ns = <0>;
  693. gpmc,wr-access-ns = <40>;
  694. gpmc,wr-data-mux-bus-ns = <0>;
  695. /* MTD partition table */
  696. /* All SPL-* partitions are sized to minimal length
  697. * which can be independently programmable. For
  698. * NAND flash this is equal to size of erase-block */
  699. #address-cells = <1>;
  700. #size-cells = <1>;
  701. partition@0 {
  702. label = "NAND.SPL";
  703. reg = <0x00000000 0x00040000>;
  704. };
  705. partition@1 {
  706. label = "NAND.SPL.backup1";
  707. reg = <0x00040000 0x00040000>;
  708. };
  709. partition@2 {
  710. label = "NAND.SPL.backup2";
  711. reg = <0x00080000 0x00040000>;
  712. };
  713. partition@3 {
  714. label = "NAND.SPL.backup3";
  715. reg = <0x000C0000 0x00040000>;
  716. };
  717. partition@4 {
  718. label = "NAND.u-boot-spl-os";
  719. reg = <0x00100000 0x00080000>;
  720. };
  721. partition@5 {
  722. label = "NAND.u-boot";
  723. reg = <0x00180000 0x00100000>;
  724. };
  725. partition@6 {
  726. label = "NAND.u-boot-env";
  727. reg = <0x00280000 0x00040000>;
  728. };
  729. partition@7 {
  730. label = "NAND.u-boot-env.backup1";
  731. reg = <0x002C0000 0x00040000>;
  732. };
  733. partition@8 {
  734. label = "NAND.kernel";
  735. reg = <0x00300000 0x00700000>;
  736. };
  737. partition@9 {
  738. label = "NAND.file-system";
  739. reg = <0x00a00000 0x1f600000>;
  740. };
  741. };
  742. };
  743. &epwmss0 {
  744. status = "okay";
  745. };
  746. &rtc_target {
  747. status = "disabled";
  748. };
  749. &tscadc {
  750. status = "okay";
  751. adc {
  752. ti,adc-channels = <0 1 2 3 4 5 6 7>;
  753. };
  754. };
  755. &ecap0 {
  756. status = "okay";
  757. pinctrl-names = "default", "sleep";
  758. pinctrl-0 = <&ecap0_pins_default>;
  759. pinctrl-1 = <&ecap0_pins_sleep>;
  760. };
  761. &spi0 {
  762. status = "okay";
  763. pinctrl-names = "default", "sleep";
  764. pinctrl-0 = <&spi0_pins_default>;
  765. pinctrl-1 = <&spi0_pins_sleep>;
  766. ti,pindir-d0-out-d1-in;
  767. };
  768. &spi1 {
  769. status = "okay";
  770. pinctrl-names = "default", "sleep";
  771. pinctrl-0 = <&spi1_pins_default>;
  772. pinctrl-1 = <&spi1_pins_sleep>;
  773. ti,pindir-d0-out-d1-in;
  774. };
  775. &usb2_phy1 {
  776. status = "okay";
  777. pinctrl-names = "default", "sleep";
  778. pinctrl-0 = <&usb2_phy1_default>;
  779. pinctrl-1 = <&usb2_phy1_sleep>;
  780. };
  781. &usb1 {
  782. dr_mode = "otg";
  783. status = "okay";
  784. };
  785. &usb2_phy2 {
  786. status = "okay";
  787. pinctrl-names = "default", "sleep";
  788. pinctrl-0 = <&usb2_phy2_default>;
  789. pinctrl-1 = <&usb2_phy2_sleep>;
  790. };
  791. &usb2 {
  792. dr_mode = "host";
  793. status = "okay";
  794. };
  795. &qspi {
  796. status = "disabled"; /* Disable GPMC (NAND) when enabling QSPI */
  797. pinctrl-names = "default", "sleep";
  798. pinctrl-0 = <&qspi1_pins_default>;
  799. pinctrl-1 = <&qspi1_pins_sleep>;
  800. spi-max-frequency = <48000000>;
  801. flash@0 {
  802. compatible = "mx66l51235l";
  803. spi-max-frequency = <48000000>;
  804. reg = <0>;
  805. spi-cpol;
  806. spi-cpha;
  807. spi-tx-bus-width = <1>;
  808. spi-rx-bus-width = <4>;
  809. #address-cells = <1>;
  810. #size-cells = <1>;
  811. /* MTD partition table.
  812. * The ROM checks the first 512KiB
  813. * for a valid file to boot(XIP).
  814. */
  815. partition@0 {
  816. label = "QSPI.U_BOOT";
  817. reg = <0x00000000 0x000080000>;
  818. };
  819. partition@1 {
  820. label = "QSPI.U_BOOT.backup";
  821. reg = <0x00080000 0x00080000>;
  822. };
  823. partition@2 {
  824. label = "QSPI.U-BOOT-SPL_OS";
  825. reg = <0x00100000 0x00010000>;
  826. };
  827. partition@3 {
  828. label = "QSPI.U_BOOT_ENV";
  829. reg = <0x00110000 0x00010000>;
  830. };
  831. partition@4 {
  832. label = "QSPI.U-BOOT-ENV.backup";
  833. reg = <0x00120000 0x00010000>;
  834. };
  835. partition@5 {
  836. label = "QSPI.KERNEL";
  837. reg = <0x00130000 0x0800000>;
  838. };
  839. partition@6 {
  840. label = "QSPI.FILESYSTEM";
  841. reg = <0x00930000 0x36D0000>;
  842. };
  843. };
  844. };
  845. &hdq {
  846. status = "okay";
  847. pinctrl-names = "default";
  848. pinctrl-0 = <&hdq_pins>;
  849. };
  850. &dss {
  851. status = "okay";
  852. pinctrl-names = "default";
  853. pinctrl-0 = <&dss_pins>;
  854. port {
  855. dpi_out: endpoint {
  856. remote-endpoint = <&lcd_in>;
  857. data-lines = <24>;
  858. };
  859. };
  860. };
  861. &vpfe1 {
  862. status = "okay";
  863. pinctrl-names = "default", "sleep";
  864. pinctrl-0 = <&vpfe1_pins_default>;
  865. pinctrl-1 = <&vpfe1_pins_sleep>;
  866. port {
  867. vpfe1_ep: endpoint {
  868. remote-endpoint = <&ov2659_1>;
  869. ti,am437x-vpfe-interface = <0>;
  870. bus-width = <8>;
  871. hsync-active = <0>;
  872. vsync-active = <0>;
  873. };
  874. };
  875. };
  876. &uart0 {
  877. status = "okay";
  878. pinctrl-names = "default", "sleep";
  879. pinctrl-0 = <&uart0_pins_default>;
  880. pinctrl-1 = <&uart0_pins_sleep>;
  881. };
  882. &mcasp1 {
  883. #sound-dai-cells = <0>;
  884. pinctrl-names = "default", "sleep";
  885. pinctrl-0 = <&mcasp1_pins>;
  886. pinctrl-1 = <&mcasp1_sleep_pins>;
  887. status = "okay";
  888. op-mode = <0>; /* MCASP_IIS_MODE */
  889. tdm-slots = <2>;
  890. /* 4 serializer */
  891. serial-dir = < /* 0: INACTIVE, 1: TX, 2: RX */
  892. 1 2 0 0
  893. >;
  894. tx-num-evt = <32>;
  895. rx-num-evt = <32>;
  896. };
  897. &mux_synctimer32k_ck {
  898. assigned-clocks = <&mux_synctimer32k_ck>;
  899. assigned-clock-parents = <&clkdiv32k_ick>;
  900. };
  901. &cpu {
  902. cpu0-supply = <&dcdc2>;
  903. };
  904. &wkup_m3_ipc {
  905. firmware-name = "am43x-evm-scale-data.bin";
  906. };
  907. &pruss1_mdio {
  908. status = "disabled";
  909. };