am335x-netcom-plus-2xx.dts 4.2 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239
  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. * Copyright (C) 2012 Texas Instruments Incorporated - https://www.ti.com/
  4. */
  5. /*
  6. * VScom OnRISC
  7. * http://www.vscom.de
  8. */
  9. /dts-v1/;
  10. #include "am335x-baltos.dtsi"
  11. #include "am335x-baltos-leds.dtsi"
  12. / {
  13. model = "NetCom Plus";
  14. };
  15. &am33xx_pinmux {
  16. uart1_pins: pinmux_uart1_pins {
  17. pinctrl-single,pins = <
  18. AM33XX_PADCONF(AM335X_PIN_UART1_RXD, PIN_INPUT, MUX_MODE0) /* RX */
  19. AM33XX_PADCONF(AM335X_PIN_UART1_TXD, PIN_INPUT, MUX_MODE0) /* TX */
  20. AM33XX_PADCONF(AM335X_PIN_UART1_CTSN, PIN_INPUT_PULLDOWN, MUX_MODE0) /* CTS */
  21. AM33XX_PADCONF(AM335X_PIN_UART1_RTSN, PIN_OUTPUT_PULLDOWN, MUX_MODE0) /* RTS */
  22. AM33XX_PADCONF(AM335X_PIN_LCD_VSYNC, PIN_OUTPUT_PULLDOWN, MUX_MODE7) /* DTR */
  23. AM33XX_PADCONF(AM335X_PIN_LCD_HSYNC, PIN_INPUT_PULLDOWN, MUX_MODE7) /* DSR */
  24. AM33XX_PADCONF(AM335X_PIN_LCD_PCLK, PIN_INPUT_PULLDOWN, MUX_MODE7) /* DCD */
  25. AM33XX_PADCONF(AM335X_PIN_LCD_AC_BIAS_EN, PIN_INPUT_PULLDOWN, MUX_MODE7) /* RI */
  26. >;
  27. };
  28. uart2_pins: pinmux_uart2_pins {
  29. pinctrl-single,pins = <
  30. AM33XX_PADCONF(AM335X_PIN_SPI0_SCLK, PIN_INPUT, MUX_MODE1) /* RX */
  31. AM33XX_PADCONF(AM335X_PIN_SPI0_D0, PIN_OUTPUT, MUX_MODE1) /* TX */
  32. AM33XX_PADCONF(AM335X_PIN_I2C0_SDA, PIN_INPUT_PULLDOWN, MUX_MODE2) /* CTS */
  33. AM33XX_PADCONF(AM335X_PIN_I2C0_SCL, PIN_OUTPUT_PULLDOWN, MUX_MODE2) /* RTS */
  34. AM33XX_PADCONF(AM335X_PIN_GPMC_AD12, PIN_OUTPUT_PULLDOWN, MUX_MODE7) /* DTR */
  35. AM33XX_PADCONF(AM335X_PIN_GPMC_AD13, PIN_INPUT_PULLDOWN, MUX_MODE7) /* DSR */
  36. AM33XX_PADCONF(AM335X_PIN_GPMC_AD14, PIN_INPUT_PULLDOWN, MUX_MODE7) /* DCD */
  37. AM33XX_PADCONF(AM335X_PIN_GPMC_AD15, PIN_INPUT_PULLDOWN, MUX_MODE7) /* RI */
  38. >;
  39. };
  40. };
  41. &usb0_phy {
  42. status = "okay";
  43. };
  44. &usb0 {
  45. status = "okay";
  46. dr_mode = "host";
  47. };
  48. &uart1 {
  49. pinctrl-names = "default";
  50. pinctrl-0 = <&uart1_pins>;
  51. dtr-gpios = <&gpio2 22 GPIO_ACTIVE_LOW>;
  52. dsr-gpios = <&gpio2 23 GPIO_ACTIVE_LOW>;
  53. dcd-gpios = <&gpio2 24 GPIO_ACTIVE_LOW>;
  54. rng-gpios = <&gpio2 25 GPIO_ACTIVE_LOW>;
  55. status = "okay";
  56. };
  57. &uart2 {
  58. pinctrl-names = "default";
  59. pinctrl-0 = <&uart2_pins>;
  60. dtr-gpios = <&gpio1 12 GPIO_ACTIVE_LOW>;
  61. dsr-gpios = <&gpio1 13 GPIO_ACTIVE_LOW>;
  62. dcd-gpios = <&gpio1 14 GPIO_ACTIVE_LOW>;
  63. rng-gpios = <&gpio1 15 GPIO_ACTIVE_LOW>;
  64. status = "okay";
  65. };
  66. &davinci_mdio_sw {
  67. phy0: ethernet-phy@0 {
  68. reg = <1>;
  69. };
  70. };
  71. &cpsw_port1 {
  72. phy-mode = "rmii";
  73. ti,dual-emac-pvid = <1>;
  74. phy-handle = <&phy0>;
  75. };
  76. &cpsw_port2 {
  77. phy-mode = "rgmii-id";
  78. ti,dual-emac-pvid = <2>;
  79. phy-handle = <&phy1>;
  80. };
  81. &gpio0 {
  82. gpio-line-names =
  83. "MDIO",
  84. "MDC",
  85. "UART2_RX",
  86. "UART2_TX",
  87. "I2C1_SDA",
  88. "I2C1_SCL",
  89. "NC",
  90. "NC",
  91. "NC",
  92. "NC",
  93. "NC",
  94. "NC",
  95. "UART1_CTSN",
  96. "UART1_RTSN",
  97. "UART1_RX",
  98. "UART1_TX",
  99. "onrisc:blue:wlan",
  100. "onrisc:green:app",
  101. "USB0_DRVVBUS",
  102. "ETH2_INT",
  103. "NC",
  104. "NC",
  105. "MMC1_DAT0",
  106. "MMC1_DAT1",
  107. "NC",
  108. "NC",
  109. "MMC1_DAT2",
  110. "MMC1_DAT3",
  111. "NC",
  112. "NC",
  113. "GPMC_WAIT0",
  114. "GPMC_WP_N";
  115. };
  116. &gpio1 {
  117. gpio-line-names =
  118. "GPMC_AD0",
  119. "GPMC_AD1",
  120. "GPMC_AD2",
  121. "GPMC_AD3",
  122. "GPMC_AD4",
  123. "GPMC_AD5",
  124. "GPMC_AD6",
  125. "GPMC_AD7",
  126. "NC",
  127. "NC",
  128. "CONSOLE_RX",
  129. "CONSOLE_TX",
  130. "UART2_DTR",
  131. "UART2_DSR",
  132. "UART2_DCD",
  133. "UART2_RI",
  134. "RGMII2_TCTL",
  135. "RGMII2_RCTL",
  136. "RGMII2_TD3",
  137. "RGMII2_TD2",
  138. "RGMII2_TD1",
  139. "RGMII2_TD0",
  140. "RGMII2_TCLK",
  141. "RGMII2_RCLK",
  142. "RGMII2_RD3",
  143. "RGMII2_RD2",
  144. "RGMII2_RD1",
  145. "RGMII2_RD0",
  146. "PMIC_INT1",
  147. "GPMC_CSN0_Flash",
  148. "MMC1_CLK",
  149. "MMC1_CMD";
  150. };
  151. &gpio2 {
  152. gpio-line-names =
  153. "GPMC_CSN3_BUS",
  154. "GPMC_CLK",
  155. "GPMC_ADVN_ALE",
  156. "GPMC_OEN_RE_N",
  157. "GPMC_WE_N",
  158. "GPMC_BEN0_CLE",
  159. "NC",
  160. "NC",
  161. "NC",
  162. "NC",
  163. "NC",
  164. "NC",
  165. "NC",
  166. "NC",
  167. "NC",
  168. "NC",
  169. "NC",
  170. "NC",
  171. "SW2_0",
  172. "SW2_1",
  173. "NC",
  174. "NC",
  175. "UART1_DTR",
  176. "UART1_DSR",
  177. "UART1_DCD",
  178. "UART1_RI",
  179. "MMC0_DAT3",
  180. "MMC0_DAT2",
  181. "MMC0_DAT1",
  182. "MMC0_DAT0",
  183. "MMC0_CLK",
  184. "MMC0_CMD";
  185. };
  186. &gpio3 {
  187. gpio-line-names =
  188. "onrisc:red:power",
  189. "NC",
  190. "NC",
  191. "NC",
  192. "NC",
  193. "UART2_CTSN",
  194. "UART2_RTSN",
  195. "WLAN_IRQ",
  196. "WLAN_EN",
  197. "SW2_2",
  198. "SW2_3",
  199. "NC",
  200. "NC",
  201. "NC",
  202. "ModeA0",
  203. "ModeA1",
  204. "ModeA2",
  205. "ModeA3",
  206. "NC",
  207. "NC",
  208. "NC",
  209. "NC",
  210. "NC",
  211. "NC",
  212. "NC",
  213. "NC",
  214. "NC",
  215. "NC",
  216. "NC",
  217. "NC",
  218. "NC",
  219. "NC";
  220. };