am335x-igep0033.dtsi 6.1 KB

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  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. * am335x-igep0033.dtsi - Device Tree file for IGEP COM AQUILA AM335x
  4. *
  5. * Copyright (C) 2013 ISEE 2007 SL - http://www.isee.biz
  6. */
  7. /dts-v1/;
  8. #include "am33xx.dtsi"
  9. #include <dt-bindings/interrupt-controller/irq.h>
  10. / {
  11. cpus {
  12. cpu@0 {
  13. cpu0-supply = <&vdd1_reg>;
  14. };
  15. };
  16. memory@80000000 {
  17. device_type = "memory";
  18. reg = <0x80000000 0x10000000>; /* 256 MB */
  19. };
  20. leds {
  21. pinctrl-names = "default";
  22. pinctrl-0 = <&leds_pins>;
  23. compatible = "gpio-leds";
  24. led0 {
  25. label = "com:green:user";
  26. gpios = <&gpio1 23 GPIO_ACTIVE_HIGH>;
  27. default-state = "on";
  28. };
  29. };
  30. vbat: fixedregulator0 {
  31. compatible = "regulator-fixed";
  32. regulator-name = "vbat";
  33. regulator-min-microvolt = <5000000>;
  34. regulator-max-microvolt = <5000000>;
  35. regulator-boot-on;
  36. };
  37. vmmc: fixedregulator1 {
  38. compatible = "regulator-fixed";
  39. regulator-name = "vmmc";
  40. regulator-min-microvolt = <3300000>;
  41. regulator-max-microvolt = <3300000>;
  42. };
  43. };
  44. &am33xx_pinmux {
  45. i2c0_pins: pinmux_i2c0_pins {
  46. pinctrl-single,pins = <
  47. AM33XX_PADCONF(AM335X_PIN_I2C0_SDA, PIN_INPUT_PULLUP, MUX_MODE0)
  48. AM33XX_PADCONF(AM335X_PIN_I2C0_SCL, PIN_INPUT_PULLUP, MUX_MODE0)
  49. >;
  50. };
  51. nandflash_pins: pinmux_nandflash_pins {
  52. pinctrl-single,pins = <
  53. AM33XX_PADCONF(AM335X_PIN_GPMC_AD0, PIN_INPUT_PULLUP, MUX_MODE0)
  54. AM33XX_PADCONF(AM335X_PIN_GPMC_AD1, PIN_INPUT_PULLUP, MUX_MODE0)
  55. AM33XX_PADCONF(AM335X_PIN_GPMC_AD2, PIN_INPUT_PULLUP, MUX_MODE0)
  56. AM33XX_PADCONF(AM335X_PIN_GPMC_AD3, PIN_INPUT_PULLUP, MUX_MODE0)
  57. AM33XX_PADCONF(AM335X_PIN_GPMC_AD4, PIN_INPUT_PULLUP, MUX_MODE0)
  58. AM33XX_PADCONF(AM335X_PIN_GPMC_AD5, PIN_INPUT_PULLUP, MUX_MODE0)
  59. AM33XX_PADCONF(AM335X_PIN_GPMC_AD6, PIN_INPUT_PULLUP, MUX_MODE0)
  60. AM33XX_PADCONF(AM335X_PIN_GPMC_AD7, PIN_INPUT_PULLUP, MUX_MODE0)
  61. AM33XX_PADCONF(AM335X_PIN_GPMC_WAIT0, PIN_INPUT_PULLUP, MUX_MODE0)
  62. AM33XX_PADCONF(AM335X_PIN_GPMC_WPN, PIN_INPUT_PULLUP, MUX_MODE7) /* gpmc_wpn.gpio0_31 */
  63. AM33XX_PADCONF(AM335X_PIN_GPMC_CSN0, PIN_OUTPUT, MUX_MODE0)
  64. AM33XX_PADCONF(AM335X_PIN_GPMC_ADVN_ALE, PIN_OUTPUT, MUX_MODE0)
  65. AM33XX_PADCONF(AM335X_PIN_GPMC_OEN_REN, PIN_OUTPUT, MUX_MODE0)
  66. AM33XX_PADCONF(AM335X_PIN_GPMC_WEN, PIN_OUTPUT, MUX_MODE0)
  67. AM33XX_PADCONF(AM335X_PIN_GPMC_BEN0_CLE, PIN_OUTPUT, MUX_MODE0)
  68. >;
  69. };
  70. uart0_pins: pinmux_uart0_pins {
  71. pinctrl-single,pins = <
  72. AM33XX_PADCONF(AM335X_PIN_UART0_RXD, PIN_INPUT_PULLUP, MUX_MODE0)
  73. AM33XX_PADCONF(AM335X_PIN_UART0_TXD, PIN_OUTPUT_PULLDOWN, MUX_MODE0)
  74. >;
  75. };
  76. leds_pins: pinmux_leds_pins {
  77. pinctrl-single,pins = <
  78. AM33XX_PADCONF(AM335X_PIN_GPMC_A7, PIN_OUTPUT_PULLDOWN, MUX_MODE7) /* gpmc_a7.gpio1_23 */
  79. >;
  80. };
  81. };
  82. &mac_sw {
  83. status = "okay";
  84. };
  85. &davinci_mdio_sw {
  86. ethphy0: ethernet-phy@0 {
  87. reg = <0>;
  88. };
  89. ethphy1: ethernet-phy@1 {
  90. reg = <1>;
  91. };
  92. };
  93. &cpsw_port1 {
  94. phy-handle = <&ethphy0>;
  95. phy-mode = "rmii";
  96. ti,dual-emac-pvid = <1>;
  97. };
  98. &cpsw_port2 {
  99. phy-handle = <&ethphy1>;
  100. phy-mode = "rmii";
  101. ti,dual-emac-pvid = <2>;
  102. };
  103. &elm {
  104. status = "okay";
  105. };
  106. &gpmc {
  107. status = "okay";
  108. pinctrl-names = "default";
  109. pinctrl-0 = <&nandflash_pins>;
  110. ranges = <0 0 0x08000000 0x1000000>; /* CS0: 16MB for NAND */
  111. nand@0,0 {
  112. compatible = "ti,omap2-nand";
  113. reg = <0 0 4>; /* CS0, offset 0, IO size 4 */
  114. interrupt-parent = <&gpmc>;
  115. interrupts = <0 IRQ_TYPE_NONE>, /* fifoevent */
  116. <1 IRQ_TYPE_NONE>; /* termcount */
  117. rb-gpios = <&gpmc 0 GPIO_ACTIVE_HIGH>; /* gpmc_wait0 */
  118. nand-bus-width = <8>;
  119. ti,nand-ecc-opt = "bch8";
  120. gpmc,device-width = <1>;
  121. gpmc,sync-clk-ps = <0>;
  122. gpmc,cs-on-ns = <0>;
  123. gpmc,cs-rd-off-ns = <44>;
  124. gpmc,cs-wr-off-ns = <44>;
  125. gpmc,adv-on-ns = <6>;
  126. gpmc,adv-rd-off-ns = <34>;
  127. gpmc,adv-wr-off-ns = <44>;
  128. gpmc,we-on-ns = <0>;
  129. gpmc,we-off-ns = <40>;
  130. gpmc,oe-on-ns = <0>;
  131. gpmc,oe-off-ns = <54>;
  132. gpmc,access-ns = <64>;
  133. gpmc,rd-cycle-ns = <82>;
  134. gpmc,wr-cycle-ns = <82>;
  135. gpmc,bus-turnaround-ns = <0>;
  136. gpmc,cycle2cycle-delay-ns = <0>;
  137. gpmc,clk-activation-ns = <0>;
  138. gpmc,wr-access-ns = <40>;
  139. gpmc,wr-data-mux-bus-ns = <0>;
  140. #address-cells = <1>;
  141. #size-cells = <1>;
  142. ti,elm-id = <&elm>;
  143. /* MTD partition table */
  144. partition@0 {
  145. label = "SPL";
  146. reg = <0x00000000 0x000080000>;
  147. };
  148. partition@1 {
  149. label = "U-boot";
  150. reg = <0x00080000 0x001e0000>;
  151. };
  152. partition@2 {
  153. label = "U-Boot Env";
  154. reg = <0x00260000 0x00020000>;
  155. };
  156. partition@3 {
  157. label = "Kernel";
  158. reg = <0x00280000 0x00500000>;
  159. };
  160. partition@4 {
  161. label = "File System";
  162. reg = <0x00780000 0x007880000>;
  163. };
  164. };
  165. };
  166. &i2c0 {
  167. status = "okay";
  168. pinctrl-names = "default";
  169. pinctrl-0 = <&i2c0_pins>;
  170. clock-frequency = <400000>;
  171. tps: tps@2d {
  172. reg = <0x2d>;
  173. };
  174. };
  175. &mmc1 {
  176. status = "okay";
  177. vmmc-supply = <&vmmc>;
  178. bus-width = <4>;
  179. };
  180. &uart0 {
  181. status = "okay";
  182. pinctrl-names = "default";
  183. pinctrl-0 = <&uart0_pins>;
  184. };
  185. &usb1 {
  186. dr_mode = "host";
  187. };
  188. #include "tps65910.dtsi"
  189. &tps {
  190. vcc1-supply = <&vbat>;
  191. vcc2-supply = <&vbat>;
  192. vcc3-supply = <&vbat>;
  193. vcc4-supply = <&vbat>;
  194. vcc5-supply = <&vbat>;
  195. vcc6-supply = <&vbat>;
  196. vcc7-supply = <&vbat>;
  197. vccio-supply = <&vbat>;
  198. regulators {
  199. vrtc_reg: regulator@0 {
  200. regulator-always-on;
  201. };
  202. vio_reg: regulator@1 {
  203. regulator-always-on;
  204. };
  205. vdd1_reg: regulator@2 {
  206. /* VDD_MPU voltage limits 0.95V - 1.26V with +/-4% tolerance */
  207. regulator-name = "vdd_mpu";
  208. regulator-min-microvolt = <912500>;
  209. regulator-max-microvolt = <1312500>;
  210. regulator-boot-on;
  211. regulator-always-on;
  212. };
  213. vdd2_reg: regulator@3 {
  214. /* VDD_CORE voltage limits 0.95V - 1.1V with +/-4% tolerance */
  215. regulator-name = "vdd_core";
  216. regulator-min-microvolt = <912500>;
  217. regulator-max-microvolt = <1150000>;
  218. regulator-boot-on;
  219. regulator-always-on;
  220. };
  221. vdd3_reg: regulator@4 {
  222. regulator-always-on;
  223. };
  224. vdig1_reg: regulator@5 {
  225. regulator-always-on;
  226. };
  227. vdig2_reg: regulator@6 {
  228. regulator-always-on;
  229. };
  230. vpll_reg: regulator@7 {
  231. regulator-always-on;
  232. };
  233. vdac_reg: regulator@8 {
  234. regulator-always-on;
  235. };
  236. vaux1_reg: regulator@9 {
  237. regulator-always-on;
  238. };
  239. vaux2_reg: regulator@10 {
  240. regulator-always-on;
  241. };
  242. vaux33_reg: regulator@11 {
  243. regulator-always-on;
  244. };
  245. vmmc_reg: regulator@12 {
  246. regulator-always-on;
  247. };
  248. };
  249. };