setup.c 16 KB

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  1. /*
  2. * arch/xtensa/kernel/setup.c
  3. *
  4. * This file is subject to the terms and conditions of the GNU General Public
  5. * License. See the file "COPYING" in the main directory of this archive
  6. * for more details.
  7. *
  8. * Copyright (C) 1995 Linus Torvalds
  9. * Copyright (C) 2001 - 2005 Tensilica Inc.
  10. * Copyright (C) 2014 - 2016 Cadence Design Systems Inc.
  11. *
  12. * Chris Zankel <[email protected]>
  13. * Joe Taylor <[email protected], [email protected]>
  14. * Kevin Chea
  15. * Marc Gauthier<[email protected]> <[email protected]>
  16. */
  17. #include <linux/errno.h>
  18. #include <linux/init.h>
  19. #include <linux/mm.h>
  20. #include <linux/proc_fs.h>
  21. #include <linux/screen_info.h>
  22. #include <linux/kernel.h>
  23. #include <linux/percpu.h>
  24. #include <linux/cpu.h>
  25. #include <linux/of.h>
  26. #include <linux/of_fdt.h>
  27. #if defined(CONFIG_VGA_CONSOLE) || defined(CONFIG_DUMMY_CONSOLE)
  28. # include <linux/console.h>
  29. #endif
  30. #ifdef CONFIG_PROC_FS
  31. # include <linux/seq_file.h>
  32. #endif
  33. #include <asm/bootparam.h>
  34. #include <asm/kasan.h>
  35. #include <asm/mmu_context.h>
  36. #include <asm/page.h>
  37. #include <asm/param.h>
  38. #include <asm/platform.h>
  39. #include <asm/processor.h>
  40. #include <asm/sections.h>
  41. #include <asm/setup.h>
  42. #include <asm/smp.h>
  43. #include <asm/sysmem.h>
  44. #include <asm/timex.h>
  45. #if defined(CONFIG_VGA_CONSOLE) || defined(CONFIG_DUMMY_CONSOLE)
  46. struct screen_info screen_info = {
  47. .orig_x = 0,
  48. .orig_y = 24,
  49. .orig_video_cols = 80,
  50. .orig_video_lines = 24,
  51. .orig_video_isVGA = 1,
  52. .orig_video_points = 16,
  53. };
  54. #endif
  55. #ifdef CONFIG_BLK_DEV_INITRD
  56. extern unsigned long initrd_start;
  57. extern unsigned long initrd_end;
  58. extern int initrd_below_start_ok;
  59. #endif
  60. #ifdef CONFIG_USE_OF
  61. void *dtb_start = __dtb_start;
  62. #endif
  63. extern unsigned long loops_per_jiffy;
  64. /* Command line specified as configuration option. */
  65. static char __initdata command_line[COMMAND_LINE_SIZE];
  66. #ifdef CONFIG_CMDLINE_BOOL
  67. static char default_command_line[COMMAND_LINE_SIZE] __initdata = CONFIG_CMDLINE;
  68. #endif
  69. #ifdef CONFIG_PARSE_BOOTPARAM
  70. /*
  71. * Boot parameter parsing.
  72. *
  73. * The Xtensa port uses a list of variable-sized tags to pass data to
  74. * the kernel. The first tag must be a BP_TAG_FIRST tag for the list
  75. * to be recognised. The list is terminated with a zero-sized
  76. * BP_TAG_LAST tag.
  77. */
  78. typedef struct tagtable {
  79. u32 tag;
  80. int (*parse)(const bp_tag_t*);
  81. } tagtable_t;
  82. #define __tagtable(tag, fn) static tagtable_t __tagtable_##fn \
  83. __section(".taglist") __attribute__((used)) = { tag, fn }
  84. /* parse current tag */
  85. static int __init parse_tag_mem(const bp_tag_t *tag)
  86. {
  87. struct bp_meminfo *mi = (struct bp_meminfo *)(tag->data);
  88. if (mi->type != MEMORY_TYPE_CONVENTIONAL)
  89. return -1;
  90. return memblock_add(mi->start, mi->end - mi->start);
  91. }
  92. __tagtable(BP_TAG_MEMORY, parse_tag_mem);
  93. #ifdef CONFIG_BLK_DEV_INITRD
  94. static int __init parse_tag_initrd(const bp_tag_t* tag)
  95. {
  96. struct bp_meminfo *mi = (struct bp_meminfo *)(tag->data);
  97. initrd_start = (unsigned long)__va(mi->start);
  98. initrd_end = (unsigned long)__va(mi->end);
  99. return 0;
  100. }
  101. __tagtable(BP_TAG_INITRD, parse_tag_initrd);
  102. #endif /* CONFIG_BLK_DEV_INITRD */
  103. #ifdef CONFIG_USE_OF
  104. static int __init parse_tag_fdt(const bp_tag_t *tag)
  105. {
  106. dtb_start = __va(tag->data[0]);
  107. return 0;
  108. }
  109. __tagtable(BP_TAG_FDT, parse_tag_fdt);
  110. #endif /* CONFIG_USE_OF */
  111. static int __init parse_tag_cmdline(const bp_tag_t* tag)
  112. {
  113. strscpy(command_line, (char *)(tag->data), COMMAND_LINE_SIZE);
  114. return 0;
  115. }
  116. __tagtable(BP_TAG_COMMAND_LINE, parse_tag_cmdline);
  117. static int __init parse_bootparam(const bp_tag_t* tag)
  118. {
  119. extern tagtable_t __tagtable_begin, __tagtable_end;
  120. tagtable_t *t;
  121. /* Boot parameters must start with a BP_TAG_FIRST tag. */
  122. if (tag->id != BP_TAG_FIRST) {
  123. pr_warn("Invalid boot parameters!\n");
  124. return 0;
  125. }
  126. tag = (bp_tag_t*)((unsigned long)tag + sizeof(bp_tag_t) + tag->size);
  127. /* Parse all tags. */
  128. while (tag != NULL && tag->id != BP_TAG_LAST) {
  129. for (t = &__tagtable_begin; t < &__tagtable_end; t++) {
  130. if (tag->id == t->tag) {
  131. t->parse(tag);
  132. break;
  133. }
  134. }
  135. if (t == &__tagtable_end)
  136. pr_warn("Ignoring tag 0x%08x\n", tag->id);
  137. tag = (bp_tag_t*)((unsigned long)(tag + 1) + tag->size);
  138. }
  139. return 0;
  140. }
  141. #else
  142. static int __init parse_bootparam(const bp_tag_t *tag)
  143. {
  144. pr_info("Ignoring boot parameters at %p\n", tag);
  145. return 0;
  146. }
  147. #endif
  148. #ifdef CONFIG_USE_OF
  149. #if !XCHAL_HAVE_PTP_MMU || XCHAL_HAVE_SPANNING_WAY
  150. unsigned long xtensa_kio_paddr = XCHAL_KIO_DEFAULT_PADDR;
  151. EXPORT_SYMBOL(xtensa_kio_paddr);
  152. static int __init xtensa_dt_io_area(unsigned long node, const char *uname,
  153. int depth, void *data)
  154. {
  155. const __be32 *ranges;
  156. int len;
  157. if (depth > 1)
  158. return 0;
  159. if (!of_flat_dt_is_compatible(node, "simple-bus"))
  160. return 0;
  161. ranges = of_get_flat_dt_prop(node, "ranges", &len);
  162. if (!ranges)
  163. return 1;
  164. if (len == 0)
  165. return 1;
  166. xtensa_kio_paddr = of_read_ulong(ranges+1, 1);
  167. /* round down to nearest 256MB boundary */
  168. xtensa_kio_paddr &= 0xf0000000;
  169. init_kio();
  170. return 1;
  171. }
  172. #else
  173. static int __init xtensa_dt_io_area(unsigned long node, const char *uname,
  174. int depth, void *data)
  175. {
  176. return 1;
  177. }
  178. #endif
  179. void __init early_init_devtree(void *params)
  180. {
  181. early_init_dt_scan(params);
  182. of_scan_flat_dt(xtensa_dt_io_area, NULL);
  183. if (!command_line[0])
  184. strscpy(command_line, boot_command_line, COMMAND_LINE_SIZE);
  185. }
  186. #endif /* CONFIG_USE_OF */
  187. /*
  188. * Initialize architecture. (Early stage)
  189. */
  190. void __init init_arch(bp_tag_t *bp_start)
  191. {
  192. /* Initialize MMU. */
  193. init_mmu();
  194. /* Initialize initial KASAN shadow map */
  195. kasan_early_init();
  196. /* Parse boot parameters */
  197. if (bp_start)
  198. parse_bootparam(bp_start);
  199. #ifdef CONFIG_USE_OF
  200. early_init_devtree(dtb_start);
  201. #endif
  202. #ifdef CONFIG_CMDLINE_BOOL
  203. if (!command_line[0])
  204. strscpy(command_line, default_command_line, COMMAND_LINE_SIZE);
  205. #endif
  206. /* Early hook for platforms */
  207. platform_init(bp_start);
  208. }
  209. /*
  210. * Initialize system. Setup memory and reserve regions.
  211. */
  212. static inline int __init_memblock mem_reserve(unsigned long start,
  213. unsigned long end)
  214. {
  215. return memblock_reserve(start, end - start);
  216. }
  217. void __init setup_arch(char **cmdline_p)
  218. {
  219. pr_info("config ID: %08x:%08x\n",
  220. xtensa_get_sr(SREG_EPC), xtensa_get_sr(SREG_EXCSAVE));
  221. if (xtensa_get_sr(SREG_EPC) != XCHAL_HW_CONFIGID0 ||
  222. xtensa_get_sr(SREG_EXCSAVE) != XCHAL_HW_CONFIGID1)
  223. pr_info("built for config ID: %08x:%08x\n",
  224. XCHAL_HW_CONFIGID0, XCHAL_HW_CONFIGID1);
  225. *cmdline_p = command_line;
  226. platform_setup(cmdline_p);
  227. strscpy(boot_command_line, *cmdline_p, COMMAND_LINE_SIZE);
  228. /* Reserve some memory regions */
  229. #ifdef CONFIG_BLK_DEV_INITRD
  230. if (initrd_start < initrd_end &&
  231. !mem_reserve(__pa(initrd_start), __pa(initrd_end)))
  232. initrd_below_start_ok = 1;
  233. else
  234. initrd_start = 0;
  235. #endif
  236. mem_reserve(__pa(_stext), __pa(_end));
  237. #ifdef CONFIG_XIP_KERNEL
  238. mem_reserve(__pa(_xip_start), __pa(_xip_end));
  239. #endif
  240. #ifdef CONFIG_VECTORS_ADDR
  241. #ifdef SUPPORT_WINDOWED
  242. mem_reserve(__pa(_WindowVectors_text_start),
  243. __pa(_WindowVectors_text_end));
  244. #endif
  245. mem_reserve(__pa(_DebugInterruptVector_text_start),
  246. __pa(_DebugInterruptVector_text_end));
  247. mem_reserve(__pa(_KernelExceptionVector_text_start),
  248. __pa(_KernelExceptionVector_text_end));
  249. mem_reserve(__pa(_UserExceptionVector_text_start),
  250. __pa(_UserExceptionVector_text_end));
  251. mem_reserve(__pa(_DoubleExceptionVector_text_start),
  252. __pa(_DoubleExceptionVector_text_end));
  253. mem_reserve(__pa(_exception_text_start),
  254. __pa(_exception_text_end));
  255. #if XCHAL_EXCM_LEVEL >= 2
  256. mem_reserve(__pa(_Level2InterruptVector_text_start),
  257. __pa(_Level2InterruptVector_text_end));
  258. #endif
  259. #if XCHAL_EXCM_LEVEL >= 3
  260. mem_reserve(__pa(_Level3InterruptVector_text_start),
  261. __pa(_Level3InterruptVector_text_end));
  262. #endif
  263. #if XCHAL_EXCM_LEVEL >= 4
  264. mem_reserve(__pa(_Level4InterruptVector_text_start),
  265. __pa(_Level4InterruptVector_text_end));
  266. #endif
  267. #if XCHAL_EXCM_LEVEL >= 5
  268. mem_reserve(__pa(_Level5InterruptVector_text_start),
  269. __pa(_Level5InterruptVector_text_end));
  270. #endif
  271. #if XCHAL_EXCM_LEVEL >= 6
  272. mem_reserve(__pa(_Level6InterruptVector_text_start),
  273. __pa(_Level6InterruptVector_text_end));
  274. #endif
  275. #endif /* CONFIG_VECTORS_ADDR */
  276. #ifdef CONFIG_SECONDARY_RESET_VECTOR
  277. mem_reserve(__pa(_SecondaryResetVector_text_start),
  278. __pa(_SecondaryResetVector_text_end));
  279. #endif
  280. parse_early_param();
  281. bootmem_init();
  282. kasan_init();
  283. unflatten_and_copy_device_tree();
  284. #ifdef CONFIG_SMP
  285. smp_init_cpus();
  286. #endif
  287. paging_init();
  288. zones_init();
  289. #ifdef CONFIG_VT
  290. # if defined(CONFIG_VGA_CONSOLE)
  291. conswitchp = &vga_con;
  292. # endif
  293. #endif
  294. }
  295. static DEFINE_PER_CPU(struct cpu, cpu_data);
  296. static int __init topology_init(void)
  297. {
  298. int i;
  299. for_each_possible_cpu(i) {
  300. struct cpu *cpu = &per_cpu(cpu_data, i);
  301. cpu->hotpluggable = !!i;
  302. register_cpu(cpu, i);
  303. }
  304. return 0;
  305. }
  306. subsys_initcall(topology_init);
  307. void cpu_reset(void)
  308. {
  309. #if XCHAL_HAVE_PTP_MMU && IS_ENABLED(CONFIG_MMU)
  310. local_irq_disable();
  311. /*
  312. * We have full MMU: all autoload ways, ways 7, 8 and 9 of DTLB must
  313. * be flushed.
  314. * Way 4 is not currently used by linux.
  315. * Ways 5 and 6 shall not be touched on MMUv2 as they are hardwired.
  316. * Way 5 shall be flushed and way 6 shall be set to identity mapping
  317. * on MMUv3.
  318. */
  319. local_flush_tlb_all();
  320. invalidate_page_directory();
  321. #if XCHAL_HAVE_SPANNING_WAY
  322. /* MMU v3 */
  323. {
  324. unsigned long vaddr = (unsigned long)cpu_reset;
  325. unsigned long paddr = __pa(vaddr);
  326. unsigned long tmpaddr = vaddr + SZ_512M;
  327. unsigned long tmp0, tmp1, tmp2, tmp3;
  328. /*
  329. * Find a place for the temporary mapping. It must not be
  330. * in the same 512MB region with vaddr or paddr, otherwise
  331. * there may be multihit exception either on entry to the
  332. * temporary mapping, or on entry to the identity mapping.
  333. * (512MB is the biggest page size supported by TLB.)
  334. */
  335. while (((tmpaddr ^ paddr) & -SZ_512M) == 0)
  336. tmpaddr += SZ_512M;
  337. /* Invalidate mapping in the selected temporary area */
  338. if (itlb_probe(tmpaddr) & BIT(ITLB_HIT_BIT))
  339. invalidate_itlb_entry(itlb_probe(tmpaddr));
  340. if (itlb_probe(tmpaddr + PAGE_SIZE) & BIT(ITLB_HIT_BIT))
  341. invalidate_itlb_entry(itlb_probe(tmpaddr + PAGE_SIZE));
  342. /*
  343. * Map two consecutive pages starting at the physical address
  344. * of this function to the temporary mapping area.
  345. */
  346. write_itlb_entry(__pte((paddr & PAGE_MASK) |
  347. _PAGE_HW_VALID |
  348. _PAGE_HW_EXEC |
  349. _PAGE_CA_BYPASS),
  350. tmpaddr & PAGE_MASK);
  351. write_itlb_entry(__pte(((paddr & PAGE_MASK) + PAGE_SIZE) |
  352. _PAGE_HW_VALID |
  353. _PAGE_HW_EXEC |
  354. _PAGE_CA_BYPASS),
  355. (tmpaddr & PAGE_MASK) + PAGE_SIZE);
  356. /* Reinitialize TLB */
  357. __asm__ __volatile__ ("movi %0, 1f\n\t"
  358. "movi %3, 2f\n\t"
  359. "add %0, %0, %4\n\t"
  360. "add %3, %3, %5\n\t"
  361. "jx %0\n"
  362. /*
  363. * No literal, data or stack access
  364. * below this point
  365. */
  366. "1:\n\t"
  367. /* Initialize *tlbcfg */
  368. "movi %0, 0\n\t"
  369. "wsr %0, itlbcfg\n\t"
  370. "wsr %0, dtlbcfg\n\t"
  371. /* Invalidate TLB way 5 */
  372. "movi %0, 4\n\t"
  373. "movi %1, 5\n"
  374. "1:\n\t"
  375. "iitlb %1\n\t"
  376. "idtlb %1\n\t"
  377. "add %1, %1, %6\n\t"
  378. "addi %0, %0, -1\n\t"
  379. "bnez %0, 1b\n\t"
  380. /* Initialize TLB way 6 */
  381. "movi %0, 7\n\t"
  382. "addi %1, %9, 3\n\t"
  383. "addi %2, %9, 6\n"
  384. "1:\n\t"
  385. "witlb %1, %2\n\t"
  386. "wdtlb %1, %2\n\t"
  387. "add %1, %1, %7\n\t"
  388. "add %2, %2, %7\n\t"
  389. "addi %0, %0, -1\n\t"
  390. "bnez %0, 1b\n\t"
  391. "isync\n\t"
  392. /* Jump to identity mapping */
  393. "jx %3\n"
  394. "2:\n\t"
  395. /* Complete way 6 initialization */
  396. "witlb %1, %2\n\t"
  397. "wdtlb %1, %2\n\t"
  398. /* Invalidate temporary mapping */
  399. "sub %0, %9, %7\n\t"
  400. "iitlb %0\n\t"
  401. "add %0, %0, %8\n\t"
  402. "iitlb %0"
  403. : "=&a"(tmp0), "=&a"(tmp1), "=&a"(tmp2),
  404. "=&a"(tmp3)
  405. : "a"(tmpaddr - vaddr),
  406. "a"(paddr - vaddr),
  407. "a"(SZ_128M), "a"(SZ_512M),
  408. "a"(PAGE_SIZE),
  409. "a"((tmpaddr + SZ_512M) & PAGE_MASK)
  410. : "memory");
  411. }
  412. #endif
  413. #endif
  414. __asm__ __volatile__ ("movi a2, 0\n\t"
  415. "wsr a2, icountlevel\n\t"
  416. "movi a2, 0\n\t"
  417. "wsr a2, icount\n\t"
  418. #if XCHAL_NUM_IBREAK > 0
  419. "wsr a2, ibreakenable\n\t"
  420. #endif
  421. #if XCHAL_HAVE_LOOPS
  422. "wsr a2, lcount\n\t"
  423. #endif
  424. "movi a2, 0x1f\n\t"
  425. "wsr a2, ps\n\t"
  426. "isync\n\t"
  427. "jx %0\n\t"
  428. :
  429. : "a" (XCHAL_RESET_VECTOR_VADDR)
  430. : "a2");
  431. for (;;)
  432. ;
  433. }
  434. void machine_restart(char * cmd)
  435. {
  436. platform_restart();
  437. }
  438. void machine_halt(void)
  439. {
  440. platform_halt();
  441. while (1);
  442. }
  443. void machine_power_off(void)
  444. {
  445. platform_power_off();
  446. while (1);
  447. }
  448. #ifdef CONFIG_PROC_FS
  449. /*
  450. * Display some core information through /proc/cpuinfo.
  451. */
  452. static int
  453. c_show(struct seq_file *f, void *slot)
  454. {
  455. /* high-level stuff */
  456. seq_printf(f, "CPU count\t: %u\n"
  457. "CPU list\t: %*pbl\n"
  458. "vendor_id\t: Tensilica\n"
  459. "model\t\t: Xtensa " XCHAL_HW_VERSION_NAME "\n"
  460. "core ID\t\t: " XCHAL_CORE_ID "\n"
  461. "build ID\t: 0x%x\n"
  462. "config ID\t: %08x:%08x\n"
  463. "byte order\t: %s\n"
  464. "cpu MHz\t\t: %lu.%02lu\n"
  465. "bogomips\t: %lu.%02lu\n",
  466. num_online_cpus(),
  467. cpumask_pr_args(cpu_online_mask),
  468. XCHAL_BUILD_UNIQUE_ID,
  469. xtensa_get_sr(SREG_EPC), xtensa_get_sr(SREG_EXCSAVE),
  470. XCHAL_HAVE_BE ? "big" : "little",
  471. ccount_freq/1000000,
  472. (ccount_freq/10000) % 100,
  473. loops_per_jiffy/(500000/HZ),
  474. (loops_per_jiffy/(5000/HZ)) % 100);
  475. seq_puts(f, "flags\t\t: "
  476. #if XCHAL_HAVE_NMI
  477. "nmi "
  478. #endif
  479. #if XCHAL_HAVE_DEBUG
  480. "debug "
  481. # if XCHAL_HAVE_OCD
  482. "ocd "
  483. # endif
  484. #endif
  485. #if XCHAL_HAVE_DENSITY
  486. "density "
  487. #endif
  488. #if XCHAL_HAVE_BOOLEANS
  489. "boolean "
  490. #endif
  491. #if XCHAL_HAVE_LOOPS
  492. "loop "
  493. #endif
  494. #if XCHAL_HAVE_NSA
  495. "nsa "
  496. #endif
  497. #if XCHAL_HAVE_MINMAX
  498. "minmax "
  499. #endif
  500. #if XCHAL_HAVE_SEXT
  501. "sext "
  502. #endif
  503. #if XCHAL_HAVE_CLAMPS
  504. "clamps "
  505. #endif
  506. #if XCHAL_HAVE_MAC16
  507. "mac16 "
  508. #endif
  509. #if XCHAL_HAVE_MUL16
  510. "mul16 "
  511. #endif
  512. #if XCHAL_HAVE_MUL32
  513. "mul32 "
  514. #endif
  515. #if XCHAL_HAVE_MUL32_HIGH
  516. "mul32h "
  517. #endif
  518. #if XCHAL_HAVE_FP
  519. "fpu "
  520. #endif
  521. #if XCHAL_HAVE_S32C1I
  522. "s32c1i "
  523. #endif
  524. #if XCHAL_HAVE_EXCLUSIVE
  525. "exclusive "
  526. #endif
  527. "\n");
  528. /* Registers. */
  529. seq_printf(f,"physical aregs\t: %d\n"
  530. "misc regs\t: %d\n"
  531. "ibreak\t\t: %d\n"
  532. "dbreak\t\t: %d\n",
  533. XCHAL_NUM_AREGS,
  534. XCHAL_NUM_MISC_REGS,
  535. XCHAL_NUM_IBREAK,
  536. XCHAL_NUM_DBREAK);
  537. /* Interrupt. */
  538. seq_printf(f,"num ints\t: %d\n"
  539. "ext ints\t: %d\n"
  540. "int levels\t: %d\n"
  541. "timers\t\t: %d\n"
  542. "debug level\t: %d\n",
  543. XCHAL_NUM_INTERRUPTS,
  544. XCHAL_NUM_EXTINTERRUPTS,
  545. XCHAL_NUM_INTLEVELS,
  546. XCHAL_NUM_TIMERS,
  547. XCHAL_DEBUGLEVEL);
  548. /* Cache */
  549. seq_printf(f,"icache line size: %d\n"
  550. "icache ways\t: %d\n"
  551. "icache size\t: %d\n"
  552. "icache flags\t: "
  553. #if XCHAL_ICACHE_LINE_LOCKABLE
  554. "lock "
  555. #endif
  556. "\n"
  557. "dcache line size: %d\n"
  558. "dcache ways\t: %d\n"
  559. "dcache size\t: %d\n"
  560. "dcache flags\t: "
  561. #if XCHAL_DCACHE_IS_WRITEBACK
  562. "writeback "
  563. #endif
  564. #if XCHAL_DCACHE_LINE_LOCKABLE
  565. "lock "
  566. #endif
  567. "\n",
  568. XCHAL_ICACHE_LINESIZE,
  569. XCHAL_ICACHE_WAYS,
  570. XCHAL_ICACHE_SIZE,
  571. XCHAL_DCACHE_LINESIZE,
  572. XCHAL_DCACHE_WAYS,
  573. XCHAL_DCACHE_SIZE);
  574. return 0;
  575. }
  576. /*
  577. * We show only CPU #0 info.
  578. */
  579. static void *
  580. c_start(struct seq_file *f, loff_t *pos)
  581. {
  582. return (*pos == 0) ? (void *)1 : NULL;
  583. }
  584. static void *
  585. c_next(struct seq_file *f, void *v, loff_t *pos)
  586. {
  587. ++*pos;
  588. return c_start(f, pos);
  589. }
  590. static void
  591. c_stop(struct seq_file *f, void *v)
  592. {
  593. }
  594. const struct seq_operations cpuinfo_op =
  595. {
  596. .start = c_start,
  597. .next = c_next,
  598. .stop = c_stop,
  599. .show = c_show,
  600. };
  601. #endif /* CONFIG_PROC_FS */