irq.c 4.6 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194
  1. // SPDX-License-Identifier: GPL-2.0
  2. /*
  3. * linux/arch/xtensa/kernel/irq.c
  4. *
  5. * Xtensa built-in interrupt controller and some generic functions copied
  6. * from i386.
  7. *
  8. * Copyright (C) 2002 - 2013 Tensilica, Inc.
  9. * Copyright (C) 1992, 1998 Linus Torvalds, Ingo Molnar
  10. *
  11. *
  12. * Chris Zankel <[email protected]>
  13. * Kevin Chea
  14. *
  15. */
  16. #include <linux/module.h>
  17. #include <linux/seq_file.h>
  18. #include <linux/interrupt.h>
  19. #include <linux/irq.h>
  20. #include <linux/kernel_stat.h>
  21. #include <linux/irqchip.h>
  22. #include <linux/irqchip/xtensa-mx.h>
  23. #include <linux/irqchip/xtensa-pic.h>
  24. #include <linux/irqdomain.h>
  25. #include <linux/of.h>
  26. #include <asm/mxregs.h>
  27. #include <linux/uaccess.h>
  28. #include <asm/platform.h>
  29. DECLARE_PER_CPU(unsigned long, nmi_count);
  30. asmlinkage void do_IRQ(int hwirq, struct pt_regs *regs)
  31. {
  32. #ifdef CONFIG_DEBUG_STACKOVERFLOW
  33. /* Debugging check for stack overflow: is there less than 1KB free? */
  34. {
  35. unsigned long sp = current_stack_pointer;
  36. sp &= THREAD_SIZE - 1;
  37. if (unlikely(sp < (sizeof(thread_info) + 1024)))
  38. printk("Stack overflow in do_IRQ: %ld\n",
  39. sp - sizeof(struct thread_info));
  40. }
  41. #endif
  42. generic_handle_domain_irq(NULL, hwirq);
  43. }
  44. int arch_show_interrupts(struct seq_file *p, int prec)
  45. {
  46. unsigned cpu __maybe_unused;
  47. #ifdef CONFIG_SMP
  48. show_ipi_list(p, prec);
  49. #endif
  50. #if XTENSA_FAKE_NMI
  51. seq_printf(p, "%*s:", prec, "NMI");
  52. for_each_online_cpu(cpu)
  53. seq_printf(p, " %10lu", per_cpu(nmi_count, cpu));
  54. seq_puts(p, " Non-maskable interrupts\n");
  55. #endif
  56. return 0;
  57. }
  58. int xtensa_irq_domain_xlate(const u32 *intspec, unsigned int intsize,
  59. unsigned long int_irq, unsigned long ext_irq,
  60. unsigned long *out_hwirq, unsigned int *out_type)
  61. {
  62. if (WARN_ON(intsize < 1 || intsize > 2))
  63. return -EINVAL;
  64. if (intsize == 2 && intspec[1] == 1) {
  65. int_irq = xtensa_map_ext_irq(ext_irq);
  66. if (int_irq < XCHAL_NUM_INTERRUPTS)
  67. *out_hwirq = int_irq;
  68. else
  69. return -EINVAL;
  70. } else {
  71. *out_hwirq = int_irq;
  72. }
  73. *out_type = IRQ_TYPE_NONE;
  74. return 0;
  75. }
  76. int xtensa_irq_map(struct irq_domain *d, unsigned int irq,
  77. irq_hw_number_t hw)
  78. {
  79. struct irq_chip *irq_chip = d->host_data;
  80. u32 mask = 1 << hw;
  81. if (mask & XCHAL_INTTYPE_MASK_SOFTWARE) {
  82. irq_set_chip_and_handler_name(irq, irq_chip,
  83. handle_simple_irq, "level");
  84. irq_set_status_flags(irq, IRQ_LEVEL);
  85. } else if (mask & XCHAL_INTTYPE_MASK_EXTERN_EDGE) {
  86. irq_set_chip_and_handler_name(irq, irq_chip,
  87. handle_edge_irq, "edge");
  88. irq_clear_status_flags(irq, IRQ_LEVEL);
  89. } else if (mask & XCHAL_INTTYPE_MASK_EXTERN_LEVEL) {
  90. irq_set_chip_and_handler_name(irq, irq_chip,
  91. handle_level_irq, "level");
  92. irq_set_status_flags(irq, IRQ_LEVEL);
  93. } else if (mask & XCHAL_INTTYPE_MASK_TIMER) {
  94. irq_set_chip_and_handler_name(irq, irq_chip,
  95. handle_percpu_irq, "timer");
  96. irq_clear_status_flags(irq, IRQ_LEVEL);
  97. #ifdef XCHAL_INTTYPE_MASK_PROFILING
  98. } else if (mask & XCHAL_INTTYPE_MASK_PROFILING) {
  99. irq_set_chip_and_handler_name(irq, irq_chip,
  100. handle_percpu_irq, "profiling");
  101. irq_set_status_flags(irq, IRQ_LEVEL);
  102. #endif
  103. } else {/* XCHAL_INTTYPE_MASK_WRITE_ERROR */
  104. /* XCHAL_INTTYPE_MASK_NMI */
  105. irq_set_chip_and_handler_name(irq, irq_chip,
  106. handle_level_irq, "level");
  107. irq_set_status_flags(irq, IRQ_LEVEL);
  108. }
  109. return 0;
  110. }
  111. unsigned xtensa_map_ext_irq(unsigned ext_irq)
  112. {
  113. unsigned mask = XCHAL_INTTYPE_MASK_EXTERN_EDGE |
  114. XCHAL_INTTYPE_MASK_EXTERN_LEVEL;
  115. unsigned i;
  116. for (i = 0; mask; ++i, mask >>= 1) {
  117. if ((mask & 1) && ext_irq-- == 0)
  118. return i;
  119. }
  120. return XCHAL_NUM_INTERRUPTS;
  121. }
  122. unsigned xtensa_get_ext_irq_no(unsigned irq)
  123. {
  124. unsigned mask = (XCHAL_INTTYPE_MASK_EXTERN_EDGE |
  125. XCHAL_INTTYPE_MASK_EXTERN_LEVEL) &
  126. ((1u << irq) - 1);
  127. return hweight32(mask);
  128. }
  129. void __init init_IRQ(void)
  130. {
  131. #ifdef CONFIG_USE_OF
  132. irqchip_init();
  133. #else
  134. #ifdef CONFIG_HAVE_SMP
  135. xtensa_mx_init_legacy(NULL);
  136. #else
  137. xtensa_pic_init_legacy(NULL);
  138. #endif
  139. #endif
  140. #ifdef CONFIG_SMP
  141. ipi_init();
  142. #endif
  143. }
  144. #ifdef CONFIG_HOTPLUG_CPU
  145. /*
  146. * The CPU has been marked offline. Migrate IRQs off this CPU. If
  147. * the affinity settings do not allow other CPUs, force them onto any
  148. * available CPU.
  149. */
  150. void migrate_irqs(void)
  151. {
  152. unsigned int i, cpu = smp_processor_id();
  153. for_each_active_irq(i) {
  154. struct irq_data *data = irq_get_irq_data(i);
  155. const struct cpumask *mask;
  156. unsigned int newcpu;
  157. if (irqd_is_per_cpu(data))
  158. continue;
  159. mask = irq_data_get_affinity_mask(data);
  160. if (!cpumask_test_cpu(cpu, mask))
  161. continue;
  162. newcpu = cpumask_any_and(mask, cpu_online_mask);
  163. if (newcpu >= nr_cpu_ids) {
  164. pr_info_ratelimited("IRQ%u no longer affine to CPU%u\n",
  165. i, cpu);
  166. irq_set_affinity(i, cpu_all_mask);
  167. } else {
  168. irq_set_affinity(i, mask);
  169. }
  170. }
  171. }
  172. #endif /* CONFIG_HOTPLUG_CPU */