head.S 7.0 KB

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  1. /*
  2. * arch/xtensa/kernel/head.S
  3. *
  4. * Xtensa Processor startup code.
  5. *
  6. * This file is subject to the terms and conditions of the GNU General Public
  7. * License. See the file "COPYING" in the main directory of this archive
  8. * for more details.
  9. *
  10. * Copyright (C) 2001 - 2008 Tensilica Inc.
  11. *
  12. * Chris Zankel <[email protected]>
  13. * Marc Gauthier <[email protected], [email protected]>
  14. * Joe Taylor <[email protected], [email protected]>
  15. * Kevin Chea
  16. */
  17. #include <asm/asmmacro.h>
  18. #include <asm/processor.h>
  19. #include <asm/page.h>
  20. #include <asm/cacheasm.h>
  21. #include <asm/initialize_mmu.h>
  22. #include <asm/mxregs.h>
  23. #include <linux/init.h>
  24. #include <linux/linkage.h>
  25. /*
  26. * This module contains the entry code for kernel images. It performs the
  27. * minimal setup needed to call the generic C routines.
  28. *
  29. * Prerequisites:
  30. *
  31. * - The kernel image has been loaded to the actual address where it was
  32. * compiled to.
  33. * - a2 contains either 0 or a pointer to a list of boot parameters.
  34. * (see setup.c for more details)
  35. *
  36. */
  37. /*
  38. * _start
  39. *
  40. * The bootloader passes a pointer to a list of boot parameters in a2.
  41. */
  42. /* The first bytes of the kernel image must be an instruction, so we
  43. * manually allocate and define the literal constant we need for a jx
  44. * instruction.
  45. */
  46. __HEAD
  47. .begin no-absolute-literals
  48. ENTRY(_start)
  49. /* Preserve the pointer to the boot parameter list in EXCSAVE_1 */
  50. wsr a2, excsave1
  51. _j _SetupOCD
  52. .align 4
  53. .literal_position
  54. _SetupOCD:
  55. /*
  56. * Initialize WB, WS, and clear PS.EXCM (to allow loop instructions).
  57. * Set Interrupt Level just below XCHAL_DEBUGLEVEL to allow
  58. * xt-gdb to single step via DEBUG exceptions received directly
  59. * by ocd.
  60. */
  61. #if XCHAL_HAVE_WINDOWED
  62. movi a1, 1
  63. movi a0, 0
  64. wsr a1, windowstart
  65. wsr a0, windowbase
  66. rsync
  67. #endif
  68. movi a1, LOCKLEVEL
  69. wsr a1, ps
  70. rsync
  71. .global _SetupMMU
  72. _SetupMMU:
  73. Offset = _SetupMMU - _start
  74. #ifdef CONFIG_INITIALIZE_XTENSA_MMU_INSIDE_VMLINUX
  75. initialize_mmu
  76. #if defined(CONFIG_MMU) && XCHAL_HAVE_PTP_MMU && XCHAL_HAVE_SPANNING_WAY
  77. rsr a2, excsave1
  78. movi a3, XCHAL_KSEG_PADDR
  79. bltu a2, a3, 1f
  80. sub a2, a2, a3
  81. movi a3, XCHAL_KSEG_SIZE
  82. bgeu a2, a3, 1f
  83. movi a3, XCHAL_KSEG_CACHED_VADDR
  84. add a2, a2, a3
  85. wsr a2, excsave1
  86. 1:
  87. #endif
  88. #endif
  89. movi a0, _startup
  90. jx a0
  91. ENDPROC(_start)
  92. .end no-absolute-literals
  93. __REF
  94. .literal_position
  95. ENTRY(_startup)
  96. /* Set a0 to 0 for the remaining initialization. */
  97. movi a0, 0
  98. #if XCHAL_HAVE_VECBASE
  99. movi a2, VECBASE_VADDR
  100. wsr a2, vecbase
  101. #endif
  102. /* Clear debugging registers. */
  103. #if XCHAL_HAVE_DEBUG
  104. #if XCHAL_NUM_IBREAK > 0
  105. wsr a0, ibreakenable
  106. #endif
  107. wsr a0, icount
  108. movi a1, 15
  109. wsr a0, icountlevel
  110. .set _index, 0
  111. .rept XCHAL_NUM_DBREAK
  112. wsr a0, SREG_DBREAKC + _index
  113. .set _index, _index + 1
  114. .endr
  115. #endif
  116. /* Clear CCOUNT (not really necessary, but nice) */
  117. wsr a0, ccount # not really necessary, but nice
  118. /* Disable zero-loops. */
  119. #if XCHAL_HAVE_LOOPS
  120. wsr a0, lcount
  121. #endif
  122. /* Disable all timers. */
  123. .set _index, 0
  124. .rept XCHAL_NUM_TIMERS
  125. wsr a0, SREG_CCOMPARE + _index
  126. .set _index, _index + 1
  127. .endr
  128. /* Interrupt initialization. */
  129. movi a2, XCHAL_INTTYPE_MASK_SOFTWARE | XCHAL_INTTYPE_MASK_EXTERN_EDGE
  130. wsr a0, intenable
  131. wsr a2, intclear
  132. /* Disable coprocessors. */
  133. #if XCHAL_HAVE_CP
  134. wsr a0, cpenable
  135. #endif
  136. /* Initialize the caches.
  137. * a2, a3 are just working registers (clobbered).
  138. */
  139. #if XCHAL_DCACHE_LINE_LOCKABLE
  140. ___unlock_dcache_all a2 a3
  141. #endif
  142. #if XCHAL_ICACHE_LINE_LOCKABLE
  143. ___unlock_icache_all a2 a3
  144. #endif
  145. ___invalidate_dcache_all a2 a3
  146. ___invalidate_icache_all a2 a3
  147. isync
  148. initialize_cacheattr
  149. #ifdef CONFIG_HAVE_SMP
  150. movi a2, CCON # MX External Register to Configure Cache
  151. movi a3, 1
  152. wer a3, a2
  153. #endif
  154. /* Setup stack and enable window exceptions (keep irqs disabled) */
  155. movi a1, start_info
  156. l32i a1, a1, 0
  157. /* Disable interrupts. */
  158. /* Enable window exceptions if kernel is built with windowed ABI. */
  159. movi a2, KERNEL_PS_WOE_MASK | LOCKLEVEL
  160. wsr a2, ps
  161. rsync
  162. #ifdef CONFIG_SMP
  163. /*
  164. * Notice that we assume with SMP that cores have PRID
  165. * supported by the cores.
  166. */
  167. rsr a2, prid
  168. bnez a2, .Lboot_secondary
  169. #endif /* CONFIG_SMP */
  170. /* Unpack data sections
  171. *
  172. * The linker script used to build the Linux kernel image
  173. * creates a table located at __boot_reloc_table_start
  174. * that contains the information what data needs to be unpacked.
  175. *
  176. * Uses a2-a7.
  177. */
  178. movi a2, __boot_reloc_table_start
  179. movi a3, __boot_reloc_table_end
  180. 1: beq a2, a3, 3f # no more entries?
  181. l32i a4, a2, 0 # start destination (in RAM)
  182. l32i a5, a2, 4 # end destination (in RAM)
  183. l32i a6, a2, 8 # start source (in ROM)
  184. addi a2, a2, 12 # next entry
  185. beq a4, a5, 1b # skip, empty entry
  186. beq a4, a6, 1b # skip, source and dest. are the same
  187. 2: l32i a7, a6, 0 # load word
  188. addi a6, a6, 4
  189. s32i a7, a4, 0 # store word
  190. addi a4, a4, 4
  191. bltu a4, a5, 2b
  192. j 1b
  193. 3:
  194. /* All code and initialized data segments have been copied.
  195. * Now clear the BSS segment.
  196. */
  197. movi a2, __bss_start # start of BSS
  198. movi a3, __bss_stop # end of BSS
  199. __loopt a2, a3, a4, 2
  200. s32i a0, a2, 0
  201. __endla a2, a3, 4
  202. #if XCHAL_DCACHE_IS_WRITEBACK
  203. /* After unpacking, flush the writeback cache to memory so the
  204. * instructions/data are available.
  205. */
  206. ___flush_dcache_all a2 a3
  207. #endif
  208. memw
  209. isync
  210. ___invalidate_icache_all a2 a3
  211. isync
  212. #ifdef CONFIG_XIP_KERNEL
  213. /* Setup bootstrap CPU stack in XIP kernel */
  214. movi a1, start_info
  215. l32i a1, a1, 0
  216. #endif
  217. movi abi_arg0, 0
  218. xsr abi_arg0, excsave1
  219. /* init_arch kick-starts the linux kernel */
  220. abi_call init_arch
  221. abi_call start_kernel
  222. should_never_return:
  223. j should_never_return
  224. #ifdef CONFIG_SMP
  225. .Lboot_secondary:
  226. movi a2, cpu_start_ccount
  227. 1:
  228. memw
  229. l32i a3, a2, 0
  230. beqi a3, 0, 1b
  231. movi a3, 0
  232. s32i a3, a2, 0
  233. 1:
  234. memw
  235. l32i a3, a2, 0
  236. beqi a3, 0, 1b
  237. wsr a3, ccount
  238. movi a3, 0
  239. s32i a3, a2, 0
  240. memw
  241. movi abi_arg0, 0
  242. wsr abi_arg0, excsave1
  243. abi_call secondary_start_kernel
  244. j should_never_return
  245. #endif /* CONFIG_SMP */
  246. ENDPROC(_startup)
  247. #ifdef CONFIG_HOTPLUG_CPU
  248. ENTRY(cpu_restart)
  249. #if XCHAL_DCACHE_IS_WRITEBACK
  250. ___flush_invalidate_dcache_all a2 a3
  251. #else
  252. ___invalidate_dcache_all a2 a3
  253. #endif
  254. memw
  255. movi a2, CCON # MX External Register to Configure Cache
  256. movi a3, 0
  257. wer a3, a2
  258. extw
  259. rsr a0, prid
  260. neg a2, a0
  261. movi a3, cpu_start_id
  262. memw
  263. s32i a2, a3, 0
  264. #if XCHAL_DCACHE_IS_WRITEBACK
  265. dhwbi a3, 0
  266. #endif
  267. 1:
  268. memw
  269. l32i a2, a3, 0
  270. dhi a3, 0
  271. bne a2, a0, 1b
  272. /*
  273. * Initialize WB, WS, and clear PS.EXCM (to allow loop instructions).
  274. * Set Interrupt Level just below XCHAL_DEBUGLEVEL to allow
  275. * xt-gdb to single step via DEBUG exceptions received directly
  276. * by ocd.
  277. */
  278. movi a1, 1
  279. movi a0, 0
  280. wsr a1, windowstart
  281. wsr a0, windowbase
  282. rsync
  283. movi a1, LOCKLEVEL
  284. wsr a1, ps
  285. rsync
  286. j _startup
  287. ENDPROC(cpu_restart)
  288. #endif /* CONFIG_HOTPLUG_CPU */
  289. /*
  290. * DATA section
  291. */
  292. __REFDATA
  293. .align 4
  294. ENTRY(start_info)
  295. .long init_thread_union + KERNEL_STACK_SIZE
  296. /*
  297. * BSS section
  298. */
  299. __PAGE_ALIGNED_BSS
  300. #ifdef CONFIG_MMU
  301. ENTRY(swapper_pg_dir)
  302. .fill PAGE_SIZE, 1, 0
  303. END(swapper_pg_dir)
  304. #endif
  305. ENTRY(empty_zero_page)
  306. .fill PAGE_SIZE, 1, 0
  307. END(empty_zero_page)