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  1. /*
  2. * Low-level exception handling
  3. *
  4. * This file is subject to the terms and conditions of the GNU General Public
  5. * License. See the file "COPYING" in the main directory of this archive
  6. * for more details.
  7. *
  8. * Copyright (C) 2004 - 2008 by Tensilica Inc.
  9. * Copyright (C) 2015 Cadence Design Systems Inc.
  10. *
  11. * Chris Zankel <[email protected]>
  12. *
  13. */
  14. #include <linux/linkage.h>
  15. #include <linux/pgtable.h>
  16. #include <asm/asm-offsets.h>
  17. #include <asm/asmmacro.h>
  18. #include <asm/processor.h>
  19. #include <asm/coprocessor.h>
  20. #include <asm/thread_info.h>
  21. #include <asm/asm-uaccess.h>
  22. #include <asm/unistd.h>
  23. #include <asm/ptrace.h>
  24. #include <asm/current.h>
  25. #include <asm/page.h>
  26. #include <asm/signal.h>
  27. #include <asm/tlbflush.h>
  28. #include <variant/tie-asm.h>
  29. /*
  30. * Macro to find first bit set in WINDOWBASE from the left + 1
  31. *
  32. * 100....0 -> 1
  33. * 010....0 -> 2
  34. * 000....1 -> WSBITS
  35. */
  36. .macro ffs_ws bit mask
  37. #if XCHAL_HAVE_NSA
  38. nsau \bit, \mask # 32-WSBITS ... 31 (32 iff 0)
  39. addi \bit, \bit, WSBITS - 32 + 1 # uppest bit set -> return 1
  40. #else
  41. movi \bit, WSBITS
  42. #if WSBITS > 16
  43. _bltui \mask, 0x10000, 99f
  44. addi \bit, \bit, -16
  45. extui \mask, \mask, 16, 16
  46. #endif
  47. #if WSBITS > 8
  48. 99: _bltui \mask, 0x100, 99f
  49. addi \bit, \bit, -8
  50. srli \mask, \mask, 8
  51. #endif
  52. 99: _bltui \mask, 0x10, 99f
  53. addi \bit, \bit, -4
  54. srli \mask, \mask, 4
  55. 99: _bltui \mask, 0x4, 99f
  56. addi \bit, \bit, -2
  57. srli \mask, \mask, 2
  58. 99: _bltui \mask, 0x2, 99f
  59. addi \bit, \bit, -1
  60. 99:
  61. #endif
  62. .endm
  63. .macro irq_save flags tmp
  64. #if XTENSA_FAKE_NMI
  65. #if defined(CONFIG_DEBUG_KERNEL) && (LOCKLEVEL | TOPLEVEL) >= XCHAL_DEBUGLEVEL
  66. rsr \flags, ps
  67. extui \tmp, \flags, PS_INTLEVEL_SHIFT, PS_INTLEVEL_WIDTH
  68. bgei \tmp, LOCKLEVEL, 99f
  69. rsil \tmp, LOCKLEVEL
  70. 99:
  71. #else
  72. movi \tmp, LOCKLEVEL
  73. rsr \flags, ps
  74. or \flags, \flags, \tmp
  75. xsr \flags, ps
  76. rsync
  77. #endif
  78. #else
  79. rsil \flags, LOCKLEVEL
  80. #endif
  81. .endm
  82. /* ----------------- DEFAULT FIRST LEVEL EXCEPTION HANDLERS ----------------- */
  83. /*
  84. * First-level exception handler for user exceptions.
  85. * Save some special registers, extra states and all registers in the AR
  86. * register file that were in use in the user task, and jump to the common
  87. * exception code.
  88. * We save SAR (used to calculate WMASK), and WB and WS (we don't have to
  89. * save them for kernel exceptions).
  90. *
  91. * Entry condition for user_exception:
  92. *
  93. * a0: trashed, original value saved on stack (PT_AREG0)
  94. * a1: a1
  95. * a2: new stack pointer, original value in depc
  96. * a3: a3
  97. * depc: a2, original value saved on stack (PT_DEPC)
  98. * excsave1: dispatch table
  99. *
  100. * PT_DEPC >= VALID_DOUBLE_EXCEPTION_ADDRESS: double exception, DEPC
  101. * < VALID_DOUBLE_EXCEPTION_ADDRESS: regular exception
  102. *
  103. * Entry condition for _user_exception:
  104. *
  105. * a0-a3 and depc have been saved to PT_AREG0...PT_AREG3 and PT_DEPC
  106. * excsave has been restored, and
  107. * stack pointer (a1) has been set.
  108. *
  109. * Note: _user_exception might be at an odd address. Don't use call0..call12
  110. */
  111. .literal_position
  112. ENTRY(user_exception)
  113. /* Save a1, a2, a3, and set SP. */
  114. rsr a0, depc
  115. s32i a1, a2, PT_AREG1
  116. s32i a0, a2, PT_AREG2
  117. s32i a3, a2, PT_AREG3
  118. mov a1, a2
  119. .globl _user_exception
  120. _user_exception:
  121. /* Save SAR and turn off single stepping */
  122. movi a2, 0
  123. wsr a2, depc # terminate user stack trace with 0
  124. rsr a3, sar
  125. xsr a2, icountlevel
  126. s32i a3, a1, PT_SAR
  127. s32i a2, a1, PT_ICOUNTLEVEL
  128. #if XCHAL_HAVE_THREADPTR
  129. rur a2, threadptr
  130. s32i a2, a1, PT_THREADPTR
  131. #endif
  132. /* Rotate ws so that the current windowbase is at bit0. */
  133. /* Assume ws = xxwww1yyyy. Rotate ws right, so that a2 = yyyyxxwww1 */
  134. #if defined(USER_SUPPORT_WINDOWED)
  135. rsr a2, windowbase
  136. rsr a3, windowstart
  137. ssr a2
  138. s32i a2, a1, PT_WINDOWBASE
  139. s32i a3, a1, PT_WINDOWSTART
  140. slli a2, a3, 32-WSBITS
  141. src a2, a3, a2
  142. srli a2, a2, 32-WSBITS
  143. s32i a2, a1, PT_WMASK # needed for restoring registers
  144. #else
  145. movi a2, 0
  146. movi a3, 1
  147. s32i a2, a1, PT_WINDOWBASE
  148. s32i a3, a1, PT_WINDOWSTART
  149. s32i a3, a1, PT_WMASK
  150. #endif
  151. /* Save only live registers. */
  152. UABI_W _bbsi.l a2, 1, .Lsave_window_registers
  153. s32i a4, a1, PT_AREG4
  154. s32i a5, a1, PT_AREG5
  155. s32i a6, a1, PT_AREG6
  156. s32i a7, a1, PT_AREG7
  157. UABI_W _bbsi.l a2, 2, .Lsave_window_registers
  158. s32i a8, a1, PT_AREG8
  159. s32i a9, a1, PT_AREG9
  160. s32i a10, a1, PT_AREG10
  161. s32i a11, a1, PT_AREG11
  162. UABI_W _bbsi.l a2, 3, .Lsave_window_registers
  163. s32i a12, a1, PT_AREG12
  164. s32i a13, a1, PT_AREG13
  165. s32i a14, a1, PT_AREG14
  166. s32i a15, a1, PT_AREG15
  167. #if defined(USER_SUPPORT_WINDOWED)
  168. /* If only one valid frame skip saving regs. */
  169. beqi a2, 1, common_exception
  170. /* Save the remaining registers.
  171. * We have to save all registers up to the first '1' from
  172. * the right, except the current frame (bit 0).
  173. * Assume a2 is: 001001000110001
  174. * All register frames starting from the top field to the marked '1'
  175. * must be saved.
  176. */
  177. .Lsave_window_registers:
  178. addi a3, a2, -1 # eliminate '1' in bit 0: yyyyxxww0
  179. neg a3, a3 # yyyyxxww0 -> YYYYXXWW1+1
  180. and a3, a3, a2 # max. only one bit is set
  181. /* Find number of frames to save */
  182. ffs_ws a0, a3 # number of frames to the '1' from left
  183. /* Store information into WMASK:
  184. * bits 0..3: xxx1 masked lower 4 bits of the rotated windowstart,
  185. * bits 4...: number of valid 4-register frames
  186. */
  187. slli a3, a0, 4 # number of frames to save in bits 8..4
  188. extui a2, a2, 0, 4 # mask for the first 16 registers
  189. or a2, a3, a2
  190. s32i a2, a1, PT_WMASK # needed when we restore the reg-file
  191. /* Save 4 registers at a time */
  192. 1: rotw -1
  193. s32i a0, a5, PT_AREG_END - 16
  194. s32i a1, a5, PT_AREG_END - 12
  195. s32i a2, a5, PT_AREG_END - 8
  196. s32i a3, a5, PT_AREG_END - 4
  197. addi a0, a4, -1
  198. addi a1, a5, -16
  199. _bnez a0, 1b
  200. /* WINDOWBASE still in SAR! */
  201. rsr a2, sar # original WINDOWBASE
  202. movi a3, 1
  203. ssl a2
  204. sll a3, a3
  205. wsr a3, windowstart # set corresponding WINDOWSTART bit
  206. wsr a2, windowbase # and WINDOWSTART
  207. rsync
  208. /* We are back to the original stack pointer (a1) */
  209. #endif
  210. /* Now, jump to the common exception handler. */
  211. j common_exception
  212. ENDPROC(user_exception)
  213. /*
  214. * First-level exit handler for kernel exceptions
  215. * Save special registers and the live window frame.
  216. * Note: Even though we changes the stack pointer, we don't have to do a
  217. * MOVSP here, as we do that when we return from the exception.
  218. * (See comment in the kernel exception exit code)
  219. *
  220. * Entry condition for kernel_exception:
  221. *
  222. * a0: trashed, original value saved on stack (PT_AREG0)
  223. * a1: a1
  224. * a2: new stack pointer, original in DEPC
  225. * a3: a3
  226. * depc: a2, original value saved on stack (PT_DEPC)
  227. * excsave_1: dispatch table
  228. *
  229. * PT_DEPC >= VALID_DOUBLE_EXCEPTION_ADDRESS: double exception, DEPC
  230. * < VALID_DOUBLE_EXCEPTION_ADDRESS: regular exception
  231. *
  232. * Entry condition for _kernel_exception:
  233. *
  234. * a0-a3 and depc have been saved to PT_AREG0...PT_AREG3 and PT_DEPC
  235. * excsave has been restored, and
  236. * stack pointer (a1) has been set.
  237. *
  238. * Note: _kernel_exception might be at an odd address. Don't use call0..call12
  239. */
  240. ENTRY(kernel_exception)
  241. /* Save a1, a2, a3, and set SP. */
  242. rsr a0, depc # get a2
  243. s32i a1, a2, PT_AREG1
  244. s32i a0, a2, PT_AREG2
  245. s32i a3, a2, PT_AREG3
  246. mov a1, a2
  247. .globl _kernel_exception
  248. _kernel_exception:
  249. /* Save SAR and turn off single stepping */
  250. movi a2, 0
  251. rsr a3, sar
  252. xsr a2, icountlevel
  253. s32i a3, a1, PT_SAR
  254. s32i a2, a1, PT_ICOUNTLEVEL
  255. #if defined(__XTENSA_WINDOWED_ABI__)
  256. /* Rotate ws so that the current windowbase is at bit0. */
  257. /* Assume ws = xxwww1yyyy. Rotate ws right, so that a2 = yyyyxxwww1 */
  258. rsr a2, windowbase # don't need to save these, we only
  259. rsr a3, windowstart # need shifted windowstart: windowmask
  260. ssr a2
  261. slli a2, a3, 32-WSBITS
  262. src a2, a3, a2
  263. srli a2, a2, 32-WSBITS
  264. s32i a2, a1, PT_WMASK # needed for kernel_exception_exit
  265. #endif
  266. /* Save only the live window-frame */
  267. KABI_W _bbsi.l a2, 1, 1f
  268. s32i a4, a1, PT_AREG4
  269. s32i a5, a1, PT_AREG5
  270. s32i a6, a1, PT_AREG6
  271. s32i a7, a1, PT_AREG7
  272. KABI_W _bbsi.l a2, 2, 1f
  273. s32i a8, a1, PT_AREG8
  274. s32i a9, a1, PT_AREG9
  275. s32i a10, a1, PT_AREG10
  276. s32i a11, a1, PT_AREG11
  277. KABI_W _bbsi.l a2, 3, 1f
  278. s32i a12, a1, PT_AREG12
  279. s32i a13, a1, PT_AREG13
  280. s32i a14, a1, PT_AREG14
  281. s32i a15, a1, PT_AREG15
  282. #ifdef __XTENSA_WINDOWED_ABI__
  283. _bnei a2, 1, 1f
  284. /* Copy spill slots of a0 and a1 to imitate movsp
  285. * in order to keep exception stack continuous
  286. */
  287. l32i a3, a1, PT_KERNEL_SIZE
  288. l32i a0, a1, PT_KERNEL_SIZE + 4
  289. s32e a3, a1, -16
  290. s32e a0, a1, -12
  291. #endif
  292. 1:
  293. l32i a0, a1, PT_AREG0 # restore saved a0
  294. wsr a0, depc
  295. /*
  296. * This is the common exception handler.
  297. * We get here from the user exception handler or simply by falling through
  298. * from the kernel exception handler.
  299. * Save the remaining special registers, switch to kernel mode, and jump
  300. * to the second-level exception handler.
  301. *
  302. */
  303. common_exception:
  304. /* Save some registers, disable loops and clear the syscall flag. */
  305. rsr a2, debugcause
  306. rsr a3, epc1
  307. s32i a2, a1, PT_DEBUGCAUSE
  308. s32i a3, a1, PT_PC
  309. movi a2, NO_SYSCALL
  310. rsr a3, excvaddr
  311. s32i a2, a1, PT_SYSCALL
  312. movi a2, 0
  313. s32i a3, a1, PT_EXCVADDR
  314. #if XCHAL_HAVE_LOOPS
  315. xsr a2, lcount
  316. s32i a2, a1, PT_LCOUNT
  317. #endif
  318. #if XCHAL_HAVE_EXCLUSIVE
  319. /* Clear exclusive access monitor set by interrupted code */
  320. clrex
  321. #endif
  322. /* It is now save to restore the EXC_TABLE_FIXUP variable. */
  323. rsr a2, exccause
  324. movi a3, 0
  325. rsr a0, excsave1
  326. s32i a2, a1, PT_EXCCAUSE
  327. s32i a3, a0, EXC_TABLE_FIXUP
  328. /* All unrecoverable states are saved on stack, now, and a1 is valid.
  329. * Now we can allow exceptions again. In case we've got an interrupt
  330. * PS.INTLEVEL is set to LOCKLEVEL disabling furhter interrupts,
  331. * otherwise it's left unchanged.
  332. *
  333. * Set PS(EXCM = 0, UM = 0, RING = 0, OWB = 0, WOE = 1, INTLEVEL = X)
  334. */
  335. rsr a3, ps
  336. s32i a3, a1, PT_PS # save ps
  337. #if XTENSA_FAKE_NMI
  338. /* Correct PS needs to be saved in the PT_PS:
  339. * - in case of exception or level-1 interrupt it's in the PS,
  340. * and is already saved.
  341. * - in case of medium level interrupt it's in the excsave2.
  342. */
  343. movi a0, EXCCAUSE_MAPPED_NMI
  344. extui a3, a3, PS_INTLEVEL_SHIFT, PS_INTLEVEL_WIDTH
  345. beq a2, a0, .Lmedium_level_irq
  346. bnei a2, EXCCAUSE_LEVEL1_INTERRUPT, .Lexception
  347. beqz a3, .Llevel1_irq # level-1 IRQ sets ps.intlevel to 0
  348. .Lmedium_level_irq:
  349. rsr a0, excsave2
  350. s32i a0, a1, PT_PS # save medium-level interrupt ps
  351. bgei a3, LOCKLEVEL, .Lexception
  352. .Llevel1_irq:
  353. movi a3, LOCKLEVEL
  354. .Lexception:
  355. KABI_W movi a0, PS_WOE_MASK
  356. KABI_W or a3, a3, a0
  357. #else
  358. addi a2, a2, -EXCCAUSE_LEVEL1_INTERRUPT
  359. movi a0, LOCKLEVEL
  360. extui a3, a3, PS_INTLEVEL_SHIFT, PS_INTLEVEL_WIDTH
  361. # a3 = PS.INTLEVEL
  362. moveqz a3, a0, a2 # a3 = LOCKLEVEL iff interrupt
  363. KABI_W movi a2, PS_WOE_MASK
  364. KABI_W or a3, a3, a2
  365. #endif
  366. /* restore return address (or 0 if return to userspace) */
  367. rsr a0, depc
  368. wsr a3, ps
  369. rsync # PS.WOE => rsync => overflow
  370. /* Save lbeg, lend */
  371. #if XCHAL_HAVE_LOOPS
  372. rsr a4, lbeg
  373. rsr a3, lend
  374. s32i a4, a1, PT_LBEG
  375. s32i a3, a1, PT_LEND
  376. #endif
  377. /* Save SCOMPARE1 */
  378. #if XCHAL_HAVE_S32C1I
  379. rsr a3, scompare1
  380. s32i a3, a1, PT_SCOMPARE1
  381. #endif
  382. /* Save optional registers. */
  383. save_xtregs_opt a1 a3 a4 a5 a6 a7 PT_XTREGS_OPT
  384. #ifdef CONFIG_TRACE_IRQFLAGS
  385. rsr abi_tmp0, ps
  386. extui abi_tmp0, abi_tmp0, PS_INTLEVEL_SHIFT, PS_INTLEVEL_WIDTH
  387. beqz abi_tmp0, 1f
  388. abi_call trace_hardirqs_off
  389. 1:
  390. #endif
  391. #ifdef CONFIG_CONTEXT_TRACKING_USER
  392. l32i abi_tmp0, a1, PT_PS
  393. bbci.l abi_tmp0, PS_UM_BIT, 1f
  394. abi_call user_exit_callable
  395. 1:
  396. #endif
  397. /* Go to second-level dispatcher. Set up parameters to pass to the
  398. * exception handler and call the exception handler.
  399. */
  400. l32i abi_arg1, a1, PT_EXCCAUSE # pass EXCCAUSE
  401. rsr abi_tmp0, excsave1
  402. addx4 abi_tmp0, abi_arg1, abi_tmp0
  403. l32i abi_tmp0, abi_tmp0, EXC_TABLE_DEFAULT # load handler
  404. mov abi_arg0, a1 # pass stack frame
  405. /* Call the second-level handler */
  406. abi_callx abi_tmp0
  407. /* Jump here for exception exit */
  408. .global common_exception_return
  409. common_exception_return:
  410. #if XTENSA_FAKE_NMI
  411. l32i abi_tmp0, a1, PT_EXCCAUSE
  412. movi abi_tmp1, EXCCAUSE_MAPPED_NMI
  413. l32i abi_saved1, a1, PT_PS
  414. beq abi_tmp0, abi_tmp1, .Lrestore_state
  415. #endif
  416. .Ltif_loop:
  417. irq_save abi_tmp0, abi_tmp1
  418. #ifdef CONFIG_TRACE_IRQFLAGS
  419. abi_call trace_hardirqs_off
  420. #endif
  421. /* Jump if we are returning from kernel exceptions. */
  422. l32i abi_saved1, a1, PT_PS
  423. GET_THREAD_INFO(abi_tmp0, a1)
  424. l32i abi_saved0, abi_tmp0, TI_FLAGS
  425. _bbci.l abi_saved1, PS_UM_BIT, .Lexit_tif_loop_kernel
  426. /* Specific to a user exception exit:
  427. * We need to check some flags for signal handling and rescheduling,
  428. * and have to restore WB and WS, extra states, and all registers
  429. * in the register file that were in use in the user task.
  430. * Note that we don't disable interrupts here.
  431. */
  432. _bbsi.l abi_saved0, TIF_NEED_RESCHED, .Lresched
  433. movi abi_tmp0, _TIF_SIGPENDING | _TIF_NOTIFY_RESUME | _TIF_NOTIFY_SIGNAL
  434. bnone abi_saved0, abi_tmp0, .Lexit_tif_loop_user
  435. l32i abi_tmp0, a1, PT_DEPC
  436. bgeui abi_tmp0, VALID_DOUBLE_EXCEPTION_ADDRESS, .Lrestore_state
  437. /* Call do_signal() */
  438. #ifdef CONFIG_TRACE_IRQFLAGS
  439. abi_call trace_hardirqs_on
  440. #endif
  441. rsil abi_tmp0, 0
  442. mov abi_arg0, a1
  443. abi_call do_notify_resume # int do_notify_resume(struct pt_regs*)
  444. j .Ltif_loop
  445. .Lresched:
  446. #ifdef CONFIG_TRACE_IRQFLAGS
  447. abi_call trace_hardirqs_on
  448. #endif
  449. rsil abi_tmp0, 0
  450. abi_call schedule # void schedule (void)
  451. j .Ltif_loop
  452. .Lexit_tif_loop_kernel:
  453. #ifdef CONFIG_PREEMPTION
  454. _bbci.l abi_saved0, TIF_NEED_RESCHED, .Lrestore_state
  455. /* Check current_thread_info->preempt_count */
  456. l32i abi_tmp1, abi_tmp0, TI_PRE_COUNT
  457. bnez abi_tmp1, .Lrestore_state
  458. abi_call preempt_schedule_irq
  459. #endif
  460. j .Lrestore_state
  461. .Lexit_tif_loop_user:
  462. #ifdef CONFIG_CONTEXT_TRACKING_USER
  463. abi_call user_enter_callable
  464. #endif
  465. #ifdef CONFIG_HAVE_HW_BREAKPOINT
  466. _bbci.l abi_saved0, TIF_DB_DISABLED, 1f
  467. abi_call restore_dbreak
  468. 1:
  469. #endif
  470. #ifdef CONFIG_DEBUG_TLB_SANITY
  471. l32i abi_tmp0, a1, PT_DEPC
  472. bgeui abi_tmp0, VALID_DOUBLE_EXCEPTION_ADDRESS, .Lrestore_state
  473. abi_call check_tlb_sanity
  474. #endif
  475. .Lrestore_state:
  476. #ifdef CONFIG_TRACE_IRQFLAGS
  477. extui abi_tmp0, abi_saved1, PS_INTLEVEL_SHIFT, PS_INTLEVEL_WIDTH
  478. bgei abi_tmp0, LOCKLEVEL, 1f
  479. abi_call trace_hardirqs_on
  480. 1:
  481. #endif
  482. /*
  483. * Restore optional registers.
  484. * abi_arg* are used as temporary registers here.
  485. */
  486. load_xtregs_opt a1 abi_tmp0 abi_arg0 abi_arg1 abi_arg2 abi_arg3 PT_XTREGS_OPT
  487. /* Restore SCOMPARE1 */
  488. #if XCHAL_HAVE_S32C1I
  489. l32i abi_tmp0, a1, PT_SCOMPARE1
  490. wsr abi_tmp0, scompare1
  491. #endif
  492. wsr abi_saved1, ps /* disable interrupts */
  493. _bbci.l abi_saved1, PS_UM_BIT, kernel_exception_exit
  494. user_exception_exit:
  495. /* Restore the state of the task and return from the exception. */
  496. #if defined(USER_SUPPORT_WINDOWED)
  497. /* Switch to the user thread WINDOWBASE. Save SP temporarily in DEPC */
  498. l32i a2, a1, PT_WINDOWBASE
  499. l32i a3, a1, PT_WINDOWSTART
  500. wsr a1, depc # use DEPC as temp storage
  501. wsr a3, windowstart # restore WINDOWSTART
  502. ssr a2 # preserve user's WB in the SAR
  503. wsr a2, windowbase # switch to user's saved WB
  504. rsync
  505. rsr a1, depc # restore stack pointer
  506. l32i a2, a1, PT_WMASK # register frames saved (in bits 4...9)
  507. rotw -1 # we restore a4..a7
  508. _bltui a6, 16, .Lclear_regs # only have to restore current window?
  509. /* The working registers are a0 and a3. We are restoring to
  510. * a4..a7. Be careful not to destroy what we have just restored.
  511. * Note: wmask has the format YYYYM:
  512. * Y: number of registers saved in groups of 4
  513. * M: 4 bit mask of first 16 registers
  514. */
  515. mov a2, a6
  516. mov a3, a5
  517. 1: rotw -1 # a0..a3 become a4..a7
  518. addi a3, a7, -4*4 # next iteration
  519. addi a2, a6, -16 # decrementing Y in WMASK
  520. l32i a4, a3, PT_AREG_END + 0
  521. l32i a5, a3, PT_AREG_END + 4
  522. l32i a6, a3, PT_AREG_END + 8
  523. l32i a7, a3, PT_AREG_END + 12
  524. _bgeui a2, 16, 1b
  525. /* Clear unrestored registers (don't leak anything to user-land */
  526. .Lclear_regs:
  527. rsr a0, windowbase
  528. rsr a3, sar
  529. sub a3, a0, a3
  530. beqz a3, 2f
  531. extui a3, a3, 0, WBBITS
  532. 1: rotw -1
  533. addi a3, a7, -1
  534. movi a4, 0
  535. movi a5, 0
  536. movi a6, 0
  537. movi a7, 0
  538. bgei a3, 1, 1b
  539. /* We are back were we were when we started.
  540. * Note: a2 still contains WMASK (if we've returned to the original
  541. * frame where we had loaded a2), or at least the lower 4 bits
  542. * (if we have restored WSBITS-1 frames).
  543. */
  544. 2:
  545. #else
  546. movi a2, 1
  547. #endif
  548. #if XCHAL_HAVE_THREADPTR
  549. l32i a3, a1, PT_THREADPTR
  550. wur a3, threadptr
  551. #endif
  552. j common_exception_exit
  553. /* This is the kernel exception exit.
  554. * We avoided to do a MOVSP when we entered the exception, but we
  555. * have to do it here.
  556. */
  557. kernel_exception_exit:
  558. #if defined(__XTENSA_WINDOWED_ABI__)
  559. /* Check if we have to do a movsp.
  560. *
  561. * We only have to do a movsp if the previous window-frame has
  562. * been spilled to the *temporary* exception stack instead of the
  563. * task's stack. This is the case if the corresponding bit in
  564. * WINDOWSTART for the previous window-frame was set before
  565. * (not spilled) but is zero now (spilled).
  566. * If this bit is zero, all other bits except the one for the
  567. * current window frame are also zero. So, we can use a simple test:
  568. * 'and' WINDOWSTART and WINDOWSTART-1:
  569. *
  570. * (XXXXXX1[0]* - 1) AND XXXXXX1[0]* = XXXXXX0[0]*
  571. *
  572. * The result is zero only if one bit was set.
  573. *
  574. * (Note: We might have gone through several task switches before
  575. * we come back to the current task, so WINDOWBASE might be
  576. * different from the time the exception occurred.)
  577. */
  578. /* Test WINDOWSTART before and after the exception.
  579. * We actually have WMASK, so we only have to test if it is 1 or not.
  580. */
  581. l32i a2, a1, PT_WMASK
  582. _beqi a2, 1, common_exception_exit # Spilled before exception,jump
  583. /* Test WINDOWSTART now. If spilled, do the movsp */
  584. rsr a3, windowstart
  585. addi a0, a3, -1
  586. and a3, a3, a0
  587. _bnez a3, common_exception_exit
  588. /* Do a movsp (we returned from a call4, so we have at least a0..a7) */
  589. addi a0, a1, -16
  590. l32i a3, a0, 0
  591. l32i a4, a0, 4
  592. s32i a3, a1, PT_KERNEL_SIZE + 0
  593. s32i a4, a1, PT_KERNEL_SIZE + 4
  594. l32i a3, a0, 8
  595. l32i a4, a0, 12
  596. s32i a3, a1, PT_KERNEL_SIZE + 8
  597. s32i a4, a1, PT_KERNEL_SIZE + 12
  598. /* Common exception exit.
  599. * We restore the special register and the current window frame, and
  600. * return from the exception.
  601. *
  602. * Note: We expect a2 to hold PT_WMASK
  603. */
  604. #else
  605. movi a2, 1
  606. #endif
  607. common_exception_exit:
  608. /* Restore address registers. */
  609. _bbsi.l a2, 1, 1f
  610. l32i a4, a1, PT_AREG4
  611. l32i a5, a1, PT_AREG5
  612. l32i a6, a1, PT_AREG6
  613. l32i a7, a1, PT_AREG7
  614. _bbsi.l a2, 2, 1f
  615. l32i a8, a1, PT_AREG8
  616. l32i a9, a1, PT_AREG9
  617. l32i a10, a1, PT_AREG10
  618. l32i a11, a1, PT_AREG11
  619. _bbsi.l a2, 3, 1f
  620. l32i a12, a1, PT_AREG12
  621. l32i a13, a1, PT_AREG13
  622. l32i a14, a1, PT_AREG14
  623. l32i a15, a1, PT_AREG15
  624. /* Restore PC, SAR */
  625. 1: l32i a2, a1, PT_PC
  626. l32i a3, a1, PT_SAR
  627. wsr a2, epc1
  628. wsr a3, sar
  629. /* Restore LBEG, LEND, LCOUNT */
  630. #if XCHAL_HAVE_LOOPS
  631. l32i a2, a1, PT_LBEG
  632. l32i a3, a1, PT_LEND
  633. wsr a2, lbeg
  634. l32i a2, a1, PT_LCOUNT
  635. wsr a3, lend
  636. wsr a2, lcount
  637. #endif
  638. /* We control single stepping through the ICOUNTLEVEL register. */
  639. l32i a2, a1, PT_ICOUNTLEVEL
  640. movi a3, -2
  641. wsr a2, icountlevel
  642. wsr a3, icount
  643. /* Check if it was double exception. */
  644. l32i a0, a1, PT_DEPC
  645. l32i a3, a1, PT_AREG3
  646. l32i a2, a1, PT_AREG2
  647. _bgeui a0, VALID_DOUBLE_EXCEPTION_ADDRESS, 1f
  648. /* Restore a0...a3 and return */
  649. l32i a0, a1, PT_AREG0
  650. l32i a1, a1, PT_AREG1
  651. rfe
  652. 1: wsr a0, depc
  653. l32i a0, a1, PT_AREG0
  654. l32i a1, a1, PT_AREG1
  655. rfde
  656. ENDPROC(kernel_exception)
  657. /*
  658. * Debug exception handler.
  659. *
  660. * Currently, we don't support KGDB, so only user application can be debugged.
  661. *
  662. * When we get here, a0 is trashed and saved to excsave[debuglevel]
  663. */
  664. .literal_position
  665. ENTRY(debug_exception)
  666. rsr a0, SREG_EPS + XCHAL_DEBUGLEVEL
  667. bbsi.l a0, PS_EXCM_BIT, .Ldebug_exception_in_exception # exception mode
  668. /* Set EPC1 and EXCCAUSE */
  669. wsr a2, depc # save a2 temporarily
  670. rsr a2, SREG_EPC + XCHAL_DEBUGLEVEL
  671. wsr a2, epc1
  672. movi a2, EXCCAUSE_MAPPED_DEBUG
  673. wsr a2, exccause
  674. /* Restore PS to the value before the debug exc but with PS.EXCM set.*/
  675. movi a2, 1 << PS_EXCM_BIT
  676. or a2, a0, a2
  677. wsr a2, ps
  678. /* Switch to kernel/user stack, restore jump vector, and save a0 */
  679. bbsi.l a2, PS_UM_BIT, .Ldebug_exception_user # jump if user mode
  680. addi a2, a1, -16 - PT_KERNEL_SIZE # assume kernel stack
  681. .Ldebug_exception_continue:
  682. l32i a0, a3, DT_DEBUG_SAVE
  683. s32i a1, a2, PT_AREG1
  684. s32i a0, a2, PT_AREG0
  685. movi a0, 0
  686. s32i a0, a2, PT_DEPC # mark it as a regular exception
  687. xsr a3, SREG_EXCSAVE + XCHAL_DEBUGLEVEL
  688. xsr a0, depc
  689. s32i a3, a2, PT_AREG3
  690. s32i a0, a2, PT_AREG2
  691. mov a1, a2
  692. /* Debug exception is handled as an exception, so interrupts will
  693. * likely be enabled in the common exception handler. Disable
  694. * preemption if we have HW breakpoints to preserve DEBUGCAUSE.DBNUM
  695. * meaning.
  696. */
  697. #if defined(CONFIG_PREEMPT_COUNT) && defined(CONFIG_HAVE_HW_BREAKPOINT)
  698. GET_THREAD_INFO(a2, a1)
  699. l32i a3, a2, TI_PRE_COUNT
  700. addi a3, a3, 1
  701. s32i a3, a2, TI_PRE_COUNT
  702. #endif
  703. rsr a2, ps
  704. bbsi.l a2, PS_UM_BIT, _user_exception
  705. j _kernel_exception
  706. .Ldebug_exception_user:
  707. rsr a2, excsave1
  708. l32i a2, a2, EXC_TABLE_KSTK # load kernel stack pointer
  709. j .Ldebug_exception_continue
  710. .Ldebug_exception_in_exception:
  711. #ifdef CONFIG_HAVE_HW_BREAKPOINT
  712. /* Debug exception while in exception mode. This may happen when
  713. * window overflow/underflow handler or fast exception handler hits
  714. * data breakpoint, in which case save and disable all data
  715. * breakpoints, single-step faulting instruction and restore data
  716. * breakpoints.
  717. */
  718. bbci.l a0, PS_UM_BIT, .Ldebug_exception_in_exception # jump if kernel mode
  719. rsr a0, debugcause
  720. bbsi.l a0, DEBUGCAUSE_DBREAK_BIT, .Ldebug_save_dbreak
  721. .set _index, 0
  722. .rept XCHAL_NUM_DBREAK
  723. l32i a0, a3, DT_DBREAKC_SAVE + _index * 4
  724. wsr a0, SREG_DBREAKC + _index
  725. .set _index, _index + 1
  726. .endr
  727. l32i a0, a3, DT_ICOUNT_LEVEL_SAVE
  728. wsr a0, icountlevel
  729. l32i a0, a3, DT_ICOUNT_SAVE
  730. xsr a0, icount
  731. l32i a0, a3, DT_DEBUG_SAVE
  732. xsr a3, SREG_EXCSAVE + XCHAL_DEBUGLEVEL
  733. rfi XCHAL_DEBUGLEVEL
  734. .Ldebug_save_dbreak:
  735. .set _index, 0
  736. .rept XCHAL_NUM_DBREAK
  737. movi a0, 0
  738. xsr a0, SREG_DBREAKC + _index
  739. s32i a0, a3, DT_DBREAKC_SAVE + _index * 4
  740. .set _index, _index + 1
  741. .endr
  742. movi a0, XCHAL_EXCM_LEVEL + 1
  743. xsr a0, icountlevel
  744. s32i a0, a3, DT_ICOUNT_LEVEL_SAVE
  745. movi a0, 0xfffffffe
  746. xsr a0, icount
  747. s32i a0, a3, DT_ICOUNT_SAVE
  748. l32i a0, a3, DT_DEBUG_SAVE
  749. xsr a3, SREG_EXCSAVE + XCHAL_DEBUGLEVEL
  750. rfi XCHAL_DEBUGLEVEL
  751. #else
  752. /* Debug exception while in exception mode. Should not happen. */
  753. j .Ldebug_exception_in_exception // FIXME!!
  754. #endif
  755. ENDPROC(debug_exception)
  756. /*
  757. * We get here in case of an unrecoverable exception.
  758. * The only thing we can do is to be nice and print a panic message.
  759. * We only produce a single stack frame for panic, so ???
  760. *
  761. *
  762. * Entry conditions:
  763. *
  764. * - a0 contains the caller address; original value saved in excsave1.
  765. * - the original a0 contains a valid return address (backtrace) or 0.
  766. * - a2 contains a valid stackpointer
  767. *
  768. * Notes:
  769. *
  770. * - If the stack pointer could be invalid, the caller has to setup a
  771. * dummy stack pointer (e.g. the stack of the init_task)
  772. *
  773. * - If the return address could be invalid, the caller has to set it
  774. * to 0, so the backtrace would stop.
  775. *
  776. */
  777. .align 4
  778. unrecoverable_text:
  779. .ascii "Unrecoverable error in exception handler\0"
  780. .literal_position
  781. ENTRY(unrecoverable_exception)
  782. #if XCHAL_HAVE_WINDOWED
  783. movi a0, 1
  784. movi a1, 0
  785. wsr a0, windowstart
  786. wsr a1, windowbase
  787. rsync
  788. #endif
  789. movi a1, KERNEL_PS_WOE_MASK | LOCKLEVEL
  790. wsr a1, ps
  791. rsync
  792. movi a1, init_task
  793. movi a0, 0
  794. addi a1, a1, PT_REGS_OFFSET
  795. movi abi_arg0, unrecoverable_text
  796. abi_call panic
  797. 1: j 1b
  798. ENDPROC(unrecoverable_exception)
  799. /* -------------------------- FAST EXCEPTION HANDLERS ----------------------- */
  800. __XTENSA_HANDLER
  801. .literal_position
  802. #ifdef SUPPORT_WINDOWED
  803. /*
  804. * Fast-handler for alloca exceptions
  805. *
  806. * The ALLOCA handler is entered when user code executes the MOVSP
  807. * instruction and the caller's frame is not in the register file.
  808. *
  809. * This algorithm was taken from the Ross Morley's RTOS Porting Layer:
  810. *
  811. * /home/ross/rtos/porting/XtensaRTOS-PortingLayer-20090507/xtensa_vectors.S
  812. *
  813. * It leverages the existing window spill/fill routines and their support for
  814. * double exceptions. The 'movsp' instruction will only cause an exception if
  815. * the next window needs to be loaded. In fact this ALLOCA exception may be
  816. * replaced at some point by changing the hardware to do a underflow exception
  817. * of the proper size instead.
  818. *
  819. * This algorithm simply backs out the register changes started by the user
  820. * exception handler, makes it appear that we have started a window underflow
  821. * by rotating the window back and then setting the old window base (OWB) in
  822. * the 'ps' register with the rolled back window base. The 'movsp' instruction
  823. * will be re-executed and this time since the next window frames is in the
  824. * active AR registers it won't cause an exception.
  825. *
  826. * If the WindowUnderflow code gets a TLB miss the page will get mapped
  827. * the partial WindowUnderflow will be handled in the double exception
  828. * handler.
  829. *
  830. * Entry condition:
  831. *
  832. * a0: trashed, original value saved on stack (PT_AREG0)
  833. * a1: a1
  834. * a2: new stack pointer, original in DEPC
  835. * a3: a3
  836. * depc: a2, original value saved on stack (PT_DEPC)
  837. * excsave_1: dispatch table
  838. *
  839. * PT_DEPC >= VALID_DOUBLE_EXCEPTION_ADDRESS: double exception, DEPC
  840. * < VALID_DOUBLE_EXCEPTION_ADDRESS: regular exception
  841. */
  842. ENTRY(fast_alloca)
  843. rsr a0, windowbase
  844. rotw -1
  845. rsr a2, ps
  846. extui a3, a2, PS_OWB_SHIFT, PS_OWB_WIDTH
  847. xor a3, a3, a4
  848. l32i a4, a6, PT_AREG0
  849. l32i a1, a6, PT_DEPC
  850. rsr a6, depc
  851. wsr a1, depc
  852. slli a3, a3, PS_OWB_SHIFT
  853. xor a2, a2, a3
  854. wsr a2, ps
  855. rsync
  856. _bbci.l a4, 31, 4f
  857. rotw -1
  858. _bbci.l a8, 30, 8f
  859. rotw -1
  860. j _WindowUnderflow12
  861. 8: j _WindowUnderflow8
  862. 4: j _WindowUnderflow4
  863. ENDPROC(fast_alloca)
  864. #endif
  865. #ifdef CONFIG_USER_ABI_CALL0_PROBE
  866. /*
  867. * fast illegal instruction handler.
  868. *
  869. * This is used to fix up user PS.WOE on the exception caused
  870. * by the first opcode related to register window. If PS.WOE is
  871. * already set it goes directly to the common user exception handler.
  872. *
  873. * Entry condition:
  874. *
  875. * a0: trashed, original value saved on stack (PT_AREG0)
  876. * a1: a1
  877. * a2: new stack pointer, original in DEPC
  878. * a3: a3
  879. * depc: a2, original value saved on stack (PT_DEPC)
  880. * excsave_1: dispatch table
  881. */
  882. ENTRY(fast_illegal_instruction_user)
  883. rsr a0, ps
  884. bbsi.l a0, PS_WOE_BIT, 1f
  885. s32i a3, a2, PT_AREG3
  886. movi a3, PS_WOE_MASK
  887. or a0, a0, a3
  888. wsr a0, ps
  889. #ifdef CONFIG_USER_ABI_CALL0_PROBE
  890. GET_THREAD_INFO(a3, a2)
  891. rsr a0, epc1
  892. s32i a0, a3, TI_PS_WOE_FIX_ADDR
  893. #endif
  894. l32i a3, a2, PT_AREG3
  895. l32i a0, a2, PT_AREG0
  896. rsr a2, depc
  897. rfe
  898. 1:
  899. call0 user_exception
  900. ENDPROC(fast_illegal_instruction_user)
  901. #endif
  902. /*
  903. * fast system calls.
  904. *
  905. * WARNING: The kernel doesn't save the entire user context before
  906. * handling a fast system call. These functions are small and short,
  907. * usually offering some functionality not available to user tasks.
  908. *
  909. * BE CAREFUL TO PRESERVE THE USER'S CONTEXT.
  910. *
  911. * Entry condition:
  912. *
  913. * a0: trashed, original value saved on stack (PT_AREG0)
  914. * a1: a1
  915. * a2: new stack pointer, original in DEPC
  916. * a3: a3
  917. * depc: a2, original value saved on stack (PT_DEPC)
  918. * excsave_1: dispatch table
  919. */
  920. ENTRY(fast_syscall_user)
  921. /* Skip syscall. */
  922. rsr a0, epc1
  923. addi a0, a0, 3
  924. wsr a0, epc1
  925. l32i a0, a2, PT_DEPC
  926. bgeui a0, VALID_DOUBLE_EXCEPTION_ADDRESS, fast_syscall_unrecoverable
  927. rsr a0, depc # get syscall-nr
  928. _beqz a0, fast_syscall_spill_registers
  929. _beqi a0, __NR_xtensa, fast_syscall_xtensa
  930. call0 user_exception
  931. ENDPROC(fast_syscall_user)
  932. ENTRY(fast_syscall_unrecoverable)
  933. /* Restore all states. */
  934. l32i a0, a2, PT_AREG0 # restore a0
  935. xsr a2, depc # restore a2, depc
  936. wsr a0, excsave1
  937. call0 unrecoverable_exception
  938. ENDPROC(fast_syscall_unrecoverable)
  939. /*
  940. * sysxtensa syscall handler
  941. *
  942. * int sysxtensa (SYS_XTENSA_ATOMIC_SET, ptr, val, unused);
  943. * int sysxtensa (SYS_XTENSA_ATOMIC_ADD, ptr, val, unused);
  944. * int sysxtensa (SYS_XTENSA_ATOMIC_EXG_ADD, ptr, val, unused);
  945. * int sysxtensa (SYS_XTENSA_ATOMIC_CMP_SWP, ptr, oldval, newval);
  946. * a2 a6 a3 a4 a5
  947. *
  948. * Entry condition:
  949. *
  950. * a0: a2 (syscall-nr), original value saved on stack (PT_AREG0)
  951. * a1: a1
  952. * a2: new stack pointer, original in a0 and DEPC
  953. * a3: a3
  954. * a4..a15: unchanged
  955. * depc: a2, original value saved on stack (PT_DEPC)
  956. * excsave_1: dispatch table
  957. *
  958. * PT_DEPC >= VALID_DOUBLE_EXCEPTION_ADDRESS: double exception, DEPC
  959. * < VALID_DOUBLE_EXCEPTION_ADDRESS: regular exception
  960. *
  961. * Note: we don't have to save a2; a2 holds the return value
  962. */
  963. .literal_position
  964. #ifdef CONFIG_FAST_SYSCALL_XTENSA
  965. ENTRY(fast_syscall_xtensa)
  966. s32i a7, a2, PT_AREG7 # we need an additional register
  967. movi a7, 4 # sizeof(unsigned int)
  968. access_ok a3, a7, a0, a2, .Leac # a0: scratch reg, a2: sp
  969. _bgeui a6, SYS_XTENSA_COUNT, .Lill
  970. _bnei a6, SYS_XTENSA_ATOMIC_CMP_SWP, .Lnswp
  971. /* Fall through for ATOMIC_CMP_SWP. */
  972. .Lswp: /* Atomic compare and swap */
  973. EX(.Leac) l32i a0, a3, 0 # read old value
  974. bne a0, a4, 1f # same as old value? jump
  975. EX(.Leac) s32i a5, a3, 0 # different, modify value
  976. l32i a7, a2, PT_AREG7 # restore a7
  977. l32i a0, a2, PT_AREG0 # restore a0
  978. movi a2, 1 # and return 1
  979. rfe
  980. 1: l32i a7, a2, PT_AREG7 # restore a7
  981. l32i a0, a2, PT_AREG0 # restore a0
  982. movi a2, 0 # return 0 (note that we cannot set
  983. rfe
  984. .Lnswp: /* Atomic set, add, and exg_add. */
  985. EX(.Leac) l32i a7, a3, 0 # orig
  986. addi a6, a6, -SYS_XTENSA_ATOMIC_SET
  987. add a0, a4, a7 # + arg
  988. moveqz a0, a4, a6 # set
  989. addi a6, a6, SYS_XTENSA_ATOMIC_SET
  990. EX(.Leac) s32i a0, a3, 0 # write new value
  991. mov a0, a2
  992. mov a2, a7
  993. l32i a7, a0, PT_AREG7 # restore a7
  994. l32i a0, a0, PT_AREG0 # restore a0
  995. rfe
  996. .Leac: l32i a7, a2, PT_AREG7 # restore a7
  997. l32i a0, a2, PT_AREG0 # restore a0
  998. movi a2, -EFAULT
  999. rfe
  1000. .Lill: l32i a7, a2, PT_AREG7 # restore a7
  1001. l32i a0, a2, PT_AREG0 # restore a0
  1002. movi a2, -EINVAL
  1003. rfe
  1004. ENDPROC(fast_syscall_xtensa)
  1005. #else /* CONFIG_FAST_SYSCALL_XTENSA */
  1006. ENTRY(fast_syscall_xtensa)
  1007. l32i a0, a2, PT_AREG0 # restore a0
  1008. movi a2, -ENOSYS
  1009. rfe
  1010. ENDPROC(fast_syscall_xtensa)
  1011. #endif /* CONFIG_FAST_SYSCALL_XTENSA */
  1012. /* fast_syscall_spill_registers.
  1013. *
  1014. * Entry condition:
  1015. *
  1016. * a0: trashed, original value saved on stack (PT_AREG0)
  1017. * a1: a1
  1018. * a2: new stack pointer, original in DEPC
  1019. * a3: a3
  1020. * depc: a2, original value saved on stack (PT_DEPC)
  1021. * excsave_1: dispatch table
  1022. *
  1023. * Note: We assume the stack pointer is EXC_TABLE_KSTK in the fixup handler.
  1024. */
  1025. #if defined(CONFIG_FAST_SYSCALL_SPILL_REGISTERS) && \
  1026. defined(USER_SUPPORT_WINDOWED)
  1027. ENTRY(fast_syscall_spill_registers)
  1028. /* Register a FIXUP handler (pass current wb as a parameter) */
  1029. xsr a3, excsave1
  1030. movi a0, fast_syscall_spill_registers_fixup
  1031. s32i a0, a3, EXC_TABLE_FIXUP
  1032. rsr a0, windowbase
  1033. s32i a0, a3, EXC_TABLE_PARAM
  1034. xsr a3, excsave1 # restore a3 and excsave_1
  1035. /* Save a3, a4 and SAR on stack. */
  1036. rsr a0, sar
  1037. s32i a3, a2, PT_AREG3
  1038. s32i a0, a2, PT_SAR
  1039. /* The spill routine might clobber a4, a7, a8, a11, a12, and a15. */
  1040. s32i a4, a2, PT_AREG4
  1041. s32i a7, a2, PT_AREG7
  1042. s32i a8, a2, PT_AREG8
  1043. s32i a11, a2, PT_AREG11
  1044. s32i a12, a2, PT_AREG12
  1045. s32i a15, a2, PT_AREG15
  1046. /*
  1047. * Rotate ws so that the current windowbase is at bit 0.
  1048. * Assume ws = xxxwww1yy (www1 current window frame).
  1049. * Rotate ws right so that a4 = yyxxxwww1.
  1050. */
  1051. rsr a0, windowbase
  1052. rsr a3, windowstart # a3 = xxxwww1yy
  1053. ssr a0 # holds WB
  1054. slli a0, a3, WSBITS
  1055. or a3, a3, a0 # a3 = xxxwww1yyxxxwww1yy
  1056. srl a3, a3 # a3 = 00xxxwww1yyxxxwww1
  1057. /* We are done if there are no more than the current register frame. */
  1058. extui a3, a3, 1, WSBITS-1 # a3 = 0yyxxxwww
  1059. movi a0, (1 << (WSBITS-1))
  1060. _beqz a3, .Lnospill # only one active frame? jump
  1061. /* We want 1 at the top, so that we return to the current windowbase */
  1062. or a3, a3, a0 # 1yyxxxwww
  1063. /* Skip empty frames - get 'oldest' WINDOWSTART-bit. */
  1064. wsr a3, windowstart # save shifted windowstart
  1065. neg a0, a3
  1066. and a3, a0, a3 # first bit set from right: 000010000
  1067. ffs_ws a0, a3 # a0: shifts to skip empty frames
  1068. movi a3, WSBITS
  1069. sub a0, a3, a0 # WSBITS-a0:number of 0-bits from right
  1070. ssr a0 # save in SAR for later.
  1071. rsr a3, windowbase
  1072. add a3, a3, a0
  1073. wsr a3, windowbase
  1074. rsync
  1075. rsr a3, windowstart
  1076. srl a3, a3 # shift windowstart
  1077. /* WB is now just one frame below the oldest frame in the register
  1078. window. WS is shifted so the oldest frame is in bit 0, thus, WB
  1079. and WS differ by one 4-register frame. */
  1080. /* Save frames. Depending what call was used (call4, call8, call12),
  1081. * we have to save 4,8. or 12 registers.
  1082. */
  1083. .Lloop: _bbsi.l a3, 1, .Lc4
  1084. _bbci.l a3, 2, .Lc12
  1085. .Lc8: s32e a4, a13, -16
  1086. l32e a4, a5, -12
  1087. s32e a8, a4, -32
  1088. s32e a5, a13, -12
  1089. s32e a6, a13, -8
  1090. s32e a7, a13, -4
  1091. s32e a9, a4, -28
  1092. s32e a10, a4, -24
  1093. s32e a11, a4, -20
  1094. srli a11, a3, 2 # shift windowbase by 2
  1095. rotw 2
  1096. _bnei a3, 1, .Lloop
  1097. j .Lexit
  1098. .Lc4: s32e a4, a9, -16
  1099. s32e a5, a9, -12
  1100. s32e a6, a9, -8
  1101. s32e a7, a9, -4
  1102. srli a7, a3, 1
  1103. rotw 1
  1104. _bnei a3, 1, .Lloop
  1105. j .Lexit
  1106. .Lc12: _bbci.l a3, 3, .Linvalid_mask # bit 2 shouldn't be zero!
  1107. /* 12-register frame (call12) */
  1108. l32e a0, a5, -12
  1109. s32e a8, a0, -48
  1110. mov a8, a0
  1111. s32e a9, a8, -44
  1112. s32e a10, a8, -40
  1113. s32e a11, a8, -36
  1114. s32e a12, a8, -32
  1115. s32e a13, a8, -28
  1116. s32e a14, a8, -24
  1117. s32e a15, a8, -20
  1118. srli a15, a3, 3
  1119. /* The stack pointer for a4..a7 is out of reach, so we rotate the
  1120. * window, grab the stackpointer, and rotate back.
  1121. * Alternatively, we could also use the following approach, but that
  1122. * makes the fixup routine much more complicated:
  1123. * rotw 1
  1124. * s32e a0, a13, -16
  1125. * ...
  1126. * rotw 2
  1127. */
  1128. rotw 1
  1129. mov a4, a13
  1130. rotw -1
  1131. s32e a4, a8, -16
  1132. s32e a5, a8, -12
  1133. s32e a6, a8, -8
  1134. s32e a7, a8, -4
  1135. rotw 3
  1136. _beqi a3, 1, .Lexit
  1137. j .Lloop
  1138. .Lexit:
  1139. /* Done. Do the final rotation and set WS */
  1140. rotw 1
  1141. rsr a3, windowbase
  1142. ssl a3
  1143. movi a3, 1
  1144. sll a3, a3
  1145. wsr a3, windowstart
  1146. .Lnospill:
  1147. /* Advance PC, restore registers and SAR, and return from exception. */
  1148. l32i a3, a2, PT_SAR
  1149. l32i a0, a2, PT_AREG0
  1150. wsr a3, sar
  1151. l32i a3, a2, PT_AREG3
  1152. /* Restore clobbered registers. */
  1153. l32i a4, a2, PT_AREG4
  1154. l32i a7, a2, PT_AREG7
  1155. l32i a8, a2, PT_AREG8
  1156. l32i a11, a2, PT_AREG11
  1157. l32i a12, a2, PT_AREG12
  1158. l32i a15, a2, PT_AREG15
  1159. movi a2, 0
  1160. rfe
  1161. .Linvalid_mask:
  1162. /* We get here because of an unrecoverable error in the window
  1163. * registers, so set up a dummy frame and kill the user application.
  1164. * Note: We assume EXC_TABLE_KSTK contains a valid stack pointer.
  1165. */
  1166. movi a0, 1
  1167. movi a1, 0
  1168. wsr a0, windowstart
  1169. wsr a1, windowbase
  1170. rsync
  1171. movi a0, 0
  1172. rsr a3, excsave1
  1173. l32i a1, a3, EXC_TABLE_KSTK
  1174. movi a4, KERNEL_PS_WOE_MASK | LOCKLEVEL
  1175. wsr a4, ps
  1176. rsync
  1177. movi abi_arg0, SIGSEGV
  1178. abi_call make_task_dead
  1179. /* shouldn't return, so panic */
  1180. wsr a0, excsave1
  1181. call0 unrecoverable_exception # should not return
  1182. 1: j 1b
  1183. ENDPROC(fast_syscall_spill_registers)
  1184. /* Fixup handler.
  1185. *
  1186. * We get here if the spill routine causes an exception, e.g. tlb miss.
  1187. * We basically restore WINDOWBASE and WINDOWSTART to the condition when
  1188. * we entered the spill routine and jump to the user exception handler.
  1189. *
  1190. * Note that we only need to restore the bits in windowstart that have not
  1191. * been spilled yet by the _spill_register routine. Luckily, a3 contains a
  1192. * rotated windowstart with only those bits set for frames that haven't been
  1193. * spilled yet. Because a3 is rotated such that bit 0 represents the register
  1194. * frame for the current windowbase - 1, we need to rotate a3 left by the
  1195. * value of the current windowbase + 1 and move it to windowstart.
  1196. *
  1197. * a0: value of depc, original value in depc
  1198. * a2: trashed, original value in EXC_TABLE_DOUBLE_SAVE
  1199. * a3: exctable, original value in excsave1
  1200. */
  1201. ENTRY(fast_syscall_spill_registers_fixup)
  1202. rsr a2, windowbase # get current windowbase (a2 is saved)
  1203. xsr a0, depc # restore depc and a0
  1204. ssl a2 # set shift (32 - WB)
  1205. /* We need to make sure the current registers (a0-a3) are preserved.
  1206. * To do this, we simply set the bit for the current window frame
  1207. * in WS, so that the exception handlers save them to the task stack.
  1208. *
  1209. * Note: we use a3 to set the windowbase, so we take a special care
  1210. * of it, saving it in the original _spill_registers frame across
  1211. * the exception handler call.
  1212. */
  1213. xsr a3, excsave1 # get spill-mask
  1214. slli a3, a3, 1 # shift left by one
  1215. addi a3, a3, 1 # set the bit for the current window frame
  1216. slli a2, a3, 32-WSBITS
  1217. src a2, a3, a2 # a2 = xxwww1yyxxxwww1yy......
  1218. wsr a2, windowstart # set corrected windowstart
  1219. srli a3, a3, 1
  1220. rsr a2, excsave1
  1221. l32i a2, a2, EXC_TABLE_DOUBLE_SAVE # restore a2
  1222. xsr a2, excsave1
  1223. s32i a3, a2, EXC_TABLE_DOUBLE_SAVE # save a3
  1224. l32i a3, a2, EXC_TABLE_PARAM # original WB (in user task)
  1225. xsr a2, excsave1
  1226. /* Return to the original (user task) WINDOWBASE.
  1227. * We leave the following frame behind:
  1228. * a0, a1, a2 same
  1229. * a3: trashed (saved in EXC_TABLE_DOUBLE_SAVE)
  1230. * depc: depc (we have to return to that address)
  1231. * excsave_1: exctable
  1232. */
  1233. wsr a3, windowbase
  1234. rsync
  1235. /* We are now in the original frame when we entered _spill_registers:
  1236. * a0: return address
  1237. * a1: used, stack pointer
  1238. * a2: kernel stack pointer
  1239. * a3: available
  1240. * depc: exception address
  1241. * excsave: exctable
  1242. * Note: This frame might be the same as above.
  1243. */
  1244. /* Setup stack pointer. */
  1245. addi a2, a2, -PT_USER_SIZE
  1246. s32i a0, a2, PT_AREG0
  1247. /* Make sure we return to this fixup handler. */
  1248. movi a3, fast_syscall_spill_registers_fixup_return
  1249. s32i a3, a2, PT_DEPC # setup depc
  1250. /* Jump to the exception handler. */
  1251. rsr a3, excsave1
  1252. rsr a0, exccause
  1253. addx4 a0, a0, a3 # find entry in table
  1254. l32i a0, a0, EXC_TABLE_FAST_USER # load handler
  1255. l32i a3, a3, EXC_TABLE_DOUBLE_SAVE
  1256. jx a0
  1257. ENDPROC(fast_syscall_spill_registers_fixup)
  1258. ENTRY(fast_syscall_spill_registers_fixup_return)
  1259. /* When we return here, all registers have been restored (a2: DEPC) */
  1260. wsr a2, depc # exception address
  1261. /* Restore fixup handler. */
  1262. rsr a2, excsave1
  1263. s32i a3, a2, EXC_TABLE_DOUBLE_SAVE
  1264. movi a3, fast_syscall_spill_registers_fixup
  1265. s32i a3, a2, EXC_TABLE_FIXUP
  1266. rsr a3, windowbase
  1267. s32i a3, a2, EXC_TABLE_PARAM
  1268. l32i a2, a2, EXC_TABLE_KSTK
  1269. /* Load WB at the time the exception occurred. */
  1270. rsr a3, sar # WB is still in SAR
  1271. neg a3, a3
  1272. wsr a3, windowbase
  1273. rsync
  1274. rsr a3, excsave1
  1275. l32i a3, a3, EXC_TABLE_DOUBLE_SAVE
  1276. rfde
  1277. ENDPROC(fast_syscall_spill_registers_fixup_return)
  1278. #else /* CONFIG_FAST_SYSCALL_SPILL_REGISTERS */
  1279. ENTRY(fast_syscall_spill_registers)
  1280. l32i a0, a2, PT_AREG0 # restore a0
  1281. movi a2, -ENOSYS
  1282. rfe
  1283. ENDPROC(fast_syscall_spill_registers)
  1284. #endif /* CONFIG_FAST_SYSCALL_SPILL_REGISTERS */
  1285. #ifdef CONFIG_MMU
  1286. /*
  1287. * We should never get here. Bail out!
  1288. */
  1289. ENTRY(fast_second_level_miss_double_kernel)
  1290. 1:
  1291. call0 unrecoverable_exception # should not return
  1292. 1: j 1b
  1293. ENDPROC(fast_second_level_miss_double_kernel)
  1294. /* First-level entry handler for user, kernel, and double 2nd-level
  1295. * TLB miss exceptions. Note that for now, user and kernel miss
  1296. * exceptions share the same entry point and are handled identically.
  1297. *
  1298. * An old, less-efficient C version of this function used to exist.
  1299. * We include it below, interleaved as comments, for reference.
  1300. *
  1301. * Entry condition:
  1302. *
  1303. * a0: trashed, original value saved on stack (PT_AREG0)
  1304. * a1: a1
  1305. * a2: new stack pointer, original in DEPC
  1306. * a3: a3
  1307. * depc: a2, original value saved on stack (PT_DEPC)
  1308. * excsave_1: dispatch table
  1309. *
  1310. * PT_DEPC >= VALID_DOUBLE_EXCEPTION_ADDRESS: double exception, DEPC
  1311. * < VALID_DOUBLE_EXCEPTION_ADDRESS: regular exception
  1312. */
  1313. ENTRY(fast_second_level_miss)
  1314. /* Save a1 and a3. Note: we don't expect a double exception. */
  1315. s32i a1, a2, PT_AREG1
  1316. s32i a3, a2, PT_AREG3
  1317. /* We need to map the page of PTEs for the user task. Find
  1318. * the pointer to that page. Also, it's possible for tsk->mm
  1319. * to be NULL while tsk->active_mm is nonzero if we faulted on
  1320. * a vmalloc address. In that rare case, we must use
  1321. * active_mm instead to avoid a fault in this handler. See
  1322. *
  1323. * http://mail.nl.linux.org/linux-mm/2002-08/msg00258.html
  1324. * (or search Internet on "mm vs. active_mm")
  1325. *
  1326. * if (!mm)
  1327. * mm = tsk->active_mm;
  1328. * pgd = pgd_offset (mm, regs->excvaddr);
  1329. * pmd = pmd_offset (pgd, regs->excvaddr);
  1330. * pmdval = *pmd;
  1331. */
  1332. GET_CURRENT(a1,a2)
  1333. l32i a0, a1, TASK_MM # tsk->mm
  1334. beqz a0, .Lfast_second_level_miss_no_mm
  1335. .Lfast_second_level_miss_continue:
  1336. rsr a3, excvaddr # fault address
  1337. _PGD_OFFSET(a0, a3, a1)
  1338. l32i a0, a0, 0 # read pmdval
  1339. beqz a0, .Lfast_second_level_miss_no_pmd
  1340. /* Read ptevaddr and convert to top of page-table page.
  1341. *
  1342. * vpnval = read_ptevaddr_register() & PAGE_MASK;
  1343. * vpnval += DTLB_WAY_PGTABLE;
  1344. * pteval = mk_pte (virt_to_page(pmd_val(pmdval)), PAGE_KERNEL);
  1345. * write_dtlb_entry (pteval, vpnval);
  1346. *
  1347. * The messy computation for 'pteval' above really simplifies
  1348. * into the following:
  1349. *
  1350. * pteval = ((pmdval - PAGE_OFFSET + PHYS_OFFSET) & PAGE_MASK)
  1351. * | PAGE_DIRECTORY
  1352. */
  1353. movi a1, (PHYS_OFFSET - PAGE_OFFSET) & 0xffffffff
  1354. add a0, a0, a1 # pmdval - PAGE_OFFSET
  1355. extui a1, a0, 0, PAGE_SHIFT # ... & PAGE_MASK
  1356. xor a0, a0, a1
  1357. movi a1, _PAGE_DIRECTORY
  1358. or a0, a0, a1 # ... | PAGE_DIRECTORY
  1359. /*
  1360. * We utilize all three wired-ways (7-9) to hold pmd translations.
  1361. * Memory regions are mapped to the DTLBs according to bits 28 and 29.
  1362. * This allows to map the three most common regions to three different
  1363. * DTLBs:
  1364. * 0,1 -> way 7 program (0040.0000) and virtual (c000.0000)
  1365. * 2 -> way 8 shared libaries (2000.0000)
  1366. * 3 -> way 0 stack (3000.0000)
  1367. */
  1368. extui a3, a3, 28, 2 # addr. bit 28 and 29 0,1,2,3
  1369. rsr a1, ptevaddr
  1370. addx2 a3, a3, a3 # -> 0,3,6,9
  1371. srli a1, a1, PAGE_SHIFT
  1372. extui a3, a3, 2, 2 # -> 0,0,1,2
  1373. slli a1, a1, PAGE_SHIFT # ptevaddr & PAGE_MASK
  1374. addi a3, a3, DTLB_WAY_PGD
  1375. add a1, a1, a3 # ... + way_number
  1376. .Lfast_second_level_miss_wdtlb:
  1377. wdtlb a0, a1
  1378. dsync
  1379. /* Exit critical section. */
  1380. .Lfast_second_level_miss_skip_wdtlb:
  1381. rsr a3, excsave1
  1382. movi a0, 0
  1383. s32i a0, a3, EXC_TABLE_FIXUP
  1384. /* Restore the working registers, and return. */
  1385. l32i a0, a2, PT_AREG0
  1386. l32i a1, a2, PT_AREG1
  1387. l32i a3, a2, PT_AREG3
  1388. l32i a2, a2, PT_DEPC
  1389. bgeui a2, VALID_DOUBLE_EXCEPTION_ADDRESS, 1f
  1390. /* Restore excsave1 and return. */
  1391. rsr a2, depc
  1392. rfe
  1393. /* Return from double exception. */
  1394. 1: xsr a2, depc
  1395. esync
  1396. rfde
  1397. .Lfast_second_level_miss_no_mm:
  1398. l32i a0, a1, TASK_ACTIVE_MM # unlikely case mm == 0
  1399. bnez a0, .Lfast_second_level_miss_continue
  1400. /* Even more unlikely case active_mm == 0.
  1401. * We can get here with NMI in the middle of context_switch that
  1402. * touches vmalloc area.
  1403. */
  1404. movi a0, init_mm
  1405. j .Lfast_second_level_miss_continue
  1406. .Lfast_second_level_miss_no_pmd:
  1407. #if (DCACHE_WAY_SIZE > PAGE_SIZE)
  1408. /* Special case for cache aliasing.
  1409. * We (should) only get here if a clear_user_page, copy_user_page
  1410. * or the aliased cache flush functions got preemptively interrupted
  1411. * by another task. Re-establish temporary mapping to the
  1412. * TLBTEMP_BASE areas.
  1413. */
  1414. /* We shouldn't be in a double exception */
  1415. l32i a0, a2, PT_DEPC
  1416. bgeui a0, VALID_DOUBLE_EXCEPTION_ADDRESS, .Lfast_second_level_miss_slow
  1417. /* Make sure the exception originated in the special functions */
  1418. movi a0, __tlbtemp_mapping_start
  1419. rsr a3, epc1
  1420. bltu a3, a0, .Lfast_second_level_miss_slow
  1421. movi a0, __tlbtemp_mapping_end
  1422. bgeu a3, a0, .Lfast_second_level_miss_slow
  1423. /* Check if excvaddr was in one of the TLBTEMP_BASE areas. */
  1424. movi a3, TLBTEMP_BASE_1
  1425. rsr a0, excvaddr
  1426. bltu a0, a3, .Lfast_second_level_miss_slow
  1427. addi a1, a0, -TLBTEMP_SIZE
  1428. bgeu a1, a3, .Lfast_second_level_miss_slow
  1429. /* Check if we have to restore an ITLB mapping. */
  1430. movi a1, __tlbtemp_mapping_itlb
  1431. rsr a3, epc1
  1432. sub a3, a3, a1
  1433. /* Calculate VPN */
  1434. movi a1, PAGE_MASK
  1435. and a1, a1, a0
  1436. /* Jump for ITLB entry */
  1437. bgez a3, 1f
  1438. /* We can use up to two TLBTEMP areas, one for src and one for dst. */
  1439. extui a3, a0, PAGE_SHIFT + DCACHE_ALIAS_ORDER, 1
  1440. add a1, a3, a1
  1441. /* PPN is in a6 for the first TLBTEMP area and in a7 for the second. */
  1442. mov a0, a6
  1443. movnez a0, a7, a3
  1444. j .Lfast_second_level_miss_wdtlb
  1445. /* ITLB entry. We only use dst in a6. */
  1446. 1: witlb a6, a1
  1447. isync
  1448. j .Lfast_second_level_miss_skip_wdtlb
  1449. #endif // DCACHE_WAY_SIZE > PAGE_SIZE
  1450. /* Invalid PGD, default exception handling */
  1451. .Lfast_second_level_miss_slow:
  1452. rsr a1, depc
  1453. s32i a1, a2, PT_AREG2
  1454. mov a1, a2
  1455. rsr a2, ps
  1456. bbsi.l a2, PS_UM_BIT, 1f
  1457. call0 _kernel_exception
  1458. 1: call0 _user_exception
  1459. ENDPROC(fast_second_level_miss)
  1460. /*
  1461. * StoreProhibitedException
  1462. *
  1463. * Update the pte and invalidate the itlb mapping for this pte.
  1464. *
  1465. * Entry condition:
  1466. *
  1467. * a0: trashed, original value saved on stack (PT_AREG0)
  1468. * a1: a1
  1469. * a2: new stack pointer, original in DEPC
  1470. * a3: a3
  1471. * depc: a2, original value saved on stack (PT_DEPC)
  1472. * excsave_1: dispatch table
  1473. *
  1474. * PT_DEPC >= VALID_DOUBLE_EXCEPTION_ADDRESS: double exception, DEPC
  1475. * < VALID_DOUBLE_EXCEPTION_ADDRESS: regular exception
  1476. */
  1477. ENTRY(fast_store_prohibited)
  1478. /* Save a1 and a3. */
  1479. s32i a1, a2, PT_AREG1
  1480. s32i a3, a2, PT_AREG3
  1481. GET_CURRENT(a1,a2)
  1482. l32i a0, a1, TASK_MM # tsk->mm
  1483. beqz a0, .Lfast_store_no_mm
  1484. .Lfast_store_continue:
  1485. rsr a1, excvaddr # fault address
  1486. _PGD_OFFSET(a0, a1, a3)
  1487. l32i a0, a0, 0
  1488. beqz a0, .Lfast_store_slow
  1489. /*
  1490. * Note that we test _PAGE_WRITABLE_BIT only if PTE is present
  1491. * and is not PAGE_NONE. See pgtable.h for possible PTE layouts.
  1492. */
  1493. _PTE_OFFSET(a0, a1, a3)
  1494. l32i a3, a0, 0 # read pteval
  1495. movi a1, _PAGE_CA_INVALID
  1496. ball a3, a1, .Lfast_store_slow
  1497. bbci.l a3, _PAGE_WRITABLE_BIT, .Lfast_store_slow
  1498. movi a1, _PAGE_ACCESSED | _PAGE_DIRTY | _PAGE_HW_WRITE
  1499. or a3, a3, a1
  1500. rsr a1, excvaddr
  1501. s32i a3, a0, 0
  1502. /* We need to flush the cache if we have page coloring. */
  1503. #if (DCACHE_WAY_SIZE > PAGE_SIZE) && XCHAL_DCACHE_IS_WRITEBACK
  1504. dhwb a0, 0
  1505. #endif
  1506. pdtlb a0, a1
  1507. wdtlb a3, a0
  1508. /* Exit critical section. */
  1509. movi a0, 0
  1510. rsr a3, excsave1
  1511. s32i a0, a3, EXC_TABLE_FIXUP
  1512. /* Restore the working registers, and return. */
  1513. l32i a3, a2, PT_AREG3
  1514. l32i a1, a2, PT_AREG1
  1515. l32i a0, a2, PT_AREG0
  1516. l32i a2, a2, PT_DEPC
  1517. bgeui a2, VALID_DOUBLE_EXCEPTION_ADDRESS, 1f
  1518. rsr a2, depc
  1519. rfe
  1520. /* Double exception. Restore FIXUP handler and return. */
  1521. 1: xsr a2, depc
  1522. esync
  1523. rfde
  1524. .Lfast_store_no_mm:
  1525. l32i a0, a1, TASK_ACTIVE_MM # unlikely case mm == 0
  1526. j .Lfast_store_continue
  1527. /* If there was a problem, handle fault in C */
  1528. .Lfast_store_slow:
  1529. rsr a1, excvaddr
  1530. pdtlb a0, a1
  1531. bbci.l a0, DTLB_HIT_BIT, 1f
  1532. idtlb a0
  1533. 1:
  1534. rsr a3, depc # still holds a2
  1535. s32i a3, a2, PT_AREG2
  1536. mov a1, a2
  1537. rsr a2, ps
  1538. bbsi.l a2, PS_UM_BIT, 1f
  1539. call0 _kernel_exception
  1540. 1: call0 _user_exception
  1541. ENDPROC(fast_store_prohibited)
  1542. #endif /* CONFIG_MMU */
  1543. .text
  1544. /*
  1545. * System Calls.
  1546. *
  1547. * void system_call (struct pt_regs* regs, int exccause)
  1548. * a2 a3
  1549. */
  1550. .literal_position
  1551. ENTRY(system_call)
  1552. #if defined(__XTENSA_WINDOWED_ABI__)
  1553. abi_entry_default
  1554. #elif defined(__XTENSA_CALL0_ABI__)
  1555. abi_entry(12)
  1556. s32i a0, sp, 0
  1557. s32i abi_saved0, sp, 4
  1558. s32i abi_saved1, sp, 8
  1559. mov abi_saved0, a2
  1560. #else
  1561. #error Unsupported Xtensa ABI
  1562. #endif
  1563. /* regs->syscall = regs->areg[2] */
  1564. l32i a7, abi_saved0, PT_AREG2
  1565. s32i a7, abi_saved0, PT_SYSCALL
  1566. GET_THREAD_INFO(a4, a1)
  1567. l32i abi_saved1, a4, TI_FLAGS
  1568. movi a4, _TIF_WORK_MASK
  1569. and abi_saved1, abi_saved1, a4
  1570. beqz abi_saved1, 1f
  1571. mov abi_arg0, abi_saved0
  1572. abi_call do_syscall_trace_enter
  1573. beqz abi_rv, .Lsyscall_exit
  1574. l32i a7, abi_saved0, PT_SYSCALL
  1575. 1:
  1576. /* syscall = sys_call_table[syscall_nr] */
  1577. movi a4, sys_call_table
  1578. movi a5, __NR_syscalls
  1579. movi abi_rv, -ENOSYS
  1580. bgeu a7, a5, 1f
  1581. addx4 a4, a7, a4
  1582. l32i abi_tmp0, a4, 0
  1583. /* Load args: arg0 - arg5 are passed via regs. */
  1584. l32i abi_arg0, abi_saved0, PT_AREG6
  1585. l32i abi_arg1, abi_saved0, PT_AREG3
  1586. l32i abi_arg2, abi_saved0, PT_AREG4
  1587. l32i abi_arg3, abi_saved0, PT_AREG5
  1588. l32i abi_arg4, abi_saved0, PT_AREG8
  1589. l32i abi_arg5, abi_saved0, PT_AREG9
  1590. abi_callx abi_tmp0
  1591. 1: /* regs->areg[2] = return_value */
  1592. s32i abi_rv, abi_saved0, PT_AREG2
  1593. bnez abi_saved1, 1f
  1594. .Lsyscall_exit:
  1595. #if defined(__XTENSA_WINDOWED_ABI__)
  1596. abi_ret_default
  1597. #elif defined(__XTENSA_CALL0_ABI__)
  1598. l32i a0, sp, 0
  1599. l32i abi_saved0, sp, 4
  1600. l32i abi_saved1, sp, 8
  1601. abi_ret(12)
  1602. #else
  1603. #error Unsupported Xtensa ABI
  1604. #endif
  1605. 1:
  1606. mov abi_arg0, abi_saved0
  1607. abi_call do_syscall_trace_leave
  1608. j .Lsyscall_exit
  1609. ENDPROC(system_call)
  1610. /*
  1611. * Spill live registers on the kernel stack macro.
  1612. *
  1613. * Entry condition: ps.woe is set, ps.excm is cleared
  1614. * Exit condition: windowstart has single bit set
  1615. * May clobber: a12, a13
  1616. */
  1617. .macro spill_registers_kernel
  1618. #if XCHAL_NUM_AREGS > 16
  1619. call12 1f
  1620. _j 2f
  1621. retw
  1622. .align 4
  1623. 1:
  1624. _entry a1, 48
  1625. addi a12, a0, 3
  1626. #if XCHAL_NUM_AREGS > 32
  1627. .rept (XCHAL_NUM_AREGS - 32) / 12
  1628. _entry a1, 48
  1629. mov a12, a0
  1630. .endr
  1631. #endif
  1632. _entry a1, 16
  1633. #if XCHAL_NUM_AREGS % 12 == 0
  1634. mov a8, a8
  1635. #elif XCHAL_NUM_AREGS % 12 == 4
  1636. mov a12, a12
  1637. #elif XCHAL_NUM_AREGS % 12 == 8
  1638. mov a4, a4
  1639. #endif
  1640. retw
  1641. 2:
  1642. #else
  1643. mov a12, a12
  1644. #endif
  1645. .endm
  1646. /*
  1647. * Task switch.
  1648. *
  1649. * struct task* _switch_to (struct task* prev, struct task* next)
  1650. * a2 a2 a3
  1651. */
  1652. ENTRY(_switch_to)
  1653. #if defined(__XTENSA_WINDOWED_ABI__)
  1654. abi_entry(XTENSA_SPILL_STACK_RESERVE)
  1655. #elif defined(__XTENSA_CALL0_ABI__)
  1656. abi_entry(16)
  1657. s32i a12, sp, 0
  1658. s32i a13, sp, 4
  1659. s32i a14, sp, 8
  1660. s32i a15, sp, 12
  1661. #else
  1662. #error Unsupported Xtensa ABI
  1663. #endif
  1664. mov a11, a3 # and 'next' (a3)
  1665. l32i a4, a2, TASK_THREAD_INFO
  1666. l32i a5, a3, TASK_THREAD_INFO
  1667. save_xtregs_user a4 a6 a8 a9 a12 a13 THREAD_XTREGS_USER
  1668. #if THREAD_RA > 1020 || THREAD_SP > 1020
  1669. addi a10, a2, TASK_THREAD
  1670. s32i a0, a10, THREAD_RA - TASK_THREAD # save return address
  1671. s32i a1, a10, THREAD_SP - TASK_THREAD # save stack pointer
  1672. #else
  1673. s32i a0, a2, THREAD_RA # save return address
  1674. s32i a1, a2, THREAD_SP # save stack pointer
  1675. #endif
  1676. #if defined(CONFIG_STACKPROTECTOR) && !defined(CONFIG_SMP)
  1677. movi a6, __stack_chk_guard
  1678. l32i a8, a3, TASK_STACK_CANARY
  1679. s32i a8, a6, 0
  1680. #endif
  1681. /* Disable ints while we manipulate the stack pointer. */
  1682. irq_save a14, a3
  1683. rsync
  1684. /* Switch CPENABLE */
  1685. #if (XTENSA_HAVE_COPROCESSORS || XTENSA_HAVE_IO_PORTS)
  1686. l32i a3, a5, THREAD_CPENABLE
  1687. #ifdef CONFIG_SMP
  1688. beqz a3, 1f
  1689. memw # pairs with memw (2) in fast_coprocessor
  1690. l32i a6, a5, THREAD_CP_OWNER_CPU
  1691. l32i a7, a5, THREAD_CPU
  1692. beq a6, a7, 1f # load 0 into CPENABLE if current CPU is not the owner
  1693. movi a3, 0
  1694. 1:
  1695. #endif
  1696. wsr a3, cpenable
  1697. #endif
  1698. #if XCHAL_HAVE_EXCLUSIVE
  1699. l32i a3, a5, THREAD_ATOMCTL8
  1700. getex a3
  1701. s32i a3, a4, THREAD_ATOMCTL8
  1702. #endif
  1703. /* Flush register file. */
  1704. #if defined(__XTENSA_WINDOWED_ABI__)
  1705. spill_registers_kernel
  1706. #endif
  1707. /* Set kernel stack (and leave critical section)
  1708. * Note: It's save to set it here. The stack will not be overwritten
  1709. * because the kernel stack will only be loaded again after
  1710. * we return from kernel space.
  1711. */
  1712. rsr a3, excsave1 # exc_table
  1713. addi a7, a5, PT_REGS_OFFSET
  1714. s32i a7, a3, EXC_TABLE_KSTK
  1715. /* restore context of the task 'next' */
  1716. l32i a0, a11, THREAD_RA # restore return address
  1717. l32i a1, a11, THREAD_SP # restore stack pointer
  1718. load_xtregs_user a5 a6 a8 a9 a12 a13 THREAD_XTREGS_USER
  1719. wsr a14, ps
  1720. rsync
  1721. #if defined(__XTENSA_WINDOWED_ABI__)
  1722. abi_ret(XTENSA_SPILL_STACK_RESERVE)
  1723. #elif defined(__XTENSA_CALL0_ABI__)
  1724. l32i a12, sp, 0
  1725. l32i a13, sp, 4
  1726. l32i a14, sp, 8
  1727. l32i a15, sp, 12
  1728. abi_ret(16)
  1729. #else
  1730. #error Unsupported Xtensa ABI
  1731. #endif
  1732. ENDPROC(_switch_to)
  1733. ENTRY(ret_from_fork)
  1734. /* void schedule_tail (struct task_struct *prev)
  1735. * Note: prev is still in abi_arg0 (return value from fake call frame)
  1736. */
  1737. abi_call schedule_tail
  1738. mov abi_arg0, a1
  1739. abi_call do_syscall_trace_leave
  1740. j common_exception_return
  1741. ENDPROC(ret_from_fork)
  1742. /*
  1743. * Kernel thread creation helper
  1744. * On entry, set up by copy_thread: abi_saved0 = thread_fn,
  1745. * abi_saved1 = thread_fn arg. Left from _switch_to: abi_arg0 = prev
  1746. */
  1747. ENTRY(ret_from_kernel_thread)
  1748. abi_call schedule_tail
  1749. mov abi_arg0, abi_saved1
  1750. abi_callx abi_saved0
  1751. j common_exception_return
  1752. ENDPROC(ret_from_kernel_thread)
  1753. #ifdef CONFIG_HIBERNATION
  1754. .section .bss, "aw"
  1755. .align 4
  1756. .Lsaved_regs:
  1757. #if defined(__XTENSA_WINDOWED_ABI__)
  1758. .fill 2, 4
  1759. #elif defined(__XTENSA_CALL0_ABI__)
  1760. .fill 6, 4
  1761. #else
  1762. #error Unsupported Xtensa ABI
  1763. #endif
  1764. .align XCHAL_NCP_SA_ALIGN
  1765. .Lsaved_user_regs:
  1766. .fill XTREGS_USER_SIZE, 1
  1767. .previous
  1768. ENTRY(swsusp_arch_suspend)
  1769. abi_entry_default
  1770. movi a2, .Lsaved_regs
  1771. movi a3, .Lsaved_user_regs
  1772. s32i a0, a2, 0
  1773. s32i a1, a2, 4
  1774. save_xtregs_user a3 a4 a5 a6 a7 a8 0
  1775. #if defined(__XTENSA_WINDOWED_ABI__)
  1776. spill_registers_kernel
  1777. #elif defined(__XTENSA_CALL0_ABI__)
  1778. s32i a12, a2, 8
  1779. s32i a13, a2, 12
  1780. s32i a14, a2, 16
  1781. s32i a15, a2, 20
  1782. #else
  1783. #error Unsupported Xtensa ABI
  1784. #endif
  1785. abi_call swsusp_save
  1786. mov a2, abi_rv
  1787. abi_ret_default
  1788. ENDPROC(swsusp_arch_suspend)
  1789. ENTRY(swsusp_arch_resume)
  1790. abi_entry_default
  1791. #if defined(__XTENSA_WINDOWED_ABI__)
  1792. spill_registers_kernel
  1793. #endif
  1794. movi a2, restore_pblist
  1795. l32i a2, a2, 0
  1796. .Lcopy_pbe:
  1797. l32i a3, a2, PBE_ADDRESS
  1798. l32i a4, a2, PBE_ORIG_ADDRESS
  1799. __loopi a3, a9, PAGE_SIZE, 16
  1800. l32i a5, a3, 0
  1801. l32i a6, a3, 4
  1802. l32i a7, a3, 8
  1803. l32i a8, a3, 12
  1804. addi a3, a3, 16
  1805. s32i a5, a4, 0
  1806. s32i a6, a4, 4
  1807. s32i a7, a4, 8
  1808. s32i a8, a4, 12
  1809. addi a4, a4, 16
  1810. __endl a3, a9
  1811. l32i a2, a2, PBE_NEXT
  1812. bnez a2, .Lcopy_pbe
  1813. movi a2, .Lsaved_regs
  1814. movi a3, .Lsaved_user_regs
  1815. l32i a0, a2, 0
  1816. l32i a1, a2, 4
  1817. load_xtregs_user a3 a4 a5 a6 a7 a8 0
  1818. #if defined(__XTENSA_CALL0_ABI__)
  1819. l32i a12, a2, 8
  1820. l32i a13, a2, 12
  1821. l32i a14, a2, 16
  1822. l32i a15, a2, 20
  1823. #endif
  1824. movi a2, 0
  1825. abi_ret_default
  1826. ENDPROC(swsusp_arch_resume)
  1827. #endif